Commit 3abe84ea authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski Committed by Linus Walleij

dt-bindings: pinctrl: qcom: lpass-lpi: correct description of second reg

The description of second IO address is a bit confusing.  It is supposed
to be the MCC range which contains the slew rate registers, not the slew
rate register base.  The Linux driver then accesses slew rate register
with hard-coded offset (0xa000).
Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: default avatarRob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20230302155255.857065-1-krzysztof.kozlowski@linaro.orgSigned-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent 6cf103bc
...@@ -20,7 +20,7 @@ properties: ...@@ -20,7 +20,7 @@ properties:
reg: reg:
items: items:
- description: LPASS LPI TLMM Control and Status registers - description: LPASS LPI TLMM Control and Status registers
- description: LPASS LPI pins SLEW registers - description: LPASS LPI MCC registers
clocks: clocks:
items: items:
......
...@@ -20,7 +20,7 @@ properties: ...@@ -20,7 +20,7 @@ properties:
reg: reg:
items: items:
- description: LPASS LPI TLMM Control and Status registers - description: LPASS LPI TLMM Control and Status registers
- description: LPASS LPI pins SLEW registers - description: LPASS LPI MCC registers
clocks: clocks:
items: items:
......
...@@ -21,7 +21,7 @@ properties: ...@@ -21,7 +21,7 @@ properties:
reg: reg:
items: items:
- description: LPASS LPI TLMM Control and Status registers - description: LPASS LPI TLMM Control and Status registers
- description: LPASS LPI pins SLEW registers - description: LPASS LPI MCC registers
clocks: clocks:
items: items:
......
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