Commit 3afee4ed authored by Leon Romanovsky's avatar Leon Romanovsky Committed by Steffen Klassert

net/mlx5: Add HW definitions for IPsec packet offload

Add all needed bits to support IPsec packet offload mode.
Reviewed-by: default avatarRaed Salem <raeds@nvidia.com>
Reviewed-by: default avatarSaeed Mahameed <saeedm@nvidia.com>
Signed-off-by: default avatarLeon Romanovsky <leonro@nvidia.com>
Signed-off-by: default avatarSteffen Klassert <steffen.klassert@secunet.com>
parent e77bbde7
...@@ -71,6 +71,7 @@ enum { ...@@ -71,6 +71,7 @@ enum {
}; };
enum { enum {
MLX5_ACCESS_ASO_OPC_MOD_IPSEC = 0x0,
MLX5_ACCESS_ASO_OPC_MOD_FLOW_METER = 0x2, MLX5_ACCESS_ASO_OPC_MOD_FLOW_METER = 0x2,
MLX5_ACCESS_ASO_OPC_MOD_MACSEC = 0x5, MLX5_ACCESS_ASO_OPC_MOD_MACSEC = 0x5,
}; };
......
...@@ -445,7 +445,10 @@ struct mlx5_ifc_flow_table_prop_layout_bits { ...@@ -445,7 +445,10 @@ struct mlx5_ifc_flow_table_prop_layout_bits {
u8 max_modify_header_actions[0x8]; u8 max_modify_header_actions[0x8];
u8 max_ft_level[0x8]; u8 max_ft_level[0x8];
u8 reserved_at_40[0x6]; u8 reformat_add_esp_trasport[0x1];
u8 reserved_at_41[0x2];
u8 reformat_del_esp_trasport[0x1];
u8 reserved_at_44[0x2];
u8 execute_aso[0x1]; u8 execute_aso[0x1];
u8 reserved_at_47[0x19]; u8 reserved_at_47[0x19];
...@@ -638,8 +641,10 @@ struct mlx5_ifc_fte_match_set_misc2_bits { ...@@ -638,8 +641,10 @@ struct mlx5_ifc_fte_match_set_misc2_bits {
u8 reserved_at_1a0[0x8]; u8 reserved_at_1a0[0x8];
u8 macsec_syndrome[0x8]; u8 macsec_syndrome[0x8];
u8 ipsec_syndrome[0x8];
u8 reserved_at_1b8[0x8];
u8 reserved_at_1b0[0x50]; u8 reserved_at_1c0[0x40];
}; };
struct mlx5_ifc_fte_match_set_misc3_bits { struct mlx5_ifc_fte_match_set_misc3_bits {
...@@ -6384,6 +6389,9 @@ enum mlx5_reformat_ctx_type { ...@@ -6384,6 +6389,9 @@ enum mlx5_reformat_ctx_type {
MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2,
MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3,
MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4,
MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV4 = 0x5,
MLX5_REFORMAT_TYPE_DEL_ESP_TRANSPORT = 0x8,
MLX5_REFORMAT_TYPE_ADD_ESP_TRANSPORT_OVER_IPV6 = 0xb,
MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf, MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf,
MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10, MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10,
MLX5_REFORMAT_TYPE_ADD_MACSEC = 0x11, MLX5_REFORMAT_TYPE_ADD_MACSEC = 0x11,
...@@ -11563,6 +11571,41 @@ enum { ...@@ -11563,6 +11571,41 @@ enum {
MLX5_IPSEC_OBJECT_ICV_LEN_16B, MLX5_IPSEC_OBJECT_ICV_LEN_16B,
}; };
enum {
MLX5_IPSEC_ASO_REG_C_0_1 = 0x0,
MLX5_IPSEC_ASO_REG_C_2_3 = 0x1,
MLX5_IPSEC_ASO_REG_C_4_5 = 0x2,
MLX5_IPSEC_ASO_REG_C_6_7 = 0x3,
};
enum {
MLX5_IPSEC_ASO_MODE = 0x0,
MLX5_IPSEC_ASO_REPLAY_PROTECTION = 0x1,
MLX5_IPSEC_ASO_INC_SN = 0x2,
};
struct mlx5_ifc_ipsec_aso_bits {
u8 valid[0x1];
u8 reserved_at_201[0x1];
u8 mode[0x2];
u8 window_sz[0x2];
u8 soft_lft_arm[0x1];
u8 hard_lft_arm[0x1];
u8 remove_flow_enable[0x1];
u8 esn_event_arm[0x1];
u8 reserved_at_20a[0x16];
u8 remove_flow_pkt_cnt[0x20];
u8 remove_flow_soft_lft[0x20];
u8 reserved_at_260[0x80];
u8 mode_parameter[0x20];
u8 replay_protection_window[0x100];
};
struct mlx5_ifc_ipsec_obj_bits { struct mlx5_ifc_ipsec_obj_bits {
u8 modify_field_select[0x40]; u8 modify_field_select[0x40];
u8 full_offload[0x1]; u8 full_offload[0x1];
...@@ -11584,7 +11627,11 @@ struct mlx5_ifc_ipsec_obj_bits { ...@@ -11584,7 +11627,11 @@ struct mlx5_ifc_ipsec_obj_bits {
u8 implicit_iv[0x40]; u8 implicit_iv[0x40];
u8 reserved_at_100[0x700]; u8 reserved_at_100[0x8];
u8 ipsec_aso_access_pd[0x18];
u8 reserved_at_120[0xe0];
struct mlx5_ifc_ipsec_aso_bits ipsec_aso;
}; };
struct mlx5_ifc_create_ipsec_obj_in_bits { struct mlx5_ifc_create_ipsec_obj_in_bits {
......
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