Commit 3b45eee8 authored by Dave Stevenson's avatar Dave Stevenson Committed by Maxime Ripard

drm/vc4: dsi: Correct DSI divider calculations

The divider calculations tried to find the divider just faster than the
clock requested. However if it required a divider of 7 then the for loop
aborted without handling the "error" case, and could end up with a clock
lower than requested.

The integer divider from parent PLL to DSI clock is also capable of
going up to /255, not just /7 that the driver was trying.  This allows
for slower link frequencies on the DSI bus where the resolution permits.

Correct the loop so that we always have a clock greater than requested,
and covering the whole range of dividers.

Fixes: 86c1b9ef ("drm/vc4: Adjust modes in DSI to work around the integer PLL divider.")
Signed-off-by: default avatarDave Stevenson <dave.stevenson@raspberrypi.com>
Link: https://lore.kernel.org/r/20220613144800.326124-13-maxime@cerno.techSigned-off-by: default avatarMaxime Ripard <maxime@cerno.tech>
parent 89c4bbe2
...@@ -805,11 +805,9 @@ static bool vc4_dsi_encoder_mode_fixup(struct drm_encoder *encoder, ...@@ -805,11 +805,9 @@ static bool vc4_dsi_encoder_mode_fixup(struct drm_encoder *encoder,
/* Find what divider gets us a faster clock than the requested /* Find what divider gets us a faster clock than the requested
* pixel clock. * pixel clock.
*/ */
for (divider = 1; divider < 8; divider++) { for (divider = 1; divider < 255; divider++) {
if (parent_rate / divider < pll_clock) { if (parent_rate / (divider + 1) < pll_clock)
divider--;
break; break;
}
} }
/* Now that we've picked a PLL divider, calculate back to its /* Now that we've picked a PLL divider, calculate back to its
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment