Commit 3b93fc0f authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski

ARM: dts: exynos: Add cooling levels for Exynos5422/5800 CPUs

On Exynos5422 and Exynos5800 we support 12 cpufreq steps (200-1300 MHz) for LITTLE
and 18 steps for big core (200-1700 MHz). Add respective cooling cells.
Signed-off-by: default avatarKrzysztof Kozlowski <k.kozlowski@samsung.com>
Acked-by: default avatarViresh Kumar <viresh.kumar@linaro.org>
parent 65ebf53f
...@@ -32,6 +32,9 @@ cpu0: cpu@100 { ...@@ -32,6 +32,9 @@ cpu0: cpu@100 {
clock-frequency = <1000000000>; clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>; cci-control-port = <&cci_control0>;
operating-points-v2 = <&cluster_a7_opp_table>; operating-points-v2 = <&cluster_a7_opp_table>;
cooling-min-level = <0>;
cooling-max-level = <11>;
#cooling-cells = <2>; /* min followed by max */
}; };
cpu1: cpu@101 { cpu1: cpu@101 {
...@@ -41,6 +44,9 @@ cpu1: cpu@101 { ...@@ -41,6 +44,9 @@ cpu1: cpu@101 {
clock-frequency = <1000000000>; clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>; cci-control-port = <&cci_control0>;
operating-points-v2 = <&cluster_a7_opp_table>; operating-points-v2 = <&cluster_a7_opp_table>;
cooling-min-level = <0>;
cooling-max-level = <11>;
#cooling-cells = <2>; /* min followed by max */
}; };
cpu2: cpu@102 { cpu2: cpu@102 {
...@@ -50,6 +56,9 @@ cpu2: cpu@102 { ...@@ -50,6 +56,9 @@ cpu2: cpu@102 {
clock-frequency = <1000000000>; clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>; cci-control-port = <&cci_control0>;
operating-points-v2 = <&cluster_a7_opp_table>; operating-points-v2 = <&cluster_a7_opp_table>;
cooling-min-level = <0>;
cooling-max-level = <11>;
#cooling-cells = <2>; /* min followed by max */
}; };
cpu3: cpu@103 { cpu3: cpu@103 {
...@@ -59,6 +68,9 @@ cpu3: cpu@103 { ...@@ -59,6 +68,9 @@ cpu3: cpu@103 {
clock-frequency = <1000000000>; clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>; cci-control-port = <&cci_control0>;
operating-points-v2 = <&cluster_a7_opp_table>; operating-points-v2 = <&cluster_a7_opp_table>;
cooling-min-level = <0>;
cooling-max-level = <11>;
#cooling-cells = <2>; /* min followed by max */
}; };
cpu4: cpu@0 { cpu4: cpu@0 {
...@@ -69,6 +81,9 @@ cpu4: cpu@0 { ...@@ -69,6 +81,9 @@ cpu4: cpu@0 {
clock-frequency = <1800000000>; clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>; cci-control-port = <&cci_control1>;
operating-points-v2 = <&cluster_a15_opp_table>; operating-points-v2 = <&cluster_a15_opp_table>;
cooling-min-level = <0>;
cooling-max-level = <15>;
#cooling-cells = <2>; /* min followed by max */
}; };
cpu5: cpu@1 { cpu5: cpu@1 {
...@@ -78,6 +93,9 @@ cpu5: cpu@1 { ...@@ -78,6 +93,9 @@ cpu5: cpu@1 {
clock-frequency = <1800000000>; clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>; cci-control-port = <&cci_control1>;
operating-points-v2 = <&cluster_a15_opp_table>; operating-points-v2 = <&cluster_a15_opp_table>;
cooling-min-level = <0>;
cooling-max-level = <15>;
#cooling-cells = <2>; /* min followed by max */
}; };
cpu6: cpu@2 { cpu6: cpu@2 {
...@@ -87,6 +105,9 @@ cpu6: cpu@2 { ...@@ -87,6 +105,9 @@ cpu6: cpu@2 {
clock-frequency = <1800000000>; clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>; cci-control-port = <&cci_control1>;
operating-points-v2 = <&cluster_a15_opp_table>; operating-points-v2 = <&cluster_a15_opp_table>;
cooling-min-level = <0>;
cooling-max-level = <15>;
#cooling-cells = <2>; /* min followed by max */
}; };
cpu7: cpu@3 { cpu7: cpu@3 {
...@@ -96,6 +117,9 @@ cpu7: cpu@3 { ...@@ -96,6 +117,9 @@ cpu7: cpu@3 {
clock-frequency = <1800000000>; clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>; cci-control-port = <&cci_control1>;
operating-points-v2 = <&cluster_a15_opp_table>; operating-points-v2 = <&cluster_a15_opp_table>;
cooling-min-level = <0>;
cooling-max-level = <15>;
#cooling-cells = <2>; /* min followed by max */
}; };
}; };
}; };
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