Commit 3be81429 authored by Olof Johansson's avatar Olof Johansson

Merge tag 'imx-fixes-3.19' of...

Merge tag 'imx-fixes-3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into fixes

Merge "ARM: imx: fixes for 3.19" from Shawn Guo:

The i.MX fixes for 3.19:
 - One fix for incorrect i.MX25 SPI1 clock assignment in device tree,
   which causes system hang when accessing SPI1.
 - Correct i.MX6SX QSPI parent clock configuration to fix a kernel Oops.
 - Fix ULPI PHY reset modelling on imx51-babbage board to remove the
   dependency on bootloader for USB3317 ULPI PHY reset.
 - Correct video divider setting on i.MX6Q rev T0 1.0 to fix the issue
   that HDMI is not working at high resolution on T0 1.0.
 - One incremental fix for CODA960 VPU enabling in device tree to
   correct interrupt order.
 - LS1021A SCFG block works in BE mode, add device tree property
   big-endian to make it right.

* tag 'imx-fixes-3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  ARM: dts: imx51-babbage: Fix ULPI PHY reset modelling
  ARM: imx6sx: Set PLL2 as parent of QSPI clocks
  ARM: dts: imx25: Fix the SPI1 clocks
  ARM: clk-imx6q: fix video divider for rev T0 1.0
  ARM: dts: imx6qdl: Fix CODA960 interrupt order
  ARM: ls1021a: dtsi: add 'big-endian' property for scfg node
Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 1591dc44 7a9f0604
...@@ -162,7 +162,7 @@ spi1: cspi@43fa4000 { ...@@ -162,7 +162,7 @@ spi1: cspi@43fa4000 {
#size-cells = <0>; #size-cells = <0>;
compatible = "fsl,imx25-cspi", "fsl,imx35-cspi"; compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
reg = <0x43fa4000 0x4000>; reg = <0x43fa4000 0x4000>;
clocks = <&clks 62>, <&clks 62>; clocks = <&clks 78>, <&clks 78>;
clock-names = "ipg", "per"; clock-names = "ipg", "per";
interrupts = <14>; interrupts = <14>;
status = "disabled"; status = "disabled";
......
...@@ -127,24 +127,12 @@ regulators { ...@@ -127,24 +127,12 @@ regulators {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
reg_usbh1_vbus: regulator@0 { reg_hub_reset: regulator@0 {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbh1reg>;
reg = <0>;
regulator-name = "usbh1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio2 5 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usbotg_vbus: regulator@1 {
compatible = "regulator-fixed"; compatible = "regulator-fixed";
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotgreg>; pinctrl-0 = <&pinctrl_usbotgreg>;
reg = <1>; reg = <0>;
regulator-name = "usbotg_vbus"; regulator-name = "hub_reset";
regulator-min-microvolt = <5000000>; regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>; regulator-max-microvolt = <5000000>;
gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>; gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
...@@ -176,6 +164,7 @@ usbh1phy: usbh1phy@0 { ...@@ -176,6 +164,7 @@ usbh1phy: usbh1phy@0 {
reg = <0>; reg = <0>;
clocks = <&clks IMX5_CLK_DUMMY>; clocks = <&clks IMX5_CLK_DUMMY>;
clock-names = "main_clk"; clock-names = "main_clk";
reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>;
}; };
}; };
}; };
...@@ -419,7 +408,7 @@ &uart3 { ...@@ -419,7 +408,7 @@ &uart3 {
&usbh1 { &usbh1 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbh1>; pinctrl-0 = <&pinctrl_usbh1>;
vbus-supply = <&reg_usbh1_vbus>; vbus-supply = <&reg_hub_reset>;
fsl,usbphy = <&usbh1phy>; fsl,usbphy = <&usbh1phy>;
phy_type = "ulpi"; phy_type = "ulpi";
status = "okay"; status = "okay";
...@@ -429,7 +418,6 @@ &usbotg { ...@@ -429,7 +418,6 @@ &usbotg {
dr_mode = "otg"; dr_mode = "otg";
disable-over-current; disable-over-current;
phy_type = "utmi_wide"; phy_type = "utmi_wide";
vbus-supply = <&reg_usbotg_vbus>;
status = "okay"; status = "okay";
}; };
......
...@@ -335,8 +335,8 @@ spba@0203c000 { ...@@ -335,8 +335,8 @@ spba@0203c000 {
vpu: vpu@02040000 { vpu: vpu@02040000 {
compatible = "cnm,coda960"; compatible = "cnm,coda960";
reg = <0x02040000 0x3c000>; reg = <0x02040000 0x3c000>;
interrupts = <0 3 IRQ_TYPE_LEVEL_HIGH>, interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>,
<0 12 IRQ_TYPE_LEVEL_HIGH>; <0 3 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "bit", "jpeg"; interrupt-names = "bit", "jpeg";
clocks = <&clks IMX6QDL_CLK_VPU_AXI>, clocks = <&clks IMX6QDL_CLK_VPU_AXI>,
<&clks IMX6QDL_CLK_MMDC_CH0_AXI>, <&clks IMX6QDL_CLK_MMDC_CH0_AXI>,
......
...@@ -142,6 +142,7 @@ esdhc: esdhc@1560000 { ...@@ -142,6 +142,7 @@ esdhc: esdhc@1560000 {
scfg: scfg@1570000 { scfg: scfg@1570000 {
compatible = "fsl,ls1021a-scfg", "syscon"; compatible = "fsl,ls1021a-scfg", "syscon";
reg = <0x0 0x1570000 0x0 0x10000>; reg = <0x0 0x1570000 0x0 0x10000>;
big-endian;
}; };
clockgen: clocking@1ee1000 { clockgen: clocking@1ee1000 {
......
...@@ -144,7 +144,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) ...@@ -144,7 +144,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node)
post_div_table[1].div = 1; post_div_table[1].div = 1;
post_div_table[2].div = 1; post_div_table[2].div = 1;
video_div_table[1].div = 1; video_div_table[1].div = 1;
video_div_table[2].div = 1; video_div_table[3].div = 1;
} }
clk[IMX6QDL_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels)); clk[IMX6QDL_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 2, pll_bypass_src_sels, ARRAY_SIZE(pll_bypass_src_sels));
......
...@@ -558,6 +558,9 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) ...@@ -558,6 +558,9 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node)
clk_set_parent(clks[IMX6SX_CLK_GPU_CORE_SEL], clks[IMX6SX_CLK_PLL3_PFD0]); clk_set_parent(clks[IMX6SX_CLK_GPU_CORE_SEL], clks[IMX6SX_CLK_PLL3_PFD0]);
clk_set_parent(clks[IMX6SX_CLK_GPU_AXI_SEL], clks[IMX6SX_CLK_PLL3_PFD0]); clk_set_parent(clks[IMX6SX_CLK_GPU_AXI_SEL], clks[IMX6SX_CLK_PLL3_PFD0]);
clk_set_parent(clks[IMX6SX_CLK_QSPI1_SEL], clks[IMX6SX_CLK_PLL2_BUS]);
clk_set_parent(clks[IMX6SX_CLK_QSPI2_SEL], clks[IMX6SX_CLK_PLL2_BUS]);
/* Set initial power mode */ /* Set initial power mode */
imx6q_set_lpm(WAIT_CLOCKED); imx6q_set_lpm(WAIT_CLOCKED);
} }
......
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