clk: at91: clk-sam9x60-pll: fix mul mask

According to datasheet mul mask is on bits 31..24. Fixes: a436c2a4 ("clk: at91: add sam9x60 PLL driver") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/1595403506-8209-4-git-send-email-claudiu.beznea@microchip.comSigned-off-by: Stephen Boyd <sboyd@kernel.org>

clk: at91: clk-sam9x60-pll: fix mul mask
According to datasheet mul mask is on bits 31..24. Fixes: a436c2a4 ("clk: at91: add sam9x60 PLL driver") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> Link: https://lore.kernel.org/r/1595403506-8209-4-git-send-email-claudiu.beznea@microchip.comSigned-off-by: Stephen Boyd <sboyd@kernel.org>
3bf639a6 · Claudiu Beznea · Stephen Boyd · 83331bfc · 3bf639a6
Commit 3bf639a6 authored Jul 22, 2020 by Claudiu Beznea Committed by Stephen Boyd Jul 24, 2020
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drivers/clk/at91/clk-sam9x60-pll.c drivers/clk/at91/clk-sam9x60-pll.c +1 -1

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--- a/drivers/clk/at91/clk-sam9x60-pll.c
+++ b/drivers/clk/at91/clk-sam9x60-pll.c
@@ -15,7 +15,7 @@
 #include "pmc.h"

 #define	PMC_PLL_CTRL0_DIV_MSK	GENMASK(7, 0)
-#define	PMC_PLL_CTRL1_MUL_MSK	GENMASK(30, 24)
+#define	PMC_PLL_CTRL1_MUL_MSK	GENMASK(31, 24)

 #define PLL_DIV_MAX		(FIELD_GET(PMC_PLL_CTRL0_DIV_MSK, UINT_MAX) + 1)
 #define UPLL_DIV		2