Commit 3c04d845 authored by Myrtle Shah's avatar Myrtle Shah Committed by Palmer Dabbelt

riscv: Fix XIP_FIXUP_FLASH_OFFSET

There were several problems with the calculation. Not only was an 'and'
being computed into t1 but thrown away; but the 'and' itself would
cause problems if the granularity of the XIP physical address was less
than XIP_OFFSET - in my case I had the kernel image at 2MB in SPI flash.

Fixes: f9ace4ed ("riscv: remove .text section size limitation for XIP")
Cc: stable@vger.kernel.org
Signed-off-by: default avatarMyrtle Shah <gatecat@ds0.me>
Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent 6a00ef44
......@@ -22,14 +22,13 @@
add \reg, \reg, t0
.endm
.macro XIP_FIXUP_FLASH_OFFSET reg
la t1, __data_loc
li t0, XIP_OFFSET_MASK
and t1, t1, t0
li t1, XIP_OFFSET
sub t0, t0, t1
sub \reg, \reg, t0
la t0, __data_loc
REG_L t1, _xip_phys_offset
sub \reg, \reg, t1
add \reg, \reg, t0
.endm
_xip_fixup: .dword CONFIG_PHYS_RAM_BASE - CONFIG_XIP_PHYS_ADDR - XIP_OFFSET
_xip_phys_offset: .dword CONFIG_XIP_PHYS_ADDR + XIP_OFFSET
#else
.macro XIP_FIXUP_OFFSET reg
.endm
......
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