Commit 3c3a7e61 authored by Rex Zhu's avatar Rex Zhu Committed by Alex Deucher

drm/amdgpu: fix bug mclk can't change on Polaris

the root cause is we gate the clock to uvd vcpu.
mclk's change should need the response from uvd if
it is power on.
Signed-off-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Acked-by: default avatarChristian König <christian.koenig@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 805b3ba8
...@@ -640,7 +640,7 @@ static void uvd_v5_0_enable_clock_gating(struct amdgpu_device *adev, bool enable ...@@ -640,7 +640,7 @@ static void uvd_v5_0_enable_clock_gating(struct amdgpu_device *adev, bool enable
UVD_SUVD_CGC_GATE__SDB_MASK; UVD_SUVD_CGC_GATE__SDB_MASK;
if (enable) { if (enable) {
data3 |= (UVD_CGC_GATE__SYS_MASK | data3 |= (UVD_CGC_GATE__SYS_MASK |
UVD_CGC_GATE__UDEC_MASK | UVD_CGC_GATE__UDEC_MASK |
UVD_CGC_GATE__MPEG2_MASK | UVD_CGC_GATE__MPEG2_MASK |
UVD_CGC_GATE__RBC_MASK | UVD_CGC_GATE__RBC_MASK |
...@@ -656,9 +656,11 @@ static void uvd_v5_0_enable_clock_gating(struct amdgpu_device *adev, bool enable ...@@ -656,9 +656,11 @@ static void uvd_v5_0_enable_clock_gating(struct amdgpu_device *adev, bool enable
UVD_CGC_GATE__UDEC_DB_MASK | UVD_CGC_GATE__UDEC_DB_MASK |
UVD_CGC_GATE__UDEC_MP_MASK | UVD_CGC_GATE__UDEC_MP_MASK |
UVD_CGC_GATE__WCB_MASK | UVD_CGC_GATE__WCB_MASK |
UVD_CGC_GATE__VCPU_MASK |
UVD_CGC_GATE__JPEG_MASK | UVD_CGC_GATE__JPEG_MASK |
UVD_CGC_GATE__SCPU_MASK); UVD_CGC_GATE__SCPU_MASK);
/* only in pg enabled, we can gate clock to vcpu*/
if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
data3 |= UVD_CGC_GATE__VCPU_MASK;
data3 &= ~UVD_CGC_GATE__REGS_MASK; data3 &= ~UVD_CGC_GATE__REGS_MASK;
data1 |= suvd_flags; data1 |= suvd_flags;
} else { } else {
......
...@@ -879,10 +879,13 @@ static void uvd_v6_0_enable_clock_gating(struct amdgpu_device *adev, bool enable ...@@ -879,10 +879,13 @@ static void uvd_v6_0_enable_clock_gating(struct amdgpu_device *adev, bool enable
UVD_CGC_GATE__UDEC_DB_MASK | UVD_CGC_GATE__UDEC_DB_MASK |
UVD_CGC_GATE__UDEC_MP_MASK | UVD_CGC_GATE__UDEC_MP_MASK |
UVD_CGC_GATE__WCB_MASK | UVD_CGC_GATE__WCB_MASK |
UVD_CGC_GATE__VCPU_MASK |
UVD_CGC_GATE__JPEG_MASK | UVD_CGC_GATE__JPEG_MASK |
UVD_CGC_GATE__SCPU_MASK | UVD_CGC_GATE__SCPU_MASK |
UVD_CGC_GATE__JPEG2_MASK); UVD_CGC_GATE__JPEG2_MASK);
/* only in pg enabled, we can gate clock to vcpu*/
if (adev->pg_flags & AMD_PG_SUPPORT_UVD)
data3 |= UVD_CGC_GATE__VCPU_MASK;
data3 &= ~UVD_CGC_GATE__REGS_MASK; data3 &= ~UVD_CGC_GATE__REGS_MASK;
} else { } else {
data3 = 0; data3 = 0;
......
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