Commit 3c677d20 authored by Joerg Roedel's avatar Joerg Roedel

iommu/amd: Set exclusion range correctly

The exlcusion range limit register needs to contain the
base-address of the last page that is part of the range, as
bits 0-11 of this register are treated as 0xfff by the
hardware for comparisons.

So correctly set the exclusion range in the hardware to the
last page which is _in_ the range.

Fixes: b2026aa2 ('x86, AMD IOMMU: add functions for programming IOMMU MMIO space')
Signed-off-by: default avatarJoerg Roedel <jroedel@suse.de>
parent 15ade5d2
...@@ -359,7 +359,7 @@ static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val) ...@@ -359,7 +359,7 @@ static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val)
static void iommu_set_exclusion_range(struct amd_iommu *iommu) static void iommu_set_exclusion_range(struct amd_iommu *iommu)
{ {
u64 start = iommu->exclusion_start & PAGE_MASK; u64 start = iommu->exclusion_start & PAGE_MASK;
u64 limit = (start + iommu->exclusion_length) & PAGE_MASK; u64 limit = (start + iommu->exclusion_length - 1) & PAGE_MASK;
u64 entry; u64 entry;
if (!iommu->exclusion_start) if (!iommu->exclusion_start)
......
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