Commit 3d64a5a7 authored by Rashmica Gupta's avatar Rashmica Gupta Committed by Linus Walleij

gpio: aspeed: Setup irqchip dynamically

This is in preparation for adding ast2600 support. The ast2600 SoC
requires two instances of the GPIO driver as it has two GPIO
controllers. Each instance needs it's own irqchip.
Signed-off-by: default avatarRashmica Gupta <rashmica.g@gmail.com>
Link: https://lore.kernel.org/r/20190906062644.13445-1-rashmica.g@gmail.comReviewed-by: default avatarJoel Stanley <joel@jms.id.au>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent 3c4710ae
...@@ -52,6 +52,7 @@ struct aspeed_gpio_config { ...@@ -52,6 +52,7 @@ struct aspeed_gpio_config {
*/ */
struct aspeed_gpio { struct aspeed_gpio {
struct gpio_chip chip; struct gpio_chip chip;
struct irq_chip irqc;
spinlock_t lock; spinlock_t lock;
void __iomem *base; void __iomem *base;
int irq; int irq;
...@@ -681,14 +682,6 @@ static void aspeed_gpio_irq_handler(struct irq_desc *desc) ...@@ -681,14 +682,6 @@ static void aspeed_gpio_irq_handler(struct irq_desc *desc)
chained_irq_exit(ic, desc); chained_irq_exit(ic, desc);
} }
static struct irq_chip aspeed_gpio_irqchip = {
.name = "aspeed-gpio",
.irq_ack = aspeed_gpio_irq_ack,
.irq_mask = aspeed_gpio_irq_mask,
.irq_unmask = aspeed_gpio_irq_unmask,
.irq_set_type = aspeed_gpio_set_type,
};
static void aspeed_init_irq_valid_mask(struct gpio_chip *gc, static void aspeed_init_irq_valid_mask(struct gpio_chip *gc,
unsigned long *valid_mask, unsigned long *valid_mask,
unsigned int ngpios) unsigned int ngpios)
...@@ -1195,7 +1188,12 @@ static int __init aspeed_gpio_probe(struct platform_device *pdev) ...@@ -1195,7 +1188,12 @@ static int __init aspeed_gpio_probe(struct platform_device *pdev)
gpio->irq = rc; gpio->irq = rc;
girq = &gpio->chip.irq; girq = &gpio->chip.irq;
girq->chip = &aspeed_gpio_irqchip; girq->chip = &gpio->irqc;
girq->chip->name = dev_name(&pdev->dev);
girq->chip->irq_ack = aspeed_gpio_irq_ack;
girq->chip->irq_mask = aspeed_gpio_irq_mask;
girq->chip->irq_unmask = aspeed_gpio_irq_unmask;
girq->chip->irq_set_type = aspeed_gpio_set_type;
girq->parent_handler = aspeed_gpio_irq_handler; girq->parent_handler = aspeed_gpio_irq_handler;
girq->num_parents = 1; girq->num_parents = 1;
girq->parents = devm_kcalloc(&pdev->dev, 1, girq->parents = devm_kcalloc(&pdev->dev, 1,
......
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