Commit 3d9170c3 authored by Peter Geis's avatar Peter Geis Committed by Heiko Stuebner

arm64: dts: rockchip: add rk356x gpio debounce clocks

The rk356x added a debounce clock to the gpio devices. This clock is
necessary for the new v2 gpio driver to bind.
Add the clocks to the rk356x device tree.
Signed-off-by: default avatarPeter Geis <pgwipeout@gmail.com>
Link: https://lore.kernel.org/r/20210728180034.717953-4-pgwipeout@gmail.comSigned-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent 8a599b56
...@@ -804,7 +804,7 @@ gpio0: gpio@fdd60000 { ...@@ -804,7 +804,7 @@ gpio0: gpio@fdd60000 {
compatible = "rockchip,gpio-bank"; compatible = "rockchip,gpio-bank";
reg = <0x0 0xfdd60000 0x0 0x100>; reg = <0x0 0xfdd60000 0x0 0x100>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&pmucru PCLK_GPIO0>; clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>;
gpio-controller; gpio-controller;
#gpio-cells = <2>; #gpio-cells = <2>;
interrupt-controller; interrupt-controller;
...@@ -815,7 +815,7 @@ gpio1: gpio@fe740000 { ...@@ -815,7 +815,7 @@ gpio1: gpio@fe740000 {
compatible = "rockchip,gpio-bank"; compatible = "rockchip,gpio-bank";
reg = <0x0 0xfe740000 0x0 0x100>; reg = <0x0 0xfe740000 0x0 0x100>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO1>; clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
gpio-controller; gpio-controller;
#gpio-cells = <2>; #gpio-cells = <2>;
interrupt-controller; interrupt-controller;
...@@ -826,7 +826,7 @@ gpio2: gpio@fe750000 { ...@@ -826,7 +826,7 @@ gpio2: gpio@fe750000 {
compatible = "rockchip,gpio-bank"; compatible = "rockchip,gpio-bank";
reg = <0x0 0xfe750000 0x0 0x100>; reg = <0x0 0xfe750000 0x0 0x100>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO2>; clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
gpio-controller; gpio-controller;
#gpio-cells = <2>; #gpio-cells = <2>;
interrupt-controller; interrupt-controller;
...@@ -837,7 +837,7 @@ gpio3: gpio@fe760000 { ...@@ -837,7 +837,7 @@ gpio3: gpio@fe760000 {
compatible = "rockchip,gpio-bank"; compatible = "rockchip,gpio-bank";
reg = <0x0 0xfe760000 0x0 0x100>; reg = <0x0 0xfe760000 0x0 0x100>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO3>; clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
gpio-controller; gpio-controller;
#gpio-cells = <2>; #gpio-cells = <2>;
interrupt-controller; interrupt-controller;
...@@ -848,7 +848,7 @@ gpio4: gpio@fe770000 { ...@@ -848,7 +848,7 @@ gpio4: gpio@fe770000 {
compatible = "rockchip,gpio-bank"; compatible = "rockchip,gpio-bank";
reg = <0x0 0xfe770000 0x0 0x100>; reg = <0x0 0xfe770000 0x0 0x100>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru PCLK_GPIO4>; clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
gpio-controller; gpio-controller;
#gpio-cells = <2>; #gpio-cells = <2>;
interrupt-controller; interrupt-controller;
......
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