Commit 3e037454 authored by Shannon Nelson's avatar Shannon Nelson Committed by Linus Torvalds

I/OAT: Add support for MSI and MSI-X

Add support for MSI and MSI-X interrupt handling, including the ability
to choose the desired interrupt method.
Signed-off-by: default avatarShannon Nelson <shannon.nelson@intel.com>
Acked-by: default avatarDavid S. Miller <davem@davemloft.net>
[bunk@kernel.org: drivers/dma/ioat_dma.c: make 3 functions static]
Signed-off-by: default avatarAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: default avatarLinus Torvalds <torvalds@linux-foundation.org>
parent 8ab89567
This diff is collapsed.
...@@ -28,6 +28,14 @@ ...@@ -28,6 +28,14 @@
#include <linux/cache.h> #include <linux/cache.h>
#include <linux/pci_ids.h> #include <linux/pci_ids.h>
enum ioat_interrupt {
none = 0,
msix_multi_vector = 1,
msix_single_vector = 2,
msi = 3,
intx = 4,
};
#define IOAT_LOW_COMPLETION_MASK 0xffffffc0 #define IOAT_LOW_COMPLETION_MASK 0xffffffc0
/** /**
...@@ -46,6 +54,9 @@ struct ioatdma_device { ...@@ -46,6 +54,9 @@ struct ioatdma_device {
struct pci_pool *completion_pool; struct pci_pool *completion_pool;
struct dma_device common; struct dma_device common;
u8 version; u8 version;
enum ioat_interrupt irq_mode;
struct msix_entry msix_entries[4];
struct ioat_dma_chan *idx[4];
}; };
/** /**
...@@ -94,6 +105,7 @@ struct ioat_dma_chan { ...@@ -94,6 +105,7 @@ struct ioat_dma_chan {
u32 high; u32 high;
}; };
} *completion_virt; } *completion_virt;
struct tasklet_struct cleanup_task;
}; };
/* wrapper around hardware descriptor format + additional software fields */ /* wrapper around hardware descriptor format + additional software fields */
......
/* /*
* Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved. * Copyright(c) 2004 - 2007 Intel Corporation. All rights reserved.
* *
* This program is free software; you can redistribute it and/or modify it * This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the Free * under the terms of the GNU General Public License as published by the Free
...@@ -21,6 +21,9 @@ ...@@ -21,6 +21,9 @@
#ifndef _IOAT_REGISTERS_H_ #ifndef _IOAT_REGISTERS_H_
#define _IOAT_REGISTERS_H_ #define _IOAT_REGISTERS_H_
#define IOAT_PCI_DMACTRL_OFFSET 0x48
#define IOAT_PCI_DMACTRL_DMA_EN 0x00000001
#define IOAT_PCI_DMACTRL_MSI_EN 0x00000002
/* MMIO Device Registers */ /* MMIO Device Registers */
#define IOAT_CHANCNT_OFFSET 0x00 /* 8-bit */ #define IOAT_CHANCNT_OFFSET 0x00 /* 8-bit */
...@@ -39,6 +42,7 @@ ...@@ -39,6 +42,7 @@
#define IOAT_INTRCTRL_MASTER_INT_EN 0x01 /* Master Interrupt Enable */ #define IOAT_INTRCTRL_MASTER_INT_EN 0x01 /* Master Interrupt Enable */
#define IOAT_INTRCTRL_INT_STATUS 0x02 /* ATTNSTATUS -or- Channel Int */ #define IOAT_INTRCTRL_INT_STATUS 0x02 /* ATTNSTATUS -or- Channel Int */
#define IOAT_INTRCTRL_INT 0x04 /* INT_STATUS -and- MASTER_INT_EN */ #define IOAT_INTRCTRL_INT 0x04 /* INT_STATUS -and- MASTER_INT_EN */
#define IOAT_INTRCTRL_MSIX_VECTOR_CONTROL 0x08 /* Enable all MSI-X vectors */
#define IOAT_ATTNSTATUS_OFFSET 0x04 /* Each bit is a channel */ #define IOAT_ATTNSTATUS_OFFSET 0x04 /* Each bit is a channel */
......
...@@ -8,6 +8,12 @@ ...@@ -8,6 +8,12 @@
*/ */
#include <asm/bitops.h> #include <asm/bitops.h>
#define for_each_bit(bit, addr, size) \
for ((bit) = find_first_bit((addr), (size)); \
(bit) < (size); \
(bit) = find_next_bit((addr), (size), (bit) + 1))
static __inline__ int get_bitmask_order(unsigned int count) static __inline__ int get_bitmask_order(unsigned int count)
{ {
int order; int order;
......
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