Commit 3e2eae8d authored by Alex Deucher's avatar Alex Deucher

drm/amdgpu: add I2C_CLASS_HWMON to SMU i2c buses

Not sure that this really matters that much, but these could
have various other hwmon chips on them.
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: default avatarLuben Tuikov <luben.tuikov@amd.com>
parent 39ed82d1
......@@ -665,7 +665,7 @@ int smu_v11_0_i2c_control_init(struct i2c_adapter *control)
mutex_init(&adev->pm.smu_i2c_mutex);
control->owner = THIS_MODULE;
control->class = I2C_CLASS_SPD;
control->class = I2C_CLASS_SPD | I2C_CLASS_HWMON;
control->dev.parent = &adev->pdev->dev;
control->algo = &smu_v11_0_i2c_algo;
snprintf(control->name, sizeof(control->name), "AMDGPU SMU");
......
......@@ -2033,7 +2033,7 @@ static int arcturus_i2c_control_init(struct smu_context *smu, struct i2c_adapter
int res;
control->owner = THIS_MODULE;
control->class = I2C_CLASS_SPD;
control->class = I2C_CLASS_SPD | I2C_CLASS_HWMON;
control->dev.parent = &adev->pdev->dev;
control->algo = &arcturus_i2c_algo;
snprintf(control->name, sizeof(control->name), "AMDGPU SMU");
......
......@@ -2832,7 +2832,7 @@ static int navi10_i2c_control_init(struct smu_context *smu, struct i2c_adapter *
int res;
control->owner = THIS_MODULE;
control->class = I2C_CLASS_SPD;
control->class = I2C_CLASS_SPD | I2C_CLASS_HWMON;
control->dev.parent = &adev->pdev->dev;
control->algo = &navi10_i2c_algo;
snprintf(control->name, sizeof(control->name), "AMDGPU SMU");
......
......@@ -3539,7 +3539,7 @@ static int sienna_cichlid_i2c_control_init(struct smu_context *smu, struct i2c_a
int res;
control->owner = THIS_MODULE;
control->class = I2C_CLASS_SPD;
control->class = I2C_CLASS_SPD | I2C_CLASS_HWMON;
control->dev.parent = &adev->pdev->dev;
control->algo = &sienna_cichlid_i2c_algo;
snprintf(control->name, sizeof(control->name), "AMDGPU SMU");
......
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