Merge nuts.ninka.net:/home/davem/src/BK/sparcwork-2.5

into nuts.ninka.net:/home/davem/src/BK/sparc-2.5

arch/sparc64/kernel/irq.c

@@ -719,12 +719,8 @@ void handler_irq(int irq, struct pt_regs *regs)
 	 */
 	{
 		unsigned long clr_mask = 1 << irq;
-		unsigned long tick_mask;
+		unsigned long tick_mask = tick_ops->softint_mask;
 
-		if (SPARC64_USE_STICK)
-			tick_mask = (1UL << 16);
-		else
-			tick_mask = (1UL << 0);
 		if ((irq == 14) && (get_softint() & tick_mask)) {
 			irq = 0;
 			clr_mask = tick_mask;
@@ -946,113 +942,6 @@ int probe_irq_off(unsigned long mask)
 	return 0;
 }
 
-/* This is gets the master TICK_INT timer going. */
-void sparc64_init_timers(void (*cfunc)(int, void *, struct pt_regs *),
-			 unsigned long *clock)
-{
-	unsigned long pstate;
-	extern unsigned long timer_tick_offset;
-	int node, err;
-#ifdef CONFIG_SMP
-	extern void smp_tick_init(void);
-#endif
-
-	if (!SPARC64_USE_STICK) {
-		node = linux_cpus[0].prom_node;
-		*clock = prom_getint(node, "clock-frequency");
-	} else {
-		node = prom_root_node;
-		*clock = prom_getint(node, "stick-frequency");
-	}
-	timer_tick_offset = *clock / HZ;
-#ifdef CONFIG_SMP
-	smp_tick_init();
-#endif
-
-	/* Register IRQ handler. */
-	err = request_irq(build_irq(0, 0, 0UL, 0UL), cfunc, SA_STATIC_ALLOC,
-			  "timer", NULL);
-
-	if (err) {
-		prom_printf("Serious problem, cannot register TICK_INT\n");
-		prom_halt();
-	}
-
-	/* Guarentee that the following sequences execute
-	 * uninterrupted.
-	 */
-	__asm__ __volatile__("rdpr	%%pstate, %0\n\t"
-			     "wrpr	%0, %1, %%pstate"
-			     : "=r" (pstate)
-			     : "i" (PSTATE_IE));
-
-	/* Set things up so user can access tick register for profiling
-	 * purposes.  Also workaround BB_ERRATA_1 by doing a dummy
-	 * read back of %tick after writing it.
-	 */
-	__asm__ __volatile__(
-	"	sethi	%%hi(0x80000000), %%g1\n"
-	"	ba,pt	%%xcc, 1f\n"
-	"	 sllx	%%g1, 32, %%g1\n"
-	"	.align	64\n"
-	"1:	rd	%%tick, %%g2\n"
-	"	add	%%g2, 6, %%g2\n"
-	"	andn	%%g2, %%g1, %%g2\n"
-	"	wrpr	%%g2, 0, %%tick\n"
-	"	rdpr	%%tick, %%g0"
-	: /* no outputs */
-	: /* no inputs */
-	: "g1", "g2");
-
-	/* Workaround for Spitfire Errata (#54 I think??), I discovered
-	 * this via Sun BugID 4008234, mentioned in Solaris-2.5.1 patch
-	 * number 103640.
-	 *
-	 * On Blackbird writes to %tick_cmpr can fail, the
-	 * workaround seems to be to execute the wr instruction
-	 * at the start of an I-cache line, and perform a dummy
-	 * read back from %tick_cmpr right after writing to it. -DaveM
-	 */
-	if (!SPARC64_USE_STICK) {
-	__asm__ __volatile__(
-	"	rd	%%tick, %%g1\n"
-	"	ba,pt	%%xcc, 1f\n"
-	"	 add	%%g1, %0, %%g1\n"
-	"	.align	64\n"
-	"1:	wr	%%g1, 0x0, %%tick_cmpr\n"
-	"	rd	%%tick_cmpr, %%g0"
-	: /* no outputs */
-	: "r" (timer_tick_offset)
-	: "g1");
-	} else {
-	/* Let the user get at STICK too. */
-	__asm__ __volatile__(
-	"	sethi	%%hi(0x80000000), %%g1\n"
-	"	sllx	%%g1, 32, %%g1\n"
-	"	rd	%%asr24, %%g2\n"
-	"	andn	%%g2, %%g1, %%g2\n"
-	"	wr	%%g2, 0, %%asr24"
-	: /* no outputs */
-	: /* no inputs */
-	: "g1", "g2");
-
-	__asm__ __volatile__(
-	"	rd	%%asr24, %%g1\n"
-	"	add	%%g1, %0, %%g1\n"
-	"	wr	%%g1, 0x0, %%asr25"
-	: /* no outputs */
-	: "r" (timer_tick_offset)
-	: "g1");
-	}
-
-	/* Restore PSTATE_IE. */
-	__asm__ __volatile__("wrpr	%0, 0x0, %%pstate"
-			     : /* no outputs */
-			     : "r" (pstate));
-
-	local_irq_enable();
-}
-
 #ifdef CONFIG_SMP
 static int retarget_one_irq(struct irqaction *p, int goal_cpu)
 {

arch/sparc64/kernel/sparc64_ksyms.c

@@ -128,20 +128,13 @@ EXPORT_SYMBOL(__write_unlock);
 #endif
 
 /* Hard IRQ locking */
-#ifdef CONFIG_SMP
 EXPORT_SYMBOL(synchronize_irq);
-#endif
 
 #if defined(CONFIG_MCOUNT)
 extern void mcount(void);
 EXPORT_SYMBOL_NOVERS(mcount);
 #endif
 
-/* Uniprocessor clock frequency */
-#ifndef CONFIG_SMP
-EXPORT_SYMBOL(up_clock_tick);
-#endif
-
 /* Per-CPU information table */
 EXPORT_SYMBOL(cpu_data);
 
@@ -162,10 +155,13 @@ EXPORT_SYMBOL(_do_write_lock);
 EXPORT_SYMBOL(_do_write_unlock);
 #endif
 
-#ifdef CONFIG_SMP
 EXPORT_SYMBOL(smp_call_function);
-#endif
+#endif /* CONFIG_SMP */
 
+/* Uniprocessor clock frequency */
+#ifndef CONFIG_SMP
+extern unsigned long up_clock_tick;
+EXPORT_SYMBOL(up_clock_tick);
 #endif
 
 /* semaphores */

arch/sparc64/kernel/traps.c

@@ -33,6 +33,7 @@
 #include <asm/chafsr.h>
 #include <asm/psrcompat.h>
 #include <asm/processor.h>
+#include <asm/timer.h>
 #ifdef CONFIG_KMOD
 #include <linux/kmod.h>
 #endif
@@ -588,7 +589,7 @@ unsigned long __init cheetah_tune_scheduling(void)
 	flush_linesize = ecache_flush_linesize;
 	flush_size = ecache_flush_size >> 1;
 
-	__asm__ __volatile__("rd %%tick, %0" : "=r" (tick1));
+	tick1 = tick_ops->get_tick();
 
 	__asm__ __volatile__("1: subcc	%0, %4, %0\n\t"
 			     "   bne,pt	%%xcc, 1b\n\t"
@@ -597,7 +598,7 @@ unsigned long __init cheetah_tune_scheduling(void)
 			     : "0" (flush_size), "r" (flush_base),
 			       "i" (ASI_PHYS_USE_EC), "r" (flush_linesize));
 
-	__asm__ __volatile__("rd %%tick, %0" : "=r" (tick2));
+	tick2 = tick_ops->get_tick();
 
 	raw = (tick2 - tick1);
 

arch/sparc64/mm/ultra.S

@@ -560,8 +560,8 @@ xcall_flush_tlb_kernel_range:
 	/* This runs in a very controlled environment, so we do
 	 * not need to worry about BH races etc.
 	 */
-	.globl		xcall_sync_stick
-xcall_sync_stick:
+	.globl		xcall_sync_tick
+xcall_sync_tick:
 	rdpr		%pstate, %g2
 	wrpr		%g2, PSTATE_IG | PSTATE_AG, %pstate
 	rdpr		%pil, %g2
@@ -569,7 +569,7 @@ xcall_sync_stick:
 	sethi		%hi(109f), %g7
 	b,pt		%xcc, etrap_irq
 109:	 or		%g7, %lo(109b), %g7
-	call		smp_synchronize_stick_client
+	call		smp_synchronize_tick_client
 	 nop
 	clr		%l6
 	b		rtrap_xcall

include/asm-sparc64/irq.h

@@ -117,8 +117,6 @@ static __inline__ char *__irq_itoa(unsigned int irq)
 extern void disable_irq(unsigned int);
 #define disable_irq_nosync disable_irq
 extern void enable_irq(unsigned int);
-extern void sparc64_init_timers(void (*lvl10_irq)(int, void *, struct pt_regs *),
-				unsigned long *);
 extern unsigned int build_irq(int pil, int inofixup, unsigned long iclr, unsigned long imap);
 extern unsigned int sbus_build_irq(void *sbus, unsigned int ino);
 extern unsigned int psycho_build_irq(void *psycho, int imap_off, int ino, int need_dma_sync);

include/asm-sparc64/spitfire.h

@@ -45,8 +45,6 @@ enum ultra_tlb_layout {
 
 extern enum ultra_tlb_layout tlb_type;
 
-#define SPARC64_USE_STICK	(tlb_type != spitfire)
-
 #define CHEETAH_HIGHEST_LOCKED_TLBENT	(16 - 1)
 
 #define L1DCACHE_SIZE		0x4000

include/asm-sparc64/timer.h

@@ -50,6 +50,17 @@ struct sun5_timer {
  */
 #define SUN5_HZ_TO_LIMIT(__hz)  (1000000/(__hz))
 
+struct sparc64_tick_ops {
+	void (*init_tick)(unsigned long);
+	unsigned long (*get_tick)(void);
+	unsigned long (*get_compare)(void);
+	unsigned long (*add_tick)(unsigned long, unsigned long);
+	unsigned long (*add_compare)(unsigned long);
+	unsigned long softint_mask;
+};
+
+extern struct sparc64_tick_ops *tick_ops;
+
 #ifdef CONFIG_SMP
 extern unsigned long timer_tick_offset;
 extern void timer_tick_interrupt(struct pt_regs *);