Commit 3e88cbb0 authored by Alex Deucher's avatar Alex Deucher

drm/amdgpu/dc: fix DCN3.1 FP handling

Missing proper DC_FP_START/DC_FP_END.
Reviewed-by: default avatarNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent df7a1658
......@@ -1633,7 +1633,7 @@ static void dcn31_update_soc_for_wm_a(struct dc *dc, struct dc_state *context)
}
}
static void dcn31_calculate_wm_and_dlg(
static void dcn31_calculate_wm_and_dlg_fp(
struct dc *dc, struct dc_state *context,
display_e2e_pipe_params_st *pipes,
int pipe_cnt,
......@@ -1759,6 +1759,17 @@ static void dcn31_calculate_wm_and_dlg(
dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);
}
static void dcn31_calculate_wm_and_dlg(
struct dc *dc, struct dc_state *context,
display_e2e_pipe_params_st *pipes,
int pipe_cnt,
int vlevel)
{
DC_FP_START();
dcn31_calculate_wm_and_dlg_fp(dc, context, pipes, pipe_cnt, vlevel);
DC_FP_END();
}
static struct dc_cap_funcs cap_funcs = {
.get_dcc_compression_cap = dcn20_get_dcc_compression_cap
};
......@@ -1890,6 +1901,8 @@ static bool dcn31_resource_construct(
struct dc_context *ctx = dc->ctx;
struct irq_service_init_data init_data;
DC_FP_START();
ctx->dc_bios->regs = &bios_regs;
pool->base.res_cap = &res_cap_dcn31;
......@@ -2152,10 +2165,13 @@ static bool dcn31_resource_construct(
dc->cap_funcs = cap_funcs;
DC_FP_END();
return true;
create_fail:
DC_FP_END();
dcn31_resource_destruct(pool);
return false;
......
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