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Commit 4006e565 authored by Daniel Glöckner's avatar Daniel Glöckner Committed by Max Filippov
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xtensa: remove s6000 variant and s6105 platform 

The Stretch s6000 family support has been merged into mainline 5 years
ago. There appear to be no users of this code since nobody complained
that there is a merge error preventing compilation.

Apart from the s6105 IP camera reference design there are no s6000 devices
known to ever have run Linux and as the chips are out of production there
probably never will be. The successor s7000 no longer uses an Xtensa core
for the OS.

Let's remove the code until someone is found who actually needs it.
Signed-off-by: default avatarDaniel Glöckner <dg@emlix.com>
Signed-off-by: default avatarMax Filippov <jcmvbkbc@gmail.com>
parent 3932b9ca
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arch/xtensa/Kconfig
View file @ 4006e565
...@@ -98,12 +98,6 @@ config XTENSA_VARIANT_DC233C ...@@ -98,12 +98,6 @@ config XTENSA_VARIANT_DC233C
help help
This variant refers to Tensilica's Diamond 233L Standard core Rev.C (LE). This variant refers to Tensilica's Diamond 233L Standard core Rev.C (LE).
config XTENSA_VARIANT_S6000
bool "s6000 - Stretch software configurable processor"
select VARIANT_IRQ_SWITCH
select ARCH_REQUIRE_GPIOLIB
select XTENSA_CALIBRATE_CCOUNT
config XTENSA_VARIANT_CUSTOM config XTENSA_VARIANT_CUSTOM
bool "Custom Xtensa processor configuration" bool "Custom Xtensa processor configuration"
select MAY_HAVE_SMP select MAY_HAVE_SMP
...@@ -126,7 +120,6 @@ config XTENSA_VARIANT_NAME ...@@ -126,7 +120,6 @@ config XTENSA_VARIANT_NAME
default "dc232b" if XTENSA_VARIANT_DC232B default "dc232b" if XTENSA_VARIANT_DC232B
default "dc233c" if XTENSA_VARIANT_DC233C default "dc233c" if XTENSA_VARIANT_DC233C
default "fsf" if XTENSA_VARIANT_FSF default "fsf" if XTENSA_VARIANT_FSF
default "s6000" if XTENSA_VARIANT_S6000
default XTENSA_VARIANT_CUSTOM_NAME if XTENSA_VARIANT_CUSTOM default XTENSA_VARIANT_CUSTOM_NAME if XTENSA_VARIANT_CUSTOM
config XTENSA_VARIANT_MMU config XTENSA_VARIANT_MMU
...@@ -310,12 +303,6 @@ config XTENSA_PLATFORM_XT2000 ...@@ -310,12 +303,6 @@ config XTENSA_PLATFORM_XT2000
XT2000 is the name of Tensilica's feature-rich emulation platform. XT2000 is the name of Tensilica's feature-rich emulation platform.
This hardware is capable of running a full Linux distribution. This hardware is capable of running a full Linux distribution.
config XTENSA_PLATFORM_S6105
bool "S6105"
select HAVE_IDE
select SERIAL_CONSOLE
select NO_IOPORT_MAP
config XTENSA_PLATFORM_XTFPGA config XTENSA_PLATFORM_XTFPGA
bool "XTFPGA" bool "XTFPGA"
select ETHOC if ETHERNET select ETHOC if ETHERNET
......
arch/xtensa/Makefile
View file @ 4006e565
...@@ -35,7 +35,6 @@ endif ...@@ -35,7 +35,6 @@ endif
platform-$(CONFIG_XTENSA_PLATFORM_XT2000) := xt2000 platform-$(CONFIG_XTENSA_PLATFORM_XT2000) := xt2000
platform-$(CONFIG_XTENSA_PLATFORM_ISS) := iss platform-$(CONFIG_XTENSA_PLATFORM_ISS) := iss
platform-$(CONFIG_XTENSA_PLATFORM_S6105) := s6105
platform-$(CONFIG_XTENSA_PLATFORM_XTFPGA) := xtfpga platform-$(CONFIG_XTENSA_PLATFORM_XTFPGA) := xtfpga
PLATFORM = $(platform-y) PLATFORM = $(platform-y)
......
arch/xtensa/configs/iss_defconfig
View file @ 4006e565
...@@ -143,7 +143,6 @@ CONFIG_MMU=y ...@@ -143,7 +143,6 @@ CONFIG_MMU=y
# #
CONFIG_XTENSA_VARIANT_FSF=y CONFIG_XTENSA_VARIANT_FSF=y
# CONFIG_XTENSA_VARIANT_DC232B is not set # CONFIG_XTENSA_VARIANT_DC232B is not set
# CONFIG_XTENSA_VARIANT_S6000 is not set
# CONFIG_XTENSA_UNALIGNED_USER is not set # CONFIG_XTENSA_UNALIGNED_USER is not set
# CONFIG_PREEMPT is not set # CONFIG_PREEMPT is not set
CONFIG_XTENSA_CALIBRATE_CCOUNT=y CONFIG_XTENSA_CALIBRATE_CCOUNT=y
...@@ -161,7 +160,6 @@ CONFIG_XTENSA_ISS_NETWORK=y ...@@ -161,7 +160,6 @@ CONFIG_XTENSA_ISS_NETWORK=y
# #
CONFIG_XTENSA_PLATFORM_ISS=y CONFIG_XTENSA_PLATFORM_ISS=y
# CONFIG_XTENSA_PLATFORM_XT2000 is not set # CONFIG_XTENSA_PLATFORM_XT2000 is not set
# CONFIG_XTENSA_PLATFORM_S6105 is not set
# CONFIG_GENERIC_CALIBRATE_DELAY is not set # CONFIG_GENERIC_CALIBRATE_DELAY is not set
CONFIG_CMDLINE_BOOL=y CONFIG_CMDLINE_BOOL=y
CONFIG_CMDLINE="console=ttyS0,38400 eth0=tuntap,,tap0 ip=192.168.168.5:192.168.168.1 root=nfs nfsroot=192.168.168.1:/opt/montavista/pro/devkit/xtensa/linux_be/target" CONFIG_CMDLINE="console=ttyS0,38400 eth0=tuntap,,tap0 ip=192.168.168.5:192.168.168.1 root=nfs nfsroot=192.168.168.1:/opt/montavista/pro/devkit/xtensa/linux_be/target"
......
arch/xtensa/configs/s6105_defconfig deleted 100644 → 0
View file @ 3932b9ca
This diff is collapsed.
arch/xtensa/platforms/s6105/Makefile deleted 100644 → 0
View file @ 3932b9ca
# Makefile for the Stretch S6105 eval board
obj-y := setup.o device.o
arch/xtensa/platforms/s6105/device.c deleted 100644 → 0
View file @ 3932b9ca
/*
* s6105 platform devices
*
* Copyright (c) 2009 emlix GmbH
*/
#include <linux/kernel.h>
#include <linux/gpio.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/phy.h>
#include <linux/platform_device.h>
#include <linux/serial.h>
#include <linux/serial_8250.h>
#include <variant/hardware.h>
#include <variant/dmac.h>
#include <platform/gpio.h>
#define GPIO3_INTNUM 3
#define UART_INTNUM 4
#define GMAC_INTNUM 5
static const signed char gpio3_irq_mappings[] = {
S6_INTC_GPIO(3),
-1
};
static const signed char uart_irq_mappings[] = {
S6_INTC_UART(0),
S6_INTC_UART(1),
-1,
};
static const signed char gmac_irq_mappings[] = {
S6_INTC_GMAC_STAT,
S6_INTC_GMAC_ERR,
S6_INTC_DMA_HOSTTERMCNT(0),
S6_INTC_DMA_HOSTTERMCNT(1),
-1
};
const signed char *platform_irq_mappings[NR_IRQS] = {
[GPIO3_INTNUM] = gpio3_irq_mappings,
[UART_INTNUM] = uart_irq_mappings,
[GMAC_INTNUM] = gmac_irq_mappings,
};
static struct plat_serial8250_port serial_platform_data[] = {
{
.membase = (void *)S6_REG_UART + 0x0000,
.mapbase = S6_REG_UART + 0x0000,
.irq = UART_INTNUM,
.uartclk = S6_SCLK,
.regshift = 2,
.iotype = SERIAL_IO_MEM,
.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST,
},
{
.membase = (void *)S6_REG_UART + 0x1000,
.mapbase = S6_REG_UART + 0x1000,
.irq = UART_INTNUM,
.uartclk = S6_SCLK,
.regshift = 2,
.iotype = SERIAL_IO_MEM,
.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST,
},
{ },
};
static struct resource s6_gmac_resource[] = {
{
.name = "mem",
.start = (resource_size_t)S6_REG_GMAC,
.end = (resource_size_t)S6_REG_GMAC + 0x10000 - 1,
.flags = IORESOURCE_MEM,
},
{
.name = "dma",
.start = (resource_size_t)
DMA_CHNL(S6_REG_HIFDMA, S6_HIFDMA_GMACTX),
.end = (resource_size_t)
DMA_CHNL(S6_REG_HIFDMA, S6_HIFDMA_GMACTX) + 0x100 - 1,
.flags = IORESOURCE_DMA,
},
{
.name = "dma",
.start = (resource_size_t)
DMA_CHNL(S6_REG_HIFDMA, S6_HIFDMA_GMACRX),
.end = (resource_size_t)
DMA_CHNL(S6_REG_HIFDMA, S6_HIFDMA_GMACRX) + 0x100 - 1,
.flags = IORESOURCE_DMA,
},
{
.name = "io",
.start = (resource_size_t)S6_MEM_GMAC,
.end = (resource_size_t)S6_MEM_GMAC + 0x2000000 - 1,
.flags = IORESOURCE_IO,
},
{
.name = "irq",
.start = (resource_size_t)GMAC_INTNUM,
.flags = IORESOURCE_IRQ,
},
{
.name = "irq",
.start = (resource_size_t)PHY_POLL,
.flags = IORESOURCE_IRQ,
},
};
static int __init prepare_phy_irq(int pin)
{
int irq;
if (gpio_request(pin, "s6gmac_phy") < 0)
goto fail;
if (gpio_direction_input(pin) < 0)
goto free;
irq = gpio_to_irq(pin);
if (irq < 0)
goto free;
if (irq_set_irq_type(irq, IRQ_TYPE_LEVEL_LOW) < 0)
goto free;
return irq;
free:
gpio_free(pin);
fail:
return PHY_POLL;
}
static struct platform_device platform_devices[] = {
{
.name = "serial8250",
.id = PLAT8250_DEV_PLATFORM,
.dev = {
.platform_data = serial_platform_data,
},
},
{
.name = "s6gmac",
.id = 0,
.resource = s6_gmac_resource,
.num_resources = ARRAY_SIZE(s6_gmac_resource),
},
{
I2C_BOARD_INFO("m41t62", S6I2C_ADDR_M41T62),
},
};
static int __init device_init(void)
{
int i;
s6_gmac_resource[5].start = prepare_phy_irq(GPIO_PHY_IRQ);
for (i = 0; i < ARRAY_SIZE(platform_devices); i++)
platform_device_register(&platform_devices[i]);
return 0;
}
arch_initcall_sync(device_init);
arch/xtensa/platforms/s6105/include/platform/gpio.h deleted 100644 → 0
View file @ 3932b9ca
#ifndef __ASM_XTENSA_S6105_GPIO_H
#define __ASM_XTENSA_S6105_GPIO_H
#define GPIO_BP_TEMP_ALARM 0
#define GPIO_PB_RESET_IN 1
#define GPIO_EXP_IRQ 2
#define GPIO_TRIGGER_IRQ 3
#define GPIO_RTC_IRQ 4
#define GPIO_PHY_IRQ 5
#define GPIO_IMAGER_RESET 6
#define GPIO_SD_IRQ 7
#define GPIO_MINI_BOOT_INH 8
#define GPIO_BOARD_RESET 9
#define GPIO_EXP_PRESENT 10
#define GPIO_LED1_NGREEN 12
#define GPIO_LED1_RED 13
#define GPIO_LED0_NGREEN 14
#define GPIO_LED0_NRED 15
#define GPIO_SPI_CS0 16
#define GPIO_SPI_CS1 17
#define GPIO_SPI_CS3 19
#define GPIO_SPI_CS4 20
#define GPIO_SD_WP 21
#define GPIO_BP_RESET 22
#define GPIO_ALARM_OUT 23
#endif /* __ASM_XTENSA_S6105_GPIO_H */
arch/xtensa/platforms/s6105/include/platform/hardware.h deleted 100644 → 0
View file @ 3932b9ca
#ifndef __XTENSA_S6105_HARDWARE_H
#define __XTENSA_S6105_HARDWARE_H
#define PLATFORM_DEFAULT_MEM_START 0x40000000
#define PLATFORM_DEFAULT_MEM_SIZE 0x08000000
#define MAX_DMA_ADDRESS 0
#define KERNELOFFSET (PLATFORM_DEFAULT_MEM_START + 0x1000)
#endif /* __XTENSA_S6105_HARDWARE_H */
arch/xtensa/platforms/s6105/include/platform/serial.h deleted 100644 → 0
View file @ 3932b9ca
#ifndef __ASM_XTENSA_S6105_SERIAL_H
#define __ASM_XTENSA_S6105_SERIAL_H
#include <variant/hardware.h>
#define BASE_BAUD (S6_SCLK / 16)
#endif /* __ASM_XTENSA_S6105_SERIAL_H */
arch/xtensa/platforms/s6105/setup.c deleted 100644 → 0
View file @ 3932b9ca
/*
* s6105 control routines
*
* Copyright (c) 2009 emlix GmbH
*/
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <asm/bootparam.h>
#include <variant/hardware.h>
#include <variant/gpio.h>
#include <platform/gpio.h>
void platform_halt(void)
{
local_irq_disable();
while (1)
;
}
void platform_power_off(void)
{
platform_halt();
}
void platform_restart(void)
{
platform_halt();
}
void __init platform_setup(char **cmdline)
{
unsigned long reg;
reg = readl(S6_REG_GREG1 + S6_GREG1_PLLSEL);
reg &= ~(S6_GREG1_PLLSEL_GMAC_MASK << S6_GREG1_PLLSEL_GMAC |
S6_GREG1_PLLSEL_GMII_MASK << S6_GREG1_PLLSEL_GMII);
reg |= S6_GREG1_PLLSEL_GMAC_125MHZ << S6_GREG1_PLLSEL_GMAC |
S6_GREG1_PLLSEL_GMII_125MHZ << S6_GREG1_PLLSEL_GMII;
writel(reg, S6_REG_GREG1 + S6_GREG1_PLLSEL);
reg = readl(S6_REG_GREG1 + S6_GREG1_CLKGATE);
reg &= ~(1 << S6_GREG1_BLOCK_SB);
reg &= ~(1 << S6_GREG1_BLOCK_GMAC);
writel(reg, S6_REG_GREG1 + S6_GREG1_CLKGATE);
reg = readl(S6_REG_GREG1 + S6_GREG1_BLOCKENA);
reg |= 1 << S6_GREG1_BLOCK_SB;
reg |= 1 << S6_GREG1_BLOCK_GMAC;
writel(reg, S6_REG_GREG1 + S6_GREG1_BLOCKENA);
printk(KERN_NOTICE "S6105 on Stretch S6000 - "
"Copyright (C) 2009 emlix GmbH <info@emlix.com>\n");
}
void __init platform_init(bp_tag_t *first)
{
s6_gpio_init(0);
gpio_request(GPIO_LED1_NGREEN, "led1_green");
gpio_request(GPIO_LED1_RED, "led1_red");
gpio_direction_output(GPIO_LED1_NGREEN, 1);
}
void platform_heartbeat(void)
{
static unsigned int c;
if (!(++c & 0x4F))
gpio_direction_output(GPIO_LED1_RED, !(c & 0x10));
}
arch/xtensa/variants/s6000/Makefile deleted 100644 → 0
View file @ 3932b9ca
# s6000 Makefile
obj-y += irq.o gpio.o dmac.o
obj-$(CONFIG_XTENSA_CALIBRATE_CCOUNT) += delay.o
arch/xtensa/variants/s6000/delay.c deleted 100644 → 0
View file @ 3932b9ca
#include <asm/timex.h>
#include <asm/io.h>
#include <variant/hardware.h>
#define LOOPS 10
void platform_calibrate_ccount(void)
{
u32 uninitialized_var(a);
u32 uninitialized_var(u);
u32 b;
u32 tstamp = S6_REG_GREG1 + S6_GREG1_GLOBAL_TIMER;
int i = LOOPS+1;
do {
u32 t = u;
asm volatile(
"1: l32i %0, %2, 0 ;"
" beq %0, %1, 1b ;"
: "=&a"(u) : "a"(t), "a"(tstamp));
b = get_ccount();
if (i == LOOPS)
a = b;
} while (--i >= 0);
b -= a;
ccount_freq = b * (100000UL / LOOPS);
}
arch/xtensa/variants/s6000/dmac.c deleted 100644 → 0
View file @ 3932b9ca
/*
* Authors: Oskar Schirmer <oskar@scara.com>
* Daniel Gloeckner <dg@emlix.com>
* (c) 2008 emlix GmbH http://www.emlix.com
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#include <linux/kernel.h>
#include <linux/io.h>
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/spinlock.h>
#include <asm/cacheflush.h>
#include <variant/dmac.h>
/* DMA engine lookup */
struct s6dmac_ctrl s6dmac_ctrl[S6_DMAC_NB];
/* DMA control, per engine */
void s6dmac_put_fifo_cache(u32 dmac, int chan, u32 src, u32 dst, u32 size)
{
if (xtensa_need_flush_dma_source(src)) {
u32 base = src;
u32 span = size;
u32 chunk = readl(DMA_CHNL(dmac, chan) + S6_DMA_CMONCHUNK);
if (chunk && (size > chunk)) {
s32 skip =
readl(DMA_CHNL(dmac, chan) + S6_DMA_SRCSKIP);
u32 gaps = (size+chunk-1)/chunk - 1;
if (skip >= 0) {
span += gaps * skip;
} else if (-skip > chunk) {
s32 decr = gaps * (chunk + skip);
base += decr;
span = chunk - decr;
} else {
span = max(span + gaps * skip,
(chunk + skip) * gaps - skip);
}
}
flush_dcache_unaligned(base, span);
}
if (xtensa_need_invalidate_dma_destination(dst)) {
u32 base = dst;
u32 span = size;
u32 chunk = readl(DMA_CHNL(dmac, chan) + S6_DMA_CMONCHUNK);
if (chunk && (size > chunk)) {
s32 skip =
readl(DMA_CHNL(dmac, chan) + S6_DMA_DSTSKIP);
u32 gaps = (size+chunk-1)/chunk - 1;
if (skip >= 0) {
span += gaps * skip;
} else if (-skip > chunk) {
s32 decr = gaps * (chunk + skip);
base += decr;
span = chunk - decr;
} else {
span = max(span + gaps * skip,
(chunk + skip) * gaps - skip);
}
}
invalidate_dcache_unaligned(base, span);
}
s6dmac_put_fifo(dmac, chan, src, dst, size);
}
void s6dmac_disable_error_irqs(u32 dmac, u32 mask)
{
unsigned long flags;
spinlock_t *spinl = &s6dmac_ctrl[_dmac_addr_index(dmac)].lock;
spin_lock_irqsave(spinl, flags);
_s6dmac_disable_error_irqs(dmac, mask);
spin_unlock_irqrestore(spinl, flags);
}
u32 s6dmac_int_sources(u32 dmac, u32 channel)
{
u32 mask, ret, tmp;
mask = 1 << channel;
tmp = readl(dmac + S6_DMA_TERMCNTIRQSTAT);
tmp &= mask;
writel(tmp, dmac + S6_DMA_TERMCNTIRQCLR);
ret = tmp >> channel;
tmp = readl(dmac + S6_DMA_PENDCNTIRQSTAT);
tmp &= mask;
writel(tmp, dmac + S6_DMA_PENDCNTIRQCLR);
ret |= (tmp >> channel) << 1;
tmp = readl(dmac + S6_DMA_LOWWMRKIRQSTAT);
tmp &= mask;
writel(tmp, dmac + S6_DMA_LOWWMRKIRQCLR);
ret |= (tmp >> channel) << 2;
tmp = readl(dmac + S6_DMA_INTRAW0);
tmp &= (mask << S6_DMA_INT0_OVER) | (mask << S6_DMA_INT0_UNDER);
writel(tmp, dmac + S6_DMA_INTCLEAR0);
if (tmp & (mask << S6_DMA_INT0_UNDER))
ret |= 1 << 3;
if (tmp & (mask << S6_DMA_INT0_OVER))
ret |= 1 << 4;
tmp = readl(dmac + S6_DMA_MASTERERRINFO);
mask <<= S6_DMA_INT1_CHANNEL;
if (((tmp >> S6_DMA_MASTERERR_CHAN(0)) & S6_DMA_MASTERERR_CHAN_MASK)
== channel)
mask |= 1 << S6_DMA_INT1_MASTER;
if (((tmp >> S6_DMA_MASTERERR_CHAN(1)) & S6_DMA_MASTERERR_CHAN_MASK)
== channel)
mask |= 1 << (S6_DMA_INT1_MASTER + 1);
if (((tmp >> S6_DMA_MASTERERR_CHAN(2)) & S6_DMA_MASTERERR_CHAN_MASK)
== channel)
mask |= 1 << (S6_DMA_INT1_MASTER + 2);
tmp = readl(dmac + S6_DMA_INTRAW1) & mask;
writel(tmp, dmac + S6_DMA_INTCLEAR1);
ret |= ((tmp >> channel) & 1) << 5;
ret |= ((tmp >> S6_DMA_INT1_MASTER) & S6_DMA_INT1_MASTER_MASK) << 6;
return ret;
}
void s6dmac_release_chan(u32 dmac, int chan)
{
if (chan >= 0)
s6dmac_disable_chan(dmac, chan);
}
/* global init */
static inline void __init dmac_init(u32 dmac, u8 chan_nb)
{
s6dmac_ctrl[S6_DMAC_INDEX(dmac)].dmac = dmac;
spin_lock_init(&s6dmac_ctrl[S6_DMAC_INDEX(dmac)].lock);
s6dmac_ctrl[S6_DMAC_INDEX(dmac)].chan_nb = chan_nb;
writel(S6_DMA_INT1_MASTER_MASK << S6_DMA_INT1_MASTER,
dmac + S6_DMA_INTCLEAR1);
}
static inline void __init dmac_master(u32 dmac,
u32 m0start, u32 m0end, u32 m1start, u32 m1end)
{
writel(m0start, dmac + S6_DMA_MASTER0START);
writel(m0end - 1, dmac + S6_DMA_MASTER0END);
writel(m1start, dmac + S6_DMA_MASTER1START);
writel(m1end - 1, dmac + S6_DMA_MASTER1END);
}
static void __init s6_dmac_init(void)
{
dmac_init(S6_REG_LMSDMA, S6_LMSDMA_NB);
dmac_master(S6_REG_LMSDMA,
S6_MEM_DDR, S6_MEM_PCIE_APER, S6_MEM_EFI, S6_MEM_GMAC);
dmac_init(S6_REG_NIDMA, S6_NIDMA_NB);
dmac_init(S6_REG_DPDMA, S6_DPDMA_NB);
dmac_master(S6_REG_DPDMA,
S6_MEM_DDR, S6_MEM_PCIE_APER, S6_REG_DP, S6_REG_DPDMA);
dmac_init(S6_REG_HIFDMA, S6_HIFDMA_NB);
dmac_master(S6_REG_HIFDMA,
S6_MEM_GMAC, S6_MEM_PCIE_CFG, S6_MEM_PCIE_APER, S6_MEM_AUX);
}
arch_initcall(s6_dmac_init);
arch/xtensa/variants/s6000/gpio.c deleted 100644 → 0
View file @ 3932b9ca
/*
* s6000 gpio driver
*
* Copyright (c) 2009 emlix GmbH
* Authors: Oskar Schirmer <oskar@scara.com>
* Johannes Weiner <hannes@cmpxchg.org>
* Daniel Gloeckner <dg@emlix.com>
*/
#include <linux/bitops.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/gpio.h>
#include <variant/hardware.h>
#define IRQ_BASE XTENSA_NR_IRQS
#define S6_GPIO_DATA 0x000
#define S6_GPIO_IS 0x404
#define S6_GPIO_IBE 0x408
#define S6_GPIO_IEV 0x40C
#define S6_GPIO_IE 0x410
#define S6_GPIO_RIS 0x414
#define S6_GPIO_MIS 0x418
#define S6_GPIO_IC 0x41C
#define S6_GPIO_AFSEL 0x420
#define S6_GPIO_DIR 0x800
#define S6_GPIO_BANK(nr) ((nr) * 0x1000)
#define S6_GPIO_MASK(nr) (4 << (nr))
#define S6_GPIO_OFFSET(nr) \
(S6_GPIO_BANK((nr) >> 3) + S6_GPIO_MASK((nr) & 7))
static int direction_input(struct gpio_chip *chip, unsigned int off)
{
writeb(0, S6_REG_GPIO + S6_GPIO_DIR + S6_GPIO_OFFSET(off));
return 0;
}
static int get(struct gpio_chip *chip, unsigned int off)
{
return readb(S6_REG_GPIO + S6_GPIO_DATA + S6_GPIO_OFFSET(off));
}
static int direction_output(struct gpio_chip *chip, unsigned int off, int val)
{
unsigned rel = S6_GPIO_OFFSET(off);
writeb(~0, S6_REG_GPIO + S6_GPIO_DIR + rel);
writeb(val ? ~0 : 0, S6_REG_GPIO + S6_GPIO_DATA + rel);
return 0;
}
static void set(struct gpio_chip *chip, unsigned int off, int val)
{
writeb(val ? ~0 : 0, S6_REG_GPIO + S6_GPIO_DATA + S6_GPIO_OFFSET(off));
}
static int to_irq(struct gpio_chip *chip, unsigned offset)
{
if (offset < 8)
return offset + IRQ_BASE;
return -EINVAL;
}
static struct gpio_chip gpiochip = {
.owner = THIS_MODULE,
.direction_input = direction_input,
.get = get,
.direction_output = direction_output,
.set = set,
.to_irq = to_irq,
.base = 0,
.ngpio = 24,
.can_sleep = 0, /* no blocking io needed */
.exported = 0, /* no exporting to userspace */
};
int s6_gpio_init(u32 afsel)
{
writeb(afsel, S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_AFSEL);
writeb(afsel >> 8, S6_REG_GPIO + S6_GPIO_BANK(1) + S6_GPIO_AFSEL);
writeb(afsel >> 16, S6_REG_GPIO + S6_GPIO_BANK(2) + S6_GPIO_AFSEL);
return gpiochip_add(&gpiochip);
}
static void ack(struct irq_data *d)
{
writeb(1 << (d->irq - IRQ_BASE), S6_REG_GPIO + S6_GPIO_IC);
}
static void mask(struct irq_data *d)
{
u8 r = readb(S6_REG_GPIO + S6_GPIO_IE);
r &= ~(1 << (d->irq - IRQ_BASE));
writeb(r, S6_REG_GPIO + S6_GPIO_IE);
}
static void unmask(struct irq_data *d)
{
u8 m = readb(S6_REG_GPIO + S6_GPIO_IE);
m |= 1 << (d->irq - IRQ_BASE);
writeb(m, S6_REG_GPIO + S6_GPIO_IE);
}
static int set_type(struct irq_data *d, unsigned int type)
{
const u8 m = 1 << (d->irq - IRQ_BASE);
irq_flow_handler_t handler;
u8 reg;
if (type == IRQ_TYPE_PROBE) {
if ((readb(S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_AFSEL) & m)
|| (readb(S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IE) & m)
|| readb(S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_DIR
+ S6_GPIO_MASK(irq - IRQ_BASE)))
return 0;
type = IRQ_TYPE_EDGE_BOTH;
}
reg = readb(S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IS);
if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) {
reg |= m;
handler = handle_level_irq;
} else {
reg &= ~m;
handler = handle_edge_irq;
}
writeb(reg, S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IS);
__irq_set_handler_locked(irq, handler);
reg = readb(S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IEV);
if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_EDGE_RISING))
reg |= m;
else
reg &= ~m;
writeb(reg, S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IEV);
reg = readb(S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IBE);
if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
reg |= m;
else
reg &= ~m;
writeb(reg, S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IBE);
return 0;
}
static struct irq_chip gpioirqs = {
.name = "GPIO",
.irq_ack = ack,
.irq_mask = mask,
.irq_unmask = unmask,
.irq_set_type = set_type,
};
static u8 demux_masks[4];
static void demux_irqs(unsigned int irq, struct irq_desc *desc)
{
struct irq_chip *chip = irq_desc_get_chip(desc);
u8 *mask = irq_desc_get_handler_data(desc);
u8 pending;
int cirq;
chip->irq_mask(&desc->irq_data);
chip->irq_ack(&desc->irq_data);
pending = readb(S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_MIS) & *mask;
cirq = IRQ_BASE - 1;
while (pending) {
int n = ffs(pending);
cirq += n;
pending >>= n;
generic_handle_irq(cirq);
}
chip->irq_unmask(&desc->irq_data);
}
extern const signed char *platform_irq_mappings[XTENSA_NR_IRQS];
void __init variant_init_irq(void)
{
int irq, n;
writeb(0, S6_REG_GPIO + S6_GPIO_BANK(0) + S6_GPIO_IE);
for (irq = n = 0; irq < XTENSA_NR_IRQS; irq++) {
const signed char *mapping = platform_irq_mappings[irq];
int alone = 1;
u8 mask;
if (!mapping)
continue;
for(mask = 0; *mapping != -1; mapping++)
switch (*mapping) {
case S6_INTC_GPIO(0):
mask |= 1 << 0;
break;
case S6_INTC_GPIO(1):
mask |= 1 << 1;
break;
case S6_INTC_GPIO(2):
mask |= 1 << 2;
break;
case S6_INTC_GPIO(3):
mask |= 0x1f << 3;
break;
default:
alone = 0;
}
if (mask) {
int cirq, i;
if (!alone) {
printk(KERN_ERR "chained irq chips can't share"
" parent irq %i\n", irq);
continue;
}
demux_masks[n] = mask;
cirq = IRQ_BASE - 1;
do {
i = ffs(mask);
cirq += i;
mask >>= i;
irq_set_chip(cirq, &gpioirqs);
irq_set_irq_type(irq, IRQ_TYPE_LEVEL_LOW);
} while (mask);
irq_set_handler_data(irq, demux_masks + n);
irq_set_chained_handler(irq, demux_irqs);
if (++n == ARRAY_SIZE(demux_masks))
break;
}
}
}
arch/xtensa/variants/s6000/include/variant/core.h deleted 100644 → 0
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arch/xtensa/variants/s6000/include/variant/dmac.h deleted 100644 → 0
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arch/xtensa/variants/s6000/include/variant/gpio.h deleted 100644 → 0
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#ifndef _XTENSA_VARIANT_S6000_GPIO_H
#define _XTENSA_VARIANT_S6000_GPIO_H
extern int s6_gpio_init(u32 afsel);
#endif /* _XTENSA_VARIANT_S6000_GPIO_H */
arch/xtensa/variants/s6000/include/variant/hardware.h deleted 100644 → 0
View file @ 3932b9ca
#ifndef __XTENSA_S6000_HARDWARE_H
#define __XTENSA_S6000_HARDWARE_H
#define S6_SCLK 1843200
#define S6_MEM_REG 0x20000000
#define S6_MEM_EFI 0x33F00000
#define S6_MEM_PCIE_DATARAM1 0x34000000
#define S6_MEM_XLMI 0x37F80000
#define S6_MEM_PIF_DATARAM1 0x37FFC000
#define S6_MEM_GMAC 0x38000000
#define S6_MEM_I2S 0x3A000000
#define S6_MEM_EGIB 0x3C000000
#define S6_MEM_PCIE_CFG 0x3E000000
#define S6_MEM_PIF_DATARAM 0x3FFE0000
#define S6_MEM_XLMI_DATARAM 0x3FFF0000
#define S6_MEM_DDR 0x40000000
#define S6_MEM_PCIE_APER 0xC0000000
#define S6_MEM_AUX 0xF0000000
/* Device addresses */
#define S6_REG_SCB S6_MEM_REG
#define S6_REG_NB (S6_REG_SCB + 0x10000)
#define S6_REG_LMSDMA (S6_REG_SCB + 0x20000)
#define S6_REG_NI (S6_REG_SCB + 0x30000)
#define S6_REG_NIDMA (S6_REG_SCB + 0x40000)
#define S6_REG_NS (S6_REG_SCB + 0x50000)
#define S6_REG_DDR (S6_REG_SCB + 0x60000)
#define S6_REG_GREG1 (S6_REG_SCB + 0x70000)
#define S6_REG_DP (S6_REG_SCB + 0x80000)
#define S6_REG_DPDMA (S6_REG_SCB + 0x90000)
#define S6_REG_EGIB (S6_REG_SCB + 0xA0000)
#define S6_REG_PCIE (S6_REG_SCB + 0xB0000)
#define S6_REG_I2S (S6_REG_SCB + 0xC0000)
#define S6_REG_GMAC (S6_REG_SCB + 0xD0000)
#define S6_REG_HIFDMA (S6_REG_SCB + 0xE0000)
#define S6_REG_GREG2 (S6_REG_SCB + 0xF0000)
#define S6_REG_APB S6_REG_SCB
#define S6_REG_UART (S6_REG_APB + 0x0000)
#define S6_REG_INTC (S6_REG_APB + 0x2000)
#define S6_REG_SPI (S6_REG_APB + 0x3000)
#define S6_REG_I2C (S6_REG_APB + 0x4000)
#define S6_REG_GPIO (S6_REG_APB + 0x8000)
/* Global register block */
#define S6_GREG1_PLL_LOCKCLEAR 0x000
#define S6_GREG1_PLL_LOCK_SYS 0
#define S6_GREG1_PLL_LOCK_IO 1
#define S6_GREG1_PLL_LOCK_AIM 2
#define S6_GREG1_PLL_LOCK_DP0 3
#define S6_GREG1_PLL_LOCK_DP2 4
#define S6_GREG1_PLL_LOCK_DDR 5
#define S6_GREG1_PLL_LOCKSTAT 0x004
#define S6_GREG1_PLL_LOCKSTAT_CURLOCK 0
#define S6_GREG1_PLL_LOCKSTAT_EVERUNLCK 8
#define S6_GREG1_PLLSEL 0x010
#define S6_GREG1_PLLSEL_AIM 0
#define S6_GREG1_PLLSEL_AIM_DDR2 0
#define S6_GREG1_PLLSEL_AIM_300MHZ 1
#define S6_GREG1_PLLSEL_AIM_240MHZ 2
#define S6_GREG1_PLLSEL_AIM_200MHZ 3
#define S6_GREG1_PLLSEL_AIM_150MHZ 4
#define S6_GREG1_PLLSEL_AIM_120MHZ 5
#define S6_GREG1_PLLSEL_AIM_40MHZ 6
#define S6_GREG1_PLLSEL_AIM_PLLAIMREF 7
#define S6_GREG1_PLLSEL_AIM_MASK 7
#define S6_GREG1_PLLSEL_DDR 8
#define S6_GREG1_PLLSEL_DDR_HS 0
#define S6_GREG1_PLLSEL_DDR_333MHZ 1
#define S6_GREG1_PLLSEL_DDR_250MHZ 2
#define S6_GREG1_PLLSEL_DDR_200MHZ 3
#define S6_GREG1_PLLSEL_DDR_167MHZ 4
#define S6_GREG1_PLLSEL_DDR_100MHZ 5
#define S6_GREG1_PLLSEL_DDR_33MHZ 6
#define S6_GREG1_PLLSEL_DDR_PLLIOREF 7
#define S6_GREG1_PLLSEL_DDR_MASK 7
#define S6_GREG1_PLLSEL_GMAC 16
#define S6_GREG1_PLLSEL_GMAC_125MHZ 0
#define S6_GREG1_PLLSEL_GMAC_25MHZ 1
#define S6_GREG1_PLLSEL_GMAC_2500KHZ 2
#define S6_GREG1_PLLSEL_GMAC_EXTERN 3
#define S6_GREG1_PLLSEL_GMAC_MASK 3
#define S6_GREG1_PLLSEL_GMII 18
#define S6_GREG1_PLLSEL_GMII_111MHZ 0
#define S6_GREG1_PLLSEL_GMII_IOREF 1
#define S6_GREG1_PLLSEL_GMII_NONE 2
#define S6_GREG1_PLLSEL_GMII_125MHZ 3
#define S6_GREG1_PLLSEL_GMII_MASK 3
#define S6_GREG1_SYSUNLOCKCNT 0x020
#define S6_GREG1_IOUNLOCKCNT 0x024
#define S6_GREG1_AIMUNLOCKCNT 0x028
#define S6_GREG1_DP0UNLOCKCNT 0x02C
#define S6_GREG1_DP2UNLOCKCNT 0x030
#define S6_GREG1_DDRUNLOCKCNT 0x034
#define S6_GREG1_CLKBAL0 0x040
#define S6_GREG1_CLKBAL0_LSGB 0
#define S6_GREG1_CLKBAL0_LSPX 8
#define S6_GREG1_CLKBAL0_MEMDO 16
#define S6_GREG1_CLKBAL0_HSXT1 24
#define S6_GREG1_CLKBAL1 0x044
#define S6_GREG1_CLKBAL1_HSISEF 0
#define S6_GREG1_CLKBAL1_HSNI 8
#define S6_GREG1_CLKBAL1_HSNS 16
#define S6_GREG1_CLKBAL1_HSISEFCFG 24
#define S6_GREG1_CLKBAL2 0x048
#define S6_GREG1_CLKBAL2_LSNB 0
#define S6_GREG1_CLKBAL2_LSSB 8
#define S6_GREG1_CLKBAL2_LSREST 24
#define S6_GREG1_CLKBAL3 0x04C
#define S6_GREG1_CLKBAL3_ISEFXAD 0
#define S6_GREG1_CLKBAL3_ISEFLMS 8
#define S6_GREG1_CLKBAL3_ISEFISEF 16
#define S6_GREG1_CLKBAL3_DDRDD 24
#define S6_GREG1_CLKBAL4 0x050
#define S6_GREG1_CLKBAL4_DDRDP 0
#define S6_GREG1_CLKBAL4_DDRDO 8
#define S6_GREG1_CLKBAL4_DDRNB 16
#define S6_GREG1_CLKBAL4_DDRLMS 24
#define S6_GREG1_BLOCKENA 0x100
#define S6_GREG1_BLOCK_DDR 0
#define S6_GREG1_BLOCK_DP 1
#define S6_GREG1_BLOCK_NSNI 2
#define S6_GREG1_BLOCK_PCIE 3
#define S6_GREG1_BLOCK_GMAC 4
#define S6_GREG1_BLOCK_I2S 5
#define S6_GREG1_BLOCK_EGIB 6
#define S6_GREG1_BLOCK_SB 7
#define S6_GREG1_BLOCK_XT1 8
#define S6_GREG1_CLKGATE 0x104
#define S6_GREG1_BGATE_AIMNORTH 9
#define S6_GREG1_BGATE_AIMEAST 10
#define S6_GREG1_BGATE_AIMWEST 11
#define S6_GREG1_BGATE_AIMSOUTH 12
#define S6_GREG1_CHIPRES 0x108
#define S6_GREG1_CHIPRES_SOFTRES 0
#define S6_GREG1_CHIPRES_LOSTLOCK 1
#define S6_GREG1_RESETCAUSE 0x10C
#define S6_GREG1_RESETCAUSE_RESETN 0
#define S6_GREG1_RESETCAUSE_GLOBAL 1
#define S6_GREG1_RESETCAUSE_WDOGTIMER 2
#define S6_GREG1_RESETCAUSE_SWCHIP 3
#define S6_GREG1_RESETCAUSE_PLLSYSLOSS 4
#define S6_GREG1_RESETCAUSE_PCIE 5
#define S6_GREG1_RESETCAUSE_CREATEDGLOB 6
#define S6_GREG1_REFCLOCKCNT 0x110
#define S6_GREG1_RESETTIMER 0x114
#define S6_GREG1_NMITIMER 0x118
#define S6_GREG1_GLOBAL_TIMER 0x11C
#define S6_GREG1_TIMER0 0x180
#define S6_GREG1_TIMER1 0x184
#define S6_GREG1_UARTCLOCKSEL 0x204
#define S6_GREG1_CHIPVERSPACKG 0x208
#define S6_GREG1_CHIPVERSPACKG_CHIPVID 0
#define S6_GREG1_CHIPVERSPACKG_PACKSEL 8
#define S6_GREG1_ONDIETERMCTRL 0x20C
#define S6_GREG1_ONDIETERMCTRL_WEST 0
#define S6_GREG1_ONDIETERMCTRL_NORTH 2
#define S6_GREG1_ONDIETERMCTRL_EAST 4
#define S6_GREG1_ONDIETERMCTRL_SOUTH 6
#define S6_GREG1_ONDIETERMCTRL_NONE 0
#define S6_GREG1_ONDIETERMCTRL_75OHM 2
#define S6_GREG1_ONDIETERMCTRL_MASK 3
#define S6_GREG1_BOOT_CFG0 0x210
#define S6_GREG1_BOOT_CFG0_AIMSTRONG 1
#define S6_GREG1_BOOT_CFG0_MINIBOOTDL 2
#define S6_GREG1_BOOT_CFG0_OCDGPIO8SET 5
#define S6_GREG1_BOOT_CFG0_OCDGPIOENA 6
#define S6_GREG1_BOOT_CFG0_DOWNSTREAM 7
#define S6_GREG1_BOOT_CFG0_PLLSYSDIV 8
#define S6_GREG1_BOOT_CFG0_PLLSYSDIV_300MHZ 1
#define S6_GREG1_BOOT_CFG0_PLLSYSDIV_240MHZ 2
#define S6_GREG1_BOOT_CFG0_PLLSYSDIV_200MHZ 3
#define S6_GREG1_BOOT_CFG0_PLLSYSDIV_150MHZ 4
#define S6_GREG1_BOOT_CFG0_PLLSYSDIV_120MHZ 5
#define S6_GREG1_BOOT_CFG0_PLLSYSDIV_40MHZ 6
#define S6_GREG1_BOOT_CFG0_PLLSYSDIV_MASK 7
#define S6_GREG1_BOOT_CFG0_BALHSLMS 12
#define S6_GREG1_BOOT_CFG0_BALHSNB 18
#define S6_GREG1_BOOT_CFG0_BALHSXAD 24
#define S6_GREG1_BOOT_CFG1 0x214
#define S6_GREG1_BOOT_CFG1_PCIE1LANE 1
#define S6_GREG1_BOOT_CFG1_MPLLPRESCALE 2
#define S6_GREG1_BOOT_CFG1_MPLLNCY 4
#define S6_GREG1_BOOT_CFG1_MPLLNCY5 9
#define S6_GREG1_BOOT_CFG1_BALHSREST 14
#define S6_GREG1_BOOT_CFG1_BALHSPSMEMS 20
#define S6_GREG1_BOOT_CFG1_BALLSGI 26
#define S6_GREG1_BOOT_CFG2 0x218
#define S6_GREG1_BOOT_CFG2_PEID 0
#define S6_GREG1_BOOT_CFG3 0x21C
#define S6_GREG1_DRAMBUSYHOLDOF 0x220
#define S6_GREG1_DRAMBUSYHOLDOF_XT0 0
#define S6_GREG1_DRAMBUSYHOLDOF_XT1 4
#define S6_GREG1_DRAMBUSYHOLDOF_XT_MASK 7
#define S6_GREG1_PCIEBAR1SIZE 0x224
#define S6_GREG1_PCIEBAR2SIZE 0x228
#define S6_GREG1_PCIEVENDOR 0x22C
#define S6_GREG1_PCIEDEVICE 0x230
#define S6_GREG1_PCIEREV 0x234
#define S6_GREG1_PCIECLASS 0x238
#define S6_GREG1_XT1DCACHEMISS 0x240
#define S6_GREG1_XT1ICACHEMISS 0x244
#define S6_GREG1_HWSEMAPHORE(n) (0x400 + 4 * (n))
#define S6_GREG1_HWSEMAPHORE_NB 16
/* peripheral interrupt numbers */
#define S6_INTC_GPIO(n) (n) /* 0..3 */
#define S6_INTC_I2C 4
#define S6_INTC_SPI 5
#define S6_INTC_NB_ERR 6
#define S6_INTC_DMA_LMSERR 7
#define S6_INTC_DMA_LMSLOWWMRK(n) (8 + (n)) /* 0..11 */
#define S6_INTC_DMA_LMSPENDCNT(n) (20 + (n)) /* 0..11 */
#define S6_INTC_DMA HOSTLOWWMRK(n) (32 + (n)) /* 0..6 */
#define S6_INTC_DMA_HOSTPENDCNT(n) (39 + (n)) /* 0..6 */
#define S6_INTC_DMA_HOSTERR 46
#define S6_INTC_UART(n) (47 + (n)) /* 0..1 */
#define S6_INTC_XAD 49
#define S6_INTC_NI_ERR 50
#define S6_INTC_NI_INFIFOFULL 51
#define S6_INTC_DMA_NIERR 52
#define S6_INTC_DMA_NILOWWMRK(n) (53 + (n)) /* 0..3 */
#define S6_INTC_DMA_NIPENDCNT(n) (57 + (n)) /* 0..3 */
#define S6_INTC_DDR 61
#define S6_INTC_NS_ERR 62
#define S6_INTC_EFI_CFGERR 63
#define S6_INTC_EFI_ISEFTEST 64
#define S6_INTC_EFI_WRITEERR 65
#define S6_INTC_NMI_TIMER 66
#define S6_INTC_PLLLOCK_SYS 67
#define S6_INTC_PLLLOCK_IO 68
#define S6_INTC_PLLLOCK_AIM 69
#define S6_INTC_PLLLOCK_DP0 70
#define S6_INTC_PLLLOCK_DP2 71
#define S6_INTC_I2S_ERR 72
#define S6_INTC_GMAC_STAT 73
#define S6_INTC_GMAC_ERR 74
#define S6_INTC_GIB_ERR 75
#define S6_INTC_PCIE_ERR 76
#define S6_INTC_PCIE_MSI(n) (77 + (n)) /* 0..3 */
#define S6_INTC_PCIE_INTA 81
#define S6_INTC_PCIE_INTB 82
#define S6_INTC_PCIE_INTC 83
#define S6_INTC_PCIE_INTD 84
#define S6_INTC_SW(n) (85 + (n)) /* 0..9 */
#define S6_INTC_SW_ENABLE(n) (85 + 256 + (n))
#define S6_INTC_DMA_DP_ERR 95
#define S6_INTC_DMA_DPLOWWMRK(n) (96 + (n)) /* 0..3 */
#define S6_INTC_DMA_DPPENDCNT(n) (100 + (n)) /* 0..3 */
#define S6_INTC_DMA_DPTERMCNT(n) (104 + (n)) /* 0..3 */
#define S6_INTC_TIMER0 108
#define S6_INTC_TIMER1 109
#define S6_INTC_DMA_HOSTTERMCNT(n) (110 + (n)) /* 0..6 */
#endif /* __XTENSA_S6000_HARDWARE_H */
arch/xtensa/variants/s6000/include/variant/irq.h deleted 100644 → 0
View file @ 3932b9ca
#ifndef _XTENSA_S6000_IRQ_H
#define _XTENSA_S6000_IRQ_H
#define VARIANT_NR_IRQS 8 /* GPIO interrupts */
extern void variant_irq_enable(unsigned int irq);
#endif /* __XTENSA_S6000_IRQ_H */
arch/xtensa/variants/s6000/include/variant/tie-asm.h deleted 100644 → 0
View file @ 3932b9ca
/*
* This header file contains assembly-language definitions (assembly
* macros, etc.) for this specific Xtensa processor's TIE extensions
* and options. It is customized to this Xtensa processor configuration.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1999-2008 Tensilica Inc.
*/
#ifndef _XTENSA_CORE_TIE_ASM_H
#define _XTENSA_CORE_TIE_ASM_H
/* Selection parameter values for save-area save/restore macros: */
/* Option vs. TIE: */
#define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */
#define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */
/* Whether used automatically by compiler: */
#define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */
#define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */
/* ABI handling across function calls: */
#define XTHAL_SAS_CALR 0x0010 /* caller-saved */
#define XTHAL_SAS_CALE 0x0020 /* callee-saved */
#define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */
/* Misc */
#define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */
/* Macro to save all non-coprocessor (extra) custom TIE and optional state
* (not including zero-overhead loop registers).
* Save area ptr (clobbered): ptr (16 byte aligned)
* Scratch regs (clobbered): at1..at4 (only first XCHAL_NCP_NUM_ATMPS needed)
*/
.macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL
xchal_sa_start \continue, \ofs
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
xchal_sa_align \ptr, 0, 1024-4, 4, 4
rsr \at1, BR // boolean option
s32i \at1, \ptr, .Lxchal_ofs_ + 0
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
.endif
.endm // xchal_ncp_store
/* Macro to save all non-coprocessor (extra) custom TIE and optional state
* (not including zero-overhead loop registers).
* Save area ptr (clobbered): ptr (16 byte aligned)
* Scratch regs (clobbered): at1..at4 (only first XCHAL_NCP_NUM_ATMPS needed)
*/
.macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL
xchal_sa_start \continue, \ofs
.ifeq (XTHAL_SAS_OPT | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
xchal_sa_align \ptr, 0, 1024-4, 4, 4
l32i \at1, \ptr, .Lxchal_ofs_ + 0
wsr \at1, BR // boolean option
.set .Lxchal_ofs_, .Lxchal_ofs_ + 4
.endif
.endm // xchal_ncp_load
#define XCHAL_NCP_NUM_ATMPS 1
/* Macro to save the state of TIE coprocessor FPU.
* Save area ptr (clobbered): ptr (16 byte aligned)
* Scratch regs (clobbered): at1..at4 (only first XCHAL_CP0_NUM_ATMPS needed)
*/
#define xchal_cp_FPU_store xchal_cp0_store
/* #define xchal_cp_FPU_store_a2 xchal_cp0_store a2 a3 a4 a5 a6 */
.macro xchal_cp0_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL
xchal_sa_start \continue, \ofs
.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
xchal_sa_align \ptr, 0, 0, 1, 16
rur232 \at1 // FCR
s32i \at1, \ptr, 0
rur233 \at1 // FSR
s32i \at1, \ptr, 4
SSI f0, \ptr, 8
SSI f1, \ptr, 12
SSI f2, \ptr, 16
SSI f3, \ptr, 20
SSI f4, \ptr, 24
SSI f5, \ptr, 28
SSI f6, \ptr, 32
SSI f7, \ptr, 36
SSI f8, \ptr, 40
SSI f9, \ptr, 44
SSI f10, \ptr, 48
SSI f11, \ptr, 52
SSI f12, \ptr, 56
SSI f13, \ptr, 60
SSI f14, \ptr, 64
SSI f15, \ptr, 68
.set .Lxchal_ofs_, .Lxchal_ofs_ + 72
.endif
.endm // xchal_cp0_store
/* Macro to restore the state of TIE coprocessor FPU.
* Save area ptr (clobbered): ptr (16 byte aligned)
* Scratch regs (clobbered): at1..at4 (only first XCHAL_CP0_NUM_ATMPS needed)
*/
#define xchal_cp_FPU_load xchal_cp0_load
/* #define xchal_cp_FPU_load_a2 xchal_cp0_load a2 a3 a4 a5 a6 */
.macro xchal_cp0_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL
xchal_sa_start \continue, \ofs
.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
xchal_sa_align \ptr, 0, 0, 1, 16
l32i \at1, \ptr, 0
wur232 \at1 // FCR
l32i \at1, \ptr, 4
wur233 \at1 // FSR
LSI f0, \ptr, 8
LSI f1, \ptr, 12
LSI f2, \ptr, 16
LSI f3, \ptr, 20
LSI f4, \ptr, 24
LSI f5, \ptr, 28
LSI f6, \ptr, 32
LSI f7, \ptr, 36
LSI f8, \ptr, 40
LSI f9, \ptr, 44
LSI f10, \ptr, 48
LSI f11, \ptr, 52
LSI f12, \ptr, 56
LSI f13, \ptr, 60
LSI f14, \ptr, 64
LSI f15, \ptr, 68
.set .Lxchal_ofs_, .Lxchal_ofs_ + 72
.endif
.endm // xchal_cp0_load
#define XCHAL_CP0_NUM_ATMPS 1
/* Macro to save the state of TIE coprocessor XAD.
* Save area ptr (clobbered): ptr (16 byte aligned)
* Scratch regs (clobbered): at1..at4 (only first XCHAL_CP6_NUM_ATMPS needed)
*/
#define xchal_cp_XAD_store xchal_cp6_store
/* #define xchal_cp_XAD_store_a2 xchal_cp6_store a2 a3 a4 a5 a6 */
.macro xchal_cp6_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL
xchal_sa_start \continue, \ofs
.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
xchal_sa_align \ptr, 0, 0, 1, 16
rur0 \at1 // LDCBHI
s32i \at1, \ptr, 0
rur1 \at1 // LDCBLO
s32i \at1, \ptr, 4
rur2 \at1 // STCBHI
s32i \at1, \ptr, 8
rur3 \at1 // STCBLO
s32i \at1, \ptr, 12
rur8 \at1 // LDBRBASE
s32i \at1, \ptr, 16
rur9 \at1 // LDBROFF
s32i \at1, \ptr, 20
rur10 \at1 // LDBRINC
s32i \at1, \ptr, 24
rur11 \at1 // STBRBASE
s32i \at1, \ptr, 28
rur12 \at1 // STBROFF
s32i \at1, \ptr, 32
rur13 \at1 // STBRINC
s32i \at1, \ptr, 36
rur24 \at1 // SCRATCH0
s32i \at1, \ptr, 40
rur25 \at1 // SCRATCH1
s32i \at1, \ptr, 44
rur26 \at1 // SCRATCH2
s32i \at1, \ptr, 48
rur27 \at1 // SCRATCH3
s32i \at1, \ptr, 52
WRAS128I wra0, \ptr, 64
WRAS128I wra1, \ptr, 80
WRAS128I wra2, \ptr, 96
WRAS128I wra3, \ptr, 112
WRAS128I wra4, \ptr, 128
WRAS128I wra5, \ptr, 144
WRAS128I wra6, \ptr, 160
WRAS128I wra7, \ptr, 176
WRAS128I wra8, \ptr, 192
WRAS128I wra9, \ptr, 208
WRAS128I wra10, \ptr, 224
WRAS128I wra11, \ptr, 240
WRAS128I wra12, \ptr, 256
WRAS128I wra13, \ptr, 272
WRAS128I wra14, \ptr, 288
WRAS128I wra15, \ptr, 304
WRBS128I wrb0, \ptr, 320
WRBS128I wrb1, \ptr, 336
WRBS128I wrb2, \ptr, 352
WRBS128I wrb3, \ptr, 368
WRBS128I wrb4, \ptr, 384
WRBS128I wrb5, \ptr, 400
WRBS128I wrb6, \ptr, 416
WRBS128I wrb7, \ptr, 432
WRBS128I wrb8, \ptr, 448
WRBS128I wrb9, \ptr, 464
WRBS128I wrb10, \ptr, 480
WRBS128I wrb11, \ptr, 496
WRBS128I wrb12, \ptr, 512
WRBS128I wrb13, \ptr, 528
WRBS128I wrb14, \ptr, 544
WRBS128I wrb15, \ptr, 560
.set .Lxchal_ofs_, .Lxchal_ofs_ + 576
.endif
.endm // xchal_cp6_store
/* Macro to restore the state of TIE coprocessor XAD.
* Save area ptr (clobbered): ptr (16 byte aligned)
* Scratch regs (clobbered): at1..at4 (only first XCHAL_CP6_NUM_ATMPS needed)
*/
#define xchal_cp_XAD_load xchal_cp6_load
/* #define xchal_cp_XAD_load_a2 xchal_cp6_load a2 a3 a4 a5 a6 */
.macro xchal_cp6_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL
xchal_sa_start \continue, \ofs
.ifeq (XTHAL_SAS_TIE | XTHAL_SAS_NOCC | XTHAL_SAS_CALR) & ~\select
xchal_sa_align \ptr, 0, 0, 1, 16
l32i \at1, \ptr, 0
wur0 \at1 // LDCBHI
l32i \at1, \ptr, 4
wur1 \at1 // LDCBLO
l32i \at1, \ptr, 8
wur2 \at1 // STCBHI
l32i \at1, \ptr, 12
wur3 \at1 // STCBLO
l32i \at1, \ptr, 16
wur8 \at1 // LDBRBASE
l32i \at1, \ptr, 20
wur9 \at1 // LDBROFF
l32i \at1, \ptr, 24
wur10 \at1 // LDBRINC
l32i \at1, \ptr, 28
wur11 \at1 // STBRBASE
l32i \at1, \ptr, 32
wur12 \at1 // STBROFF
l32i \at1, \ptr, 36
wur13 \at1 // STBRINC
l32i \at1, \ptr, 40
wur24 \at1 // SCRATCH0
l32i \at1, \ptr, 44
wur25 \at1 // SCRATCH1
l32i \at1, \ptr, 48
wur26 \at1 // SCRATCH2
l32i \at1, \ptr, 52
wur27 \at1 // SCRATCH3
WRBL128I wrb0, \ptr, 320
WRBL128I wrb1, \ptr, 336
WRBL128I wrb2, \ptr, 352
WRBL128I wrb3, \ptr, 368
WRBL128I wrb4, \ptr, 384
WRBL128I wrb5, \ptr, 400
WRBL128I wrb6, \ptr, 416
WRBL128I wrb7, \ptr, 432
WRBL128I wrb8, \ptr, 448
WRBL128I wrb9, \ptr, 464
WRBL128I wrb10, \ptr, 480
WRBL128I wrb11, \ptr, 496
WRBL128I wrb12, \ptr, 512
WRBL128I wrb13, \ptr, 528
WRBL128I wrb14, \ptr, 544
WRBL128I wrb15, \ptr, 560
WRAL128I wra0, \ptr, 64
WRAL128I wra1, \ptr, 80
WRAL128I wra2, \ptr, 96
WRAL128I wra3, \ptr, 112
WRAL128I wra4, \ptr, 128
WRAL128I wra5, \ptr, 144
WRAL128I wra6, \ptr, 160
WRAL128I wra7, \ptr, 176
WRAL128I wra8, \ptr, 192
WRAL128I wra9, \ptr, 208
WRAL128I wra10, \ptr, 224
WRAL128I wra11, \ptr, 240
WRAL128I wra12, \ptr, 256
WRAL128I wra13, \ptr, 272
WRAL128I wra14, \ptr, 288
WRAL128I wra15, \ptr, 304
.set .Lxchal_ofs_, .Lxchal_ofs_ + 576
.endif
.endm // xchal_cp6_load
#define XCHAL_CP6_NUM_ATMPS 1
#define XCHAL_SA_NUM_ATMPS 1
/* Empty macros for unconfigured coprocessors: */
.macro xchal_cp1_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp1_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp2_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp2_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp3_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp3_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp4_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp4_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp5_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp5_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp7_store p a b c d continue=0 ofs=-1 select=-1 ; .endm
.macro xchal_cp7_load p a b c d continue=0 ofs=-1 select=-1 ; .endm
#endif /*_XTENSA_CORE_TIE_ASM_H*/
arch/xtensa/variants/s6000/include/variant/tie.h deleted 100644 → 0
View file @ 3932b9ca
/*
* This header file describes this specific Xtensa processor's TIE extensions
* that extend basic Xtensa core functionality. It is customized to this
* Xtensa processor configuration.
*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 1999-2008 Tensilica Inc.
*/
#ifndef _XTENSA_CORE_TIE_H
#define _XTENSA_CORE_TIE_H
#define XCHAL_CP_NUM 2 /* number of coprocessors */
#define XCHAL_CP_MAX 7 /* max CP ID + 1 (0 if none) */
#define XCHAL_CP_MASK 0x41 /* bitmask of all CPs by ID */
#define XCHAL_CP_PORT_MASK 0x00 /* bitmask of only port CPs */
/* Basic parameters of each coprocessor: */
#define XCHAL_CP0_NAME "FPU"
#define XCHAL_CP0_IDENT FPU
#define XCHAL_CP0_SA_SIZE 72 /* size of state save area */
#define XCHAL_CP0_SA_ALIGN 4 /* min alignment of save area */
#define XCHAL_CP_ID_FPU 0 /* coprocessor ID (0..7) */
#define XCHAL_CP6_NAME "XAD"
#define XCHAL_CP6_IDENT XAD
#define XCHAL_CP6_SA_SIZE 576 /* size of state save area */
#define XCHAL_CP6_SA_ALIGN 16 /* min alignment of save area */
#define XCHAL_CP_ID_XAD 6 /* coprocessor ID (0..7) */
/* Filler info for unassigned coprocessors, to simplify arrays etc: */
#define XCHAL_CP1_SA_SIZE 0
#define XCHAL_CP1_SA_ALIGN 1
#define XCHAL_CP2_SA_SIZE 0
#define XCHAL_CP2_SA_ALIGN 1
#define XCHAL_CP3_SA_SIZE 0
#define XCHAL_CP3_SA_ALIGN 1
#define XCHAL_CP4_SA_SIZE 0
#define XCHAL_CP4_SA_ALIGN 1
#define XCHAL_CP5_SA_SIZE 0
#define XCHAL_CP5_SA_ALIGN 1
#define XCHAL_CP7_SA_SIZE 0
#define XCHAL_CP7_SA_ALIGN 1
/* Save area for non-coprocessor optional and custom (TIE) state: */
#define XCHAL_NCP_SA_SIZE 4
#define XCHAL_NCP_SA_ALIGN 4
/* Total save area for optional and custom state (NCP + CPn): */
#define XCHAL_TOTAL_SA_SIZE 672 /* with 16-byte align padding */
#define XCHAL_TOTAL_SA_ALIGN 16 /* actual minimum alignment */
/*
* Detailed contents of save areas.
* NOTE: caller must define the XCHAL_SA_REG macro (not defined here)
* before expanding the XCHAL_xxx_SA_LIST() macros.
*
* XCHAL_SA_REG(s,ccused,abikind,kind,opt,name,galign,align,asize,
* dbnum,base,regnum,bitsz,gapsz,reset,x...)
*
* s = passed from XCHAL_*_LIST(s), eg. to select how to expand
* ccused = set if used by compiler without special options or code
* abikind = 0 (caller-saved), 1 (callee-saved), or 2 (thread-global)
* kind = 0 (special reg), 1 (TIE user reg), or 2 (TIE regfile reg)
* opt = 0 (custom TIE extension or coprocessor), or 1 (optional reg)
* name = lowercase reg name (no quotes)
* galign = group byte alignment (power of 2) (galign >= align)
* align = register byte alignment (power of 2)
* asize = allocated size in bytes (asize*8 == bitsz + gapsz + padsz)
* (not including any pad bytes required to galign this or next reg)
* dbnum = unique target number f/debug (see <xtensa-libdb-macros.h>)
* base = reg shortname w/o index (or sr=special, ur=TIE user reg)
* regnum = reg index in regfile, or special/TIE-user reg number
* bitsz = number of significant bits (regfile width, or ur/sr mask bits)
* gapsz = intervening bits, if bitsz bits not stored contiguously
* (padsz = pad bits at end [TIE regfile] or at msbits [ur,sr] of asize)
* reset = register reset value (or 0 if undefined at reset)
* x = reserved for future use (0 until then)
*
* To filter out certain registers, e.g. to expand only the non-global
* registers used by the compiler, you can do something like this:
*
* #define XCHAL_SA_REG(s,ccused,p...) SELCC##ccused(p)
* #define SELCC0(p...)
* #define SELCC1(abikind,p...) SELAK##abikind(p)
* #define SELAK0(p...) REG(p)
* #define SELAK1(p...) REG(p)
* #define SELAK2(p...)
* #define REG(kind,tie,name,galn,aln,asz,csz,dbnum,base,rnum,bsz,rst,x...) \
* ...what you want to expand...
*/
#define XCHAL_NCP_SA_NUM 1
#define XCHAL_NCP_SA_LIST(s) \
XCHAL_SA_REG(s,0,0,0,1, br, 4, 4, 4,0x0204, sr,4 , 16,0,0,0)
#define XCHAL_CP0_SA_NUM 18
#define XCHAL_CP0_SA_LIST(s) \
XCHAL_SA_REG(s,0,0,1,0, fcr, 4, 4, 4,0x03E8, ur,232, 32,0,0,0) \
XCHAL_SA_REG(s,0,0,1,0, fsr, 4, 4, 4,0x03E9, ur,233, 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f0, 4, 4, 4,0x0030, f,0 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f1, 4, 4, 4,0x0031, f,1 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f2, 4, 4, 4,0x0032, f,2 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f3, 4, 4, 4,0x0033, f,3 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f4, 4, 4, 4,0x0034, f,4 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f5, 4, 4, 4,0x0035, f,5 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f6, 4, 4, 4,0x0036, f,6 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f7, 4, 4, 4,0x0037, f,7 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f8, 4, 4, 4,0x0038, f,8 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f9, 4, 4, 4,0x0039, f,9 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f10, 4, 4, 4,0x003A, f,10 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f11, 4, 4, 4,0x003B, f,11 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f12, 4, 4, 4,0x003C, f,12 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f13, 4, 4, 4,0x003D, f,13 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f14, 4, 4, 4,0x003E, f,14 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, f15, 4, 4, 4,0x003F, f,15 , 32,0,0,0)
#define XCHAL_CP1_SA_NUM 0
#define XCHAL_CP1_SA_LIST(s) /* empty */
#define XCHAL_CP2_SA_NUM 0
#define XCHAL_CP2_SA_LIST(s) /* empty */
#define XCHAL_CP3_SA_NUM 0
#define XCHAL_CP3_SA_LIST(s) /* empty */
#define XCHAL_CP4_SA_NUM 0
#define XCHAL_CP4_SA_LIST(s) /* empty */
#define XCHAL_CP5_SA_NUM 0
#define XCHAL_CP5_SA_LIST(s) /* empty */
#define XCHAL_CP6_SA_NUM 46
#define XCHAL_CP6_SA_LIST(s) \
XCHAL_SA_REG(s,0,0,1,0, ldcbhi,16, 4, 4,0x0300, ur,0 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,1,0, ldcblo, 4, 4, 4,0x0301, ur,1 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,1,0, stcbhi, 4, 4, 4,0x0302, ur,2 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,1,0, stcblo, 4, 4, 4,0x0303, ur,3 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,1,0, ldbrbase, 4, 4, 4,0x0308, ur,8 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,1,0, ldbroff, 4, 4, 4,0x0309, ur,9 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,1,0, ldbrinc, 4, 4, 4,0x030A, ur,10 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,1,0, stbrbase, 4, 4, 4,0x030B, ur,11 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,1,0, stbroff, 4, 4, 4,0x030C, ur,12 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,1,0, stbrinc, 4, 4, 4,0x030D, ur,13 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,1,0, scratch0, 4, 4, 4,0x0318, ur,24 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,1,0, scratch1, 4, 4, 4,0x0319, ur,25 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,1,0, scratch2, 4, 4, 4,0x031A, ur,26 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,1,0, scratch3, 4, 4, 4,0x031B, ur,27 , 32,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, wra0,16,16,16,0x1010, wra,0 ,128,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, wra1,16,16,16,0x1011, wra,1 ,128,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, wra2,16,16,16,0x1012, wra,2 ,128,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, wra3,16,16,16,0x1013, wra,3 ,128,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, wra4,16,16,16,0x1014, wra,4 ,128,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, wra5,16,16,16,0x1015, wra,5 ,128,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, wra6,16,16,16,0x1016, wra,6 ,128,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, wra7,16,16,16,0x1017, wra,7 ,128,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, wra8,16,16,16,0x1018, wra,8 ,128,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, wra9,16,16,16,0x1019, wra,9 ,128,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, wra10,16,16,16,0x101A, wra,10 ,128,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, wra11,16,16,16,0x101B, wra,11 ,128,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, wra12,16,16,16,0x101C, wra,12 ,128,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, wra13,16,16,16,0x101D, wra,13 ,128,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, wra14,16,16,16,0x101E, wra,14 ,128,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, wra15,16,16,16,0x101F, wra,15 ,128,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, wrb0,16,16,16,0x1020, wrb,0 ,128,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, wrb1,16,16,16,0x1021, wrb,1 ,128,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, wrb2,16,16,16,0x1022, wrb,2 ,128,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, wrb3,16,16,16,0x1023, wrb,3 ,128,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, wrb4,16,16,16,0x1024, wrb,4 ,128,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, wrb5,16,16,16,0x1025, wrb,5 ,128,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, wrb6,16,16,16,0x1026, wrb,6 ,128,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, wrb7,16,16,16,0x1027, wrb,7 ,128,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, wrb8,16,16,16,0x1028, wrb,8 ,128,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, wrb9,16,16,16,0x1029, wrb,9 ,128,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, wrb10,16,16,16,0x102A, wrb,10 ,128,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, wrb11,16,16,16,0x102B, wrb,11 ,128,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, wrb12,16,16,16,0x102C, wrb,12 ,128,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, wrb13,16,16,16,0x102D, wrb,13 ,128,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, wrb14,16,16,16,0x102E, wrb,14 ,128,0,0,0) \
XCHAL_SA_REG(s,0,0,2,0, wrb15,16,16,16,0x102F, wrb,15 ,128,0,0,0)
#define XCHAL_CP7_SA_NUM 0
#define XCHAL_CP7_SA_LIST(s) /* empty */
/* Byte length of instruction from its first nibble (op0 field), per FLIX. */
#define XCHAL_OP0_FORMAT_LENGTHS 3,3,3,3,3,3,3,3,2,2,2,2,2,2,8,8
#endif /*_XTENSA_CORE_TIE_H*/
arch/xtensa/variants/s6000/irq.c deleted 100644 → 0
View file @ 3932b9ca
/*
* s6000 irq crossbar
*
* Copyright (c) 2009 emlix GmbH
* Authors: Johannes Weiner <hannes@cmpxchg.org>
* Oskar Schirmer <oskar@scara.com>
*/
#include <linux/io.h>
#include <asm/irq.h>
#include <variant/hardware.h>
/* S6_REG_INTC */
#define INTC_STATUS 0x000
#define INTC_RAW 0x010
#define INTC_STATUS_AG 0x100
#define INTC_CFG(n) (0x200 + 4 * (n))
/*
* The s6000 has a crossbar that multiplexes interrupt output lines
* from the peripherals to input lines on the xtensa core.
*
* We leave the mapping decisions to the platform as it depends on the
* actually connected peripherals which distribution makes sense.
*/
extern const signed char *platform_irq_mappings[NR_IRQS];
static unsigned long scp_to_intc_enable[] = {
#define TO_INTC_ENABLE(n) (((n) << 1) + 1)
TO_INTC_ENABLE(0),
TO_INTC_ENABLE(1),
TO_INTC_ENABLE(2),
TO_INTC_ENABLE(3),
TO_INTC_ENABLE(4),
TO_INTC_ENABLE(5),
TO_INTC_ENABLE(6),
TO_INTC_ENABLE(7),
TO_INTC_ENABLE(8),
TO_INTC_ENABLE(9),
TO_INTC_ENABLE(10),
TO_INTC_ENABLE(11),
TO_INTC_ENABLE(12),
-1,
-1,
TO_INTC_ENABLE(13),
-1,
TO_INTC_ENABLE(14),
-1,
TO_INTC_ENABLE(15),
#undef TO_INTC_ENABLE
};
static void irq_set(unsigned int irq, int enable)
{
unsigned long en;
const signed char *m = platform_irq_mappings[irq];
if (!m)
return;
en = enable ? scp_to_intc_enable[irq] : 0;
while (*m >= 0) {
writel(en, S6_REG_INTC + INTC_CFG(*m));
m++;
}
}
void variant_irq_enable(unsigned int irq)
{
irq_set(irq, 1);
}
void variant_irq_disable(unsigned int irq)
{
irq_set(irq, 0);
}
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