Commit 404d9e3f authored by Vipul Pandya's avatar Vipul Pandya Committed by David S. Miller

cxgb4: Address various sparse warnings

This patch fixes type assignment issues, function definition and symbol
shadowing which triggered sparse warnings.
Signed-off-by: default avatarJay Hernandez <jay@chelsio.com>
Signed-off-by: default avatarVipul Pandya <vipul@chelsio.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent ee9a8f7a
...@@ -696,6 +696,7 @@ int t4_seeprom_wp(struct adapter *adapter, bool enable); ...@@ -696,6 +696,7 @@ int t4_seeprom_wp(struct adapter *adapter, bool enable);
int get_vpd_params(struct adapter *adapter, struct vpd_params *p); int get_vpd_params(struct adapter *adapter, struct vpd_params *p);
int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size); int t4_load_fw(struct adapter *adapter, const u8 *fw_data, unsigned int size);
unsigned int t4_flash_cfg_addr(struct adapter *adapter); unsigned int t4_flash_cfg_addr(struct adapter *adapter);
int t4_load_cfg(struct adapter *adapter, const u8 *cfg_data, unsigned int size);
int t4_check_fw_version(struct adapter *adapter); int t4_check_fw_version(struct adapter *adapter);
int t4_prep_adapter(struct adapter *adapter); int t4_prep_adapter(struct adapter *adapter);
int t4_port_init(struct adapter *adap, int mbox, int pf, int vf); int t4_port_init(struct adapter *adap, int mbox, int pf, int vf);
......
...@@ -443,7 +443,10 @@ int dbfifo_int_thresh = 10; /* 10 == 640 entry threshold */ ...@@ -443,7 +443,10 @@ int dbfifo_int_thresh = 10; /* 10 == 640 entry threshold */
module_param(dbfifo_int_thresh, int, 0644); module_param(dbfifo_int_thresh, int, 0644);
MODULE_PARM_DESC(dbfifo_int_thresh, "doorbell fifo interrupt threshold"); MODULE_PARM_DESC(dbfifo_int_thresh, "doorbell fifo interrupt threshold");
int dbfifo_drain_delay = 1000; /* usecs to sleep while draining the dbfifo */ /*
* usecs to sleep while draining the dbfifo
*/
static int dbfifo_drain_delay = 1000;
module_param(dbfifo_drain_delay, int, 0644); module_param(dbfifo_drain_delay, int, 0644);
MODULE_PARM_DESC(dbfifo_drain_delay, MODULE_PARM_DESC(dbfifo_drain_delay,
"usecs to sleep while draining the dbfifo"); "usecs to sleep while draining the dbfifo");
...@@ -636,7 +639,7 @@ static void name_msix_vecs(struct adapter *adap) ...@@ -636,7 +639,7 @@ static void name_msix_vecs(struct adapter *adap)
static int request_msix_queue_irqs(struct adapter *adap) static int request_msix_queue_irqs(struct adapter *adap)
{ {
struct sge *s = &adap->sge; struct sge *s = &adap->sge;
int err, ethqidx, ofldqidx = 0, rdmaqidx = 0, msi = 2; int err, ethqidx, ofldqidx = 0, rdmaqidx = 0, msi_index = 2;
err = request_irq(adap->msix_info[1].vec, t4_sge_intr_msix, 0, err = request_irq(adap->msix_info[1].vec, t4_sge_intr_msix, 0,
adap->msix_info[1].desc, &s->fw_evtq); adap->msix_info[1].desc, &s->fw_evtq);
...@@ -644,56 +647,60 @@ static int request_msix_queue_irqs(struct adapter *adap) ...@@ -644,56 +647,60 @@ static int request_msix_queue_irqs(struct adapter *adap)
return err; return err;
for_each_ethrxq(s, ethqidx) { for_each_ethrxq(s, ethqidx) {
err = request_irq(adap->msix_info[msi].vec, t4_sge_intr_msix, 0, err = request_irq(adap->msix_info[msi_index].vec,
adap->msix_info[msi].desc, t4_sge_intr_msix, 0,
adap->msix_info[msi_index].desc,
&s->ethrxq[ethqidx].rspq); &s->ethrxq[ethqidx].rspq);
if (err) if (err)
goto unwind; goto unwind;
msi++; msi_index++;
} }
for_each_ofldrxq(s, ofldqidx) { for_each_ofldrxq(s, ofldqidx) {
err = request_irq(adap->msix_info[msi].vec, t4_sge_intr_msix, 0, err = request_irq(adap->msix_info[msi_index].vec,
adap->msix_info[msi].desc, t4_sge_intr_msix, 0,
adap->msix_info[msi_index].desc,
&s->ofldrxq[ofldqidx].rspq); &s->ofldrxq[ofldqidx].rspq);
if (err) if (err)
goto unwind; goto unwind;
msi++; msi_index++;
} }
for_each_rdmarxq(s, rdmaqidx) { for_each_rdmarxq(s, rdmaqidx) {
err = request_irq(adap->msix_info[msi].vec, t4_sge_intr_msix, 0, err = request_irq(adap->msix_info[msi_index].vec,
adap->msix_info[msi].desc, t4_sge_intr_msix, 0,
adap->msix_info[msi_index].desc,
&s->rdmarxq[rdmaqidx].rspq); &s->rdmarxq[rdmaqidx].rspq);
if (err) if (err)
goto unwind; goto unwind;
msi++; msi_index++;
} }
return 0; return 0;
unwind: unwind:
while (--rdmaqidx >= 0) while (--rdmaqidx >= 0)
free_irq(adap->msix_info[--msi].vec, free_irq(adap->msix_info[--msi_index].vec,
&s->rdmarxq[rdmaqidx].rspq); &s->rdmarxq[rdmaqidx].rspq);
while (--ofldqidx >= 0) while (--ofldqidx >= 0)
free_irq(adap->msix_info[--msi].vec, free_irq(adap->msix_info[--msi_index].vec,
&s->ofldrxq[ofldqidx].rspq); &s->ofldrxq[ofldqidx].rspq);
while (--ethqidx >= 0) while (--ethqidx >= 0)
free_irq(adap->msix_info[--msi].vec, &s->ethrxq[ethqidx].rspq); free_irq(adap->msix_info[--msi_index].vec,
&s->ethrxq[ethqidx].rspq);
free_irq(adap->msix_info[1].vec, &s->fw_evtq); free_irq(adap->msix_info[1].vec, &s->fw_evtq);
return err; return err;
} }
static void free_msix_queue_irqs(struct adapter *adap) static void free_msix_queue_irqs(struct adapter *adap)
{ {
int i, msi = 2; int i, msi_index = 2;
struct sge *s = &adap->sge; struct sge *s = &adap->sge;
free_irq(adap->msix_info[1].vec, &s->fw_evtq); free_irq(adap->msix_info[1].vec, &s->fw_evtq);
for_each_ethrxq(s, i) for_each_ethrxq(s, i)
free_irq(adap->msix_info[msi++].vec, &s->ethrxq[i].rspq); free_irq(adap->msix_info[msi_index++].vec, &s->ethrxq[i].rspq);
for_each_ofldrxq(s, i) for_each_ofldrxq(s, i)
free_irq(adap->msix_info[msi++].vec, &s->ofldrxq[i].rspq); free_irq(adap->msix_info[msi_index++].vec, &s->ofldrxq[i].rspq);
for_each_rdmarxq(s, i) for_each_rdmarxq(s, i)
free_irq(adap->msix_info[msi++].vec, &s->rdmarxq[i].rspq); free_irq(adap->msix_info[msi_index++].vec, &s->rdmarxq[i].rspq);
} }
/** /**
...@@ -2535,9 +2542,8 @@ static int read_eq_indices(struct adapter *adap, u16 qid, u16 *pidx, u16 *cidx) ...@@ -2535,9 +2542,8 @@ static int read_eq_indices(struct adapter *adap, u16 qid, u16 *pidx, u16 *cidx)
ret = t4_mem_win_read_len(adap, addr, (__be32 *)&indices, 8); ret = t4_mem_win_read_len(adap, addr, (__be32 *)&indices, 8);
if (!ret) { if (!ret) {
indices = be64_to_cpu(indices); *cidx = (be64_to_cpu(indices) >> 25) & 0xffff;
*cidx = (indices >> 25) & 0xffff; *pidx = (be64_to_cpu(indices) >> 9) & 0xffff;
*pidx = (indices >> 9) & 0xffff;
} }
return ret; return ret;
} }
...@@ -3634,10 +3640,10 @@ static int adap_init0_no_config(struct adapter *adapter, int reset) ...@@ -3634,10 +3640,10 @@ static int adap_init0_no_config(struct adapter *adapter, int reset)
* field selections will fit in the 36-bit budget. * field selections will fit in the 36-bit budget.
*/ */
if (tp_vlan_pri_map != TP_VLAN_PRI_MAP_DEFAULT) { if (tp_vlan_pri_map != TP_VLAN_PRI_MAP_DEFAULT) {
int i, bits = 0; int j, bits = 0;
for (i = TP_VLAN_PRI_MAP_FIRST; i <= TP_VLAN_PRI_MAP_LAST; i++) for (j = TP_VLAN_PRI_MAP_FIRST; j <= TP_VLAN_PRI_MAP_LAST; j++)
switch (tp_vlan_pri_map & (1 << i)) { switch (tp_vlan_pri_map & (1 << j)) {
case 0: case 0:
/* compressed filter field not enabled */ /* compressed filter field not enabled */
break; break;
......
...@@ -380,9 +380,11 @@ static int t4_mem_win_rw(struct adapter *adap, u32 addr, __be32 *data, int dir) ...@@ -380,9 +380,11 @@ static int t4_mem_win_rw(struct adapter *adap, u32 addr, __be32 *data, int dir)
/* Collecting data 4 bytes at a time upto MEMWIN0_APERTURE */ /* Collecting data 4 bytes at a time upto MEMWIN0_APERTURE */
for (i = 0; i < MEMWIN0_APERTURE; i = i+0x4) { for (i = 0; i < MEMWIN0_APERTURE; i = i+0x4) {
if (dir) if (dir)
*data++ = t4_read_reg(adap, (MEMWIN0_BASE + i)); *data++ = (__force __be32) t4_read_reg(adap,
(MEMWIN0_BASE + i));
else else
t4_write_reg(adap, (MEMWIN0_BASE + i), *data++); t4_write_reg(adap, (MEMWIN0_BASE + i),
(__force u32) *data++);
} }
return 0; return 0;
...@@ -744,7 +746,7 @@ static int t4_read_flash(struct adapter *adapter, unsigned int addr, ...@@ -744,7 +746,7 @@ static int t4_read_flash(struct adapter *adapter, unsigned int addr,
if (ret) if (ret)
return ret; return ret;
if (byte_oriented) if (byte_oriented)
*data = htonl(*data); *data = (__force __u32) (htonl(*data));
} }
return 0; return 0;
} }
...@@ -992,7 +994,7 @@ int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size) ...@@ -992,7 +994,7 @@ int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size)
int ret, addr; int ret, addr;
unsigned int i; unsigned int i;
u8 first_page[SF_PAGE_SIZE]; u8 first_page[SF_PAGE_SIZE];
const u32 *p = (const u32 *)fw_data; const __be32 *p = (const __be32 *)fw_data;
const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data; const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data;
unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec; unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
unsigned int fw_img_start = adap->params.sf_fw_start; unsigned int fw_img_start = adap->params.sf_fw_start;
...@@ -2315,7 +2317,8 @@ int t4_mem_win_read_len(struct adapter *adap, u32 addr, __be32 *data, int len) ...@@ -2315,7 +2317,8 @@ int t4_mem_win_read_len(struct adapter *adap, u32 addr, __be32 *data, int len)
t4_read_reg(adap, PCIE_MEM_ACCESS_OFFSET); t4_read_reg(adap, PCIE_MEM_ACCESS_OFFSET);
for (i = 0; i < len; i += 4) for (i = 0; i < len; i += 4)
*data++ = t4_read_reg(adap, (MEMWIN0_BASE + off + i)); *data++ = (__force __be32) t4_read_reg(adap,
(MEMWIN0_BASE + off + i));
return 0; return 0;
} }
......
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