Commit 40d3921f authored by Xiangliang Yu's avatar Xiangliang Yu Committed by James Bottomley

[SCSI] mvsas: fixed SMP request watchdog timeout issue.

set SMP link timeout value to maximum.
Signed-off-by: default avatarXiangliang Yu <yuxiangl@marvell.com>
Signed-off-by: default avatarJames Bottomley <JBottomley@Parallels.com>
parent 3a4b7efe
...@@ -510,6 +510,10 @@ static int __devinit mvs_94xx_init(struct mvs_info *mvi) ...@@ -510,6 +510,10 @@ static int __devinit mvs_94xx_init(struct mvs_info *mvi)
tmp |= CINT_PHY_MASK; tmp |= CINT_PHY_MASK;
mw32(MVS_INT_MASK, tmp); mw32(MVS_INT_MASK, tmp);
tmp = mvs_cr32(mvi, CMD_LINK_TIMER);
tmp |= 0xFFFF0000;
mvs_cw32(mvi, CMD_LINK_TIMER, tmp);
/* tune STP performance */ /* tune STP performance */
tmp = 0x003F003F; tmp = 0x003F003F;
mvs_cw32(mvi, CMD_PL_TIMER, tmp); mvs_cw32(mvi, CMD_PL_TIMER, tmp);
......
...@@ -388,6 +388,7 @@ enum sas_cmd_port_registers { ...@@ -388,6 +388,7 @@ enum sas_cmd_port_registers {
CMD_SL_MODE1 = 0x1C0, /* SL Mode 1 */ CMD_SL_MODE1 = 0x1C0, /* SL Mode 1 */
CMD_PND_FIFO_CTL1 = 0x1C4, /* Pending FIFO Control 1 */ CMD_PND_FIFO_CTL1 = 0x1C4, /* Pending FIFO Control 1 */
CMD_PORT_LAYER_TIMER1 = 0x1E0, /* Port Layer Timer 1 */ CMD_PORT_LAYER_TIMER1 = 0x1E0, /* Port Layer Timer 1 */
CMD_LINK_TIMER = 0x1E4, /* Link Timer */
}; };
enum mvs_info_flags { enum mvs_info_flags {
......
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