Commit 41bf5706 authored by Maxime Ripard's avatar Maxime Ripard Committed by Shawn Guo

ARM: dts: mxs: Add missing address and size cells in SSP nodes

Signed-off-by: default avatarMaxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: default avatarShawn Guo <shawn.guo@linaro.org>
parent fa876cef
...@@ -86,6 +86,8 @@ gpmi-nand@8000c000 { ...@@ -86,6 +86,8 @@ gpmi-nand@8000c000 {
}; };
ssp0: ssp@80010000 { ssp0: ssp@80010000 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x80010000 0x2000>; reg = <0x80010000 0x2000>;
interrupts = <96 82>; interrupts = <96 82>;
fsl,ssp-dma-channel = <0>; fsl,ssp-dma-channel = <0>;
...@@ -93,6 +95,8 @@ ssp0: ssp@80010000 { ...@@ -93,6 +95,8 @@ ssp0: ssp@80010000 {
}; };
ssp1: ssp@80012000 { ssp1: ssp@80012000 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x80012000 0x2000>; reg = <0x80012000 0x2000>;
interrupts = <97 83>; interrupts = <97 83>;
fsl,ssp-dma-channel = <1>; fsl,ssp-dma-channel = <1>;
...@@ -100,6 +104,8 @@ ssp1: ssp@80012000 { ...@@ -100,6 +104,8 @@ ssp1: ssp@80012000 {
}; };
ssp2: ssp@80014000 { ssp2: ssp@80014000 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x80014000 0x2000>; reg = <0x80014000 0x2000>;
interrupts = <98 84>; interrupts = <98 84>;
fsl,ssp-dma-channel = <2>; fsl,ssp-dma-channel = <2>;
...@@ -107,6 +113,8 @@ ssp2: ssp@80014000 { ...@@ -107,6 +113,8 @@ ssp2: ssp@80014000 {
}; };
ssp3: ssp@80016000 { ssp3: ssp@80016000 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x80016000 0x2000>; reg = <0x80016000 0x2000>;
interrupts = <99 85>; interrupts = <99 85>;
fsl,ssp-dma-channel = <3>; fsl,ssp-dma-channel = <3>;
......
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