Commit 41ef3dcd authored by Michael Strauss's avatar Michael Strauss Committed by Alex Deucher

drm/amd/display: Fix RV2 Variant Detection

[WHY]
RV2 and variants are indistinguishable by hw internal rev alone, need to
be distinguishable in order to correctly set max vlevel.  Previous
detection change incorrectly checked for hw internal rev.

[HOW]
Use pci revision to check if RV2 or low power variant Correct a few
overlapping ASICREV range checks
Signed-off-by: default avatarMichael Strauss <michael.strauss@amd.com>
Reviewed-by: default avatarMichael Strauss <Michael.Strauss@amd.com>
Acked-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: default avatarHarry Wentland <harry.wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 9dac88d8
...@@ -703,11 +703,19 @@ static void hack_bounding_box(struct dcn_bw_internal_vars *v, ...@@ -703,11 +703,19 @@ static void hack_bounding_box(struct dcn_bw_internal_vars *v,
} }
unsigned int get_highest_allowed_voltage_level(uint32_t hw_internal_rev) unsigned int get_highest_allowed_voltage_level(uint32_t hw_internal_rev, uint32_t pci_revision_id)
{ {
/* for dali & pollock, the highest voltage level we want is 0 */ /* for low power RV2 variants, the highest voltage level we want is 0 */
if (ASICREV_IS_POLLOCK(hw_internal_rev) || ASICREV_IS_DALI(hw_internal_rev)) if (ASICREV_IS_RAVEN2(hw_internal_rev))
return 0; switch (pci_revision_id) {
case PRID_DALI_DE:
case PRID_DALI_DF:
case PRID_DALI_E3:
case PRID_DALI_E4:
return 0;
default:
break;
}
/* we are ok with all levels */ /* we are ok with all levels */
return 4; return 4;
...@@ -1277,7 +1285,9 @@ bool dcn_validate_bandwidth( ...@@ -1277,7 +1285,9 @@ bool dcn_validate_bandwidth(
PERFORMANCE_TRACE_END(); PERFORMANCE_TRACE_END();
BW_VAL_TRACE_FINISH(); BW_VAL_TRACE_FINISH();
if (bw_limit_pass && v->voltage_level <= get_highest_allowed_voltage_level(dc->ctx->asic_id.hw_internal_rev)) if (bw_limit_pass && v->voltage_level <= get_highest_allowed_voltage_level(
dc->ctx->asic_id.hw_internal_rev,
dc->ctx->asic_id.pci_revision_id))
return true; return true;
else else
return false; return false;
......
...@@ -153,13 +153,6 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p ...@@ -153,13 +153,6 @@ struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *p
#if defined(CONFIG_DRM_AMD_DC_DCN) #if defined(CONFIG_DRM_AMD_DC_DCN)
case FAMILY_RV: case FAMILY_RV:
if (ASICREV_IS_DALI(asic_id.hw_internal_rev) ||
ASICREV_IS_POLLOCK(asic_id.hw_internal_rev)) {
/* TEMP: this check has to come before ASICREV_IS_RENOIR */
/* which also incorrectly returns true for Dali/Pollock*/
rv2_clk_mgr_construct(ctx, clk_mgr, pp_smu);
break;
}
if (ASICREV_IS_RENOIR(asic_id.hw_internal_rev)) { if (ASICREV_IS_RENOIR(asic_id.hw_internal_rev)) {
rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg);
break; break;
......
...@@ -136,8 +136,6 @@ ...@@ -136,8 +136,6 @@
#define RAVEN2_A0 0x81 #define RAVEN2_A0 0x81
#define RAVEN2_15D8_REV_94 0x94 #define RAVEN2_15D8_REV_94 0x94
#define RAVEN2_15D8_REV_95 0x95 #define RAVEN2_15D8_REV_95 0x95
#define RAVEN2_15D8_REV_E3 0xE3
#define RAVEN2_15D8_REV_E4 0xE4
#define RAVEN2_15D8_REV_E9 0xE9 #define RAVEN2_15D8_REV_E9 0xE9
#define RAVEN2_15D8_REV_EA 0xEA #define RAVEN2_15D8_REV_EA 0xEA
#define RAVEN2_15D8_REV_EB 0xEB #define RAVEN2_15D8_REV_EB 0xEB
...@@ -146,14 +144,16 @@ ...@@ -146,14 +144,16 @@
#ifndef ASICREV_IS_RAVEN #ifndef ASICREV_IS_RAVEN
#define ASICREV_IS_RAVEN(eChipRev) ((eChipRev >= RAVEN_A0) && eChipRev < RAVEN_UNKNOWN) #define ASICREV_IS_RAVEN(eChipRev) ((eChipRev >= RAVEN_A0) && eChipRev < RAVEN_UNKNOWN)
#endif #endif
#define PRID_DALI_DE 0xDE
#define PRID_DALI_DF 0xDF
#define PRID_DALI_E3 0xE3
#define PRID_DALI_E4 0xE4
#define ASICREV_IS_PICASSO(eChipRev) ((eChipRev >= PICASSO_A0) && (eChipRev < RAVEN2_A0)) #define ASICREV_IS_PICASSO(eChipRev) ((eChipRev >= PICASSO_A0) && (eChipRev < RAVEN2_A0))
#ifndef ASICREV_IS_RAVEN2 #ifndef ASICREV_IS_RAVEN2
#define ASICREV_IS_RAVEN2(eChipRev) ((eChipRev >= RAVEN2_A0) && (eChipRev < RAVEN1_F0)) #define ASICREV_IS_RAVEN2(eChipRev) ((eChipRev >= RAVEN2_A0) && (eChipRev < RENOIR_A0))
#endif #endif
#define ASICREV_IS_RV1_F0(eChipRev) ((eChipRev >= RAVEN1_F0) && (eChipRev < RAVEN_UNKNOWN)) #define ASICREV_IS_RV1_F0(eChipRev) ((eChipRev >= RAVEN1_F0) && (eChipRev < RAVEN_UNKNOWN))
#define ASICREV_IS_DALI(eChipRev) ((eChipRev == RAVEN2_15D8_REV_E3) \
|| (eChipRev == RAVEN2_15D8_REV_E4))
#define ASICREV_IS_POLLOCK(eChipRev) (eChipRev == RAVEN2_15D8_REV_94 \ #define ASICREV_IS_POLLOCK(eChipRev) (eChipRev == RAVEN2_15D8_REV_94 \
|| eChipRev == RAVEN2_15D8_REV_95 \ || eChipRev == RAVEN2_15D8_REV_95 \
|| eChipRev == RAVEN2_15D8_REV_E9 \ || eChipRev == RAVEN2_15D8_REV_E9 \
...@@ -177,7 +177,7 @@ enum { ...@@ -177,7 +177,7 @@ enum {
#define ASICREV_IS_NAVI14_M(eChipRev) ((eChipRev >= NV_NAVI14_M_A0) && (eChipRev < NV_UNKNOWN)) #define ASICREV_IS_NAVI14_M(eChipRev) ((eChipRev >= NV_NAVI14_M_A0) && (eChipRev < NV_UNKNOWN))
#define RENOIR_A0 0x91 #define RENOIR_A0 0x91
#define DEVICE_ID_RENOIR_1636 0x1636 // Renoir #define DEVICE_ID_RENOIR_1636 0x1636 // Renoir
#define ASICREV_IS_RENOIR(eChipRev) ((eChipRev >= RENOIR_A0) && (eChipRev < 0xFF)) #define ASICREV_IS_RENOIR(eChipRev) ((eChipRev >= RENOIR_A0) && (eChipRev < RAVEN1_F0))
/* /*
* ASIC chip ID * ASIC chip ID
......
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