Commit 42329854 authored by Dmitry Osipenko's avatar Dmitry Osipenko Committed by Thierry Reding

clk: tegra30: Use custom CCLK implementation

We're going to use the generic cpufreq-dt driver on Tegra30 and thus CCLK
intermediate re-parenting will be performed by the clock driver. There is
now special CCLK implementation that supports all CCLK quirks, this patch
makes Tegra30 SoCs to use that implementation.
Acked-by: default avatarPeter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: default avatarPeter Geis <pgwipeout@gmail.com>
Tested-by: default avatarMarcel Ziswiler <marcel@ziswiler.com>
Tested-by: default avatarJasper Korten <jja2000@gmail.com>
Tested-by: default avatarDavid Heidelberg <david@ixit.cz>
Tested-by: default avatarNicolas Chauvet <kwizart@gmail.com>
Signed-off-by: default avatarDmitry Osipenko <digetx@gmail.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 2db2fcd7
...@@ -499,6 +499,8 @@ static struct tegra_clk_pll_params pll_x_params __ro_after_init = { ...@@ -499,6 +499,8 @@ static struct tegra_clk_pll_params pll_x_params __ro_after_init = {
.freq_table = pll_x_freq_table, .freq_table = pll_x_freq_table,
.flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_DCCON | .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_DCCON |
TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE, TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
.pre_rate_change = tegra_cclk_pre_pllx_rate_change,
.post_rate_change = tegra_cclk_post_pllx_rate_change,
}; };
static struct tegra_clk_pll_params pll_e_params __ro_after_init = { static struct tegra_clk_pll_params pll_e_params __ro_after_init = {
...@@ -926,11 +928,11 @@ static void __init tegra30_super_clk_init(void) ...@@ -926,11 +928,11 @@ static void __init tegra30_super_clk_init(void)
clk_register_clkdev(clk, "pll_p_out4_cclkg", NULL); clk_register_clkdev(clk, "pll_p_out4_cclkg", NULL);
/* CCLKG */ /* CCLKG */
clk = tegra_clk_register_super_mux("cclk_g", cclk_g_parents, clk = tegra_clk_register_super_cclk("cclk_g", cclk_g_parents,
ARRAY_SIZE(cclk_g_parents), ARRAY_SIZE(cclk_g_parents),
CLK_SET_RATE_PARENT, CLK_SET_RATE_PARENT,
clk_base + CCLKG_BURST_POLICY, clk_base + CCLKG_BURST_POLICY,
0, 4, 0, 0, NULL); 0, NULL);
clks[TEGRA30_CLK_CCLK_G] = clk; clks[TEGRA30_CLK_CCLK_G] = clk;
/* /*
......
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