Commit 42a708c9 authored by Qipan Li's avatar Qipan Li Committed by Linus Walleij

pinctrl: sirf: fix the pin number and mux bit for usp0

we missed a pin and related mux bit for usp pin group, this
patch fixes it.
Signed-off-by: default avatarQipan Li <Qipan.Li@csr.com>
Signed-off-by: default avatarBarry Song <Baohua.Song@csr.com>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent c5f167d3
...@@ -496,7 +496,7 @@ static const unsigned sdmmc5_pins[] = { 24, 25, 26 }; ...@@ -496,7 +496,7 @@ static const unsigned sdmmc5_pins[] = { 24, 25, 26 };
static const struct sirfsoc_muxmask usp0_muxmask[] = { static const struct sirfsoc_muxmask usp0_muxmask[] = {
{ {
.group = 1, .group = 1,
.mask = BIT(19) | BIT(20) | BIT(21) | BIT(22), .mask = BIT(19) | BIT(20) | BIT(21) | BIT(22) | BIT(23),
}, },
}; };
...@@ -507,7 +507,7 @@ static const struct sirfsoc_padmux usp0_padmux = { ...@@ -507,7 +507,7 @@ static const struct sirfsoc_padmux usp0_padmux = {
.funcval = 0, .funcval = 0,
}; };
static const unsigned usp0_pins[] = { 51, 52, 53, 54 }; static const unsigned usp0_pins[] = { 51, 52, 53, 54, 55 };
static const struct sirfsoc_muxmask usp1_muxmask[] = { static const struct sirfsoc_muxmask usp1_muxmask[] = {
{ {
......
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