Commit 43b815c6 authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC fixes from Olof Johansson:
 "A few fixes this time around:

   - Fixup of some clock specifications for DRA7 (device-tree fix)

   - Removal of some dead/legacy CPU OPP/PM code for OMAP that throws
     warnings at boot

   - A few more minor fixups for OMAPs, most around display

   - Enable STM32 QSPI as =y since their rootfs sometimes comes from
     there

   - Switch CONFIG_REMOTEPROC to =y since it went from tristate to bool

   - Fix of thermal zone definition for ux500 (5.4 regression)"

* tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc:
  ARM: multi_v7_defconfig: Fix SPI_STM32_QSPI support
  ARM: dts: ux500: Fix up the CPU thermal zone
  arm64/ARM: configs: Change CONFIG_REMOTEPROC from m to y
  ARM: dts: am4372: Set memory bandwidth limit for DISPC
  ARM: OMAP2+: Fix warnings with broken omap2_set_init_voltage()
  ARM: OMAP2+: Add missing LCDC midlemode for am335x
  ARM: OMAP2+: Fix missing reset done flag for am3 and am43
  ARM: dts: Fix gpio0 flags for am335x-icev2
  ARM: omap2plus_defconfig: Enable more droid4 devices as loadable modules
  ARM: omap2plus_defconfig: Enable DRM_TI_TFP410
  DTS: ARM: gta04: introduce legacy spi-cs-high to make display work again
  ARM: dts: Fix wrong clocks for dra7 mcasp
  clk: ti: dra7: Fix mcasp8 clock bits
parents 2d00aee2 60c1b3e2
...@@ -432,7 +432,7 @@ &mmc1 { ...@@ -432,7 +432,7 @@ &mmc1 {
pinctrl-0 = <&mmc0_pins_default>; pinctrl-0 = <&mmc0_pins_default>;
}; };
&gpio0 { &gpio0_target {
/* Do not idle the GPIO used for holding the VTT regulator */ /* Do not idle the GPIO used for holding the VTT regulator */
ti,no-reset-on-init; ti,no-reset-on-init;
ti,no-idle-on-init; ti,no-idle-on-init;
......
...@@ -127,7 +127,7 @@ target-module@5000 { /* 0x44e05000, ap 12 30.0 */ ...@@ -127,7 +127,7 @@ target-module@5000 { /* 0x44e05000, ap 12 30.0 */
ranges = <0x0 0x5000 0x1000>; ranges = <0x0 0x5000 0x1000>;
}; };
target-module@7000 { /* 0x44e07000, ap 14 20.0 */ gpio0_target: target-module@7000 { /* 0x44e07000, ap 14 20.0 */
compatible = "ti,sysc-omap2", "ti,sysc"; compatible = "ti,sysc-omap2", "ti,sysc";
ti,hwmods = "gpio1"; ti,hwmods = "gpio1";
reg = <0x7000 0x4>, reg = <0x7000 0x4>,
...@@ -2038,7 +2038,9 @@ target-module@e000 { /* 0x4830e000, ap 72 4a.0 */ ...@@ -2038,7 +2038,9 @@ target-module@e000 { /* 0x4830e000, ap 72 4a.0 */
reg = <0xe000 0x4>, reg = <0xe000 0x4>,
<0xe054 0x4>; <0xe054 0x4>;
reg-names = "rev", "sysc"; reg-names = "rev", "sysc";
ti,sysc-midle ; ti,sysc-midle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>, ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>, <SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>; <SYSC_IDLE_SMART>;
......
...@@ -337,6 +337,8 @@ dispc: dispc@4832a400 { ...@@ -337,6 +337,8 @@ dispc: dispc@4832a400 {
ti,hwmods = "dss_dispc"; ti,hwmods = "dss_dispc";
clocks = <&disp_clk>; clocks = <&disp_clk>;
clock-names = "fck"; clock-names = "fck";
max-memory-bandwidth = <230000000>;
}; };
rfbi: rfbi@4832a800 { rfbi: rfbi@4832a800 {
......
...@@ -2732,7 +2732,7 @@ mcasp1: mcasp@0 { ...@@ -2732,7 +2732,7 @@ mcasp1: mcasp@0 {
interrupt-names = "tx", "rx"; interrupt-names = "tx", "rx";
dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>; dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 22>, clocks = <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 0>,
<&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>, <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>,
<&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 28>; <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 28>;
clock-names = "fck", "ahclkx", "ahclkr"; clock-names = "fck", "ahclkx", "ahclkr";
...@@ -2768,8 +2768,8 @@ mcasp2: mcasp@0 { ...@@ -2768,8 +2768,8 @@ mcasp2: mcasp@0 {
interrupt-names = "tx", "rx"; interrupt-names = "tx", "rx";
dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>; dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 22>, clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 0>,
<&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 24>, <&ipu_clkctrl DRA7_IPU_MCASP1_CLKCTRL 24>,
<&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 28>; <&l4per2_clkctrl DRA7_L4PER2_MCASP2_CLKCTRL 28>;
clock-names = "fck", "ahclkx", "ahclkr"; clock-names = "fck", "ahclkx", "ahclkr";
status = "disabled"; status = "disabled";
...@@ -2786,9 +2786,8 @@ target-module@68000 { /* 0x48468000, ap 13 26.0 */ ...@@ -2786,9 +2786,8 @@ target-module@68000 { /* 0x48468000, ap 13 26.0 */
<SYSC_IDLE_SMART>; <SYSC_IDLE_SMART>;
/* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>, clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>,
<&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>, <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>;
<&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 28>; clock-names = "fck", "ahclkx";
clock-names = "fck", "ahclkx", "ahclkr";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
ranges = <0x0 0x68000 0x2000>, ranges = <0x0 0x68000 0x2000>,
...@@ -2804,7 +2803,7 @@ mcasp3: mcasp@0 { ...@@ -2804,7 +2803,7 @@ mcasp3: mcasp@0 {
interrupt-names = "tx", "rx"; interrupt-names = "tx", "rx";
dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>; dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 22>, clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 0>,
<&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>; <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>;
clock-names = "fck", "ahclkx"; clock-names = "fck", "ahclkx";
status = "disabled"; status = "disabled";
...@@ -2821,9 +2820,8 @@ target-module@6c000 { /* 0x4846c000, ap 15 2e.0 */ ...@@ -2821,9 +2820,8 @@ target-module@6c000 { /* 0x4846c000, ap 15 2e.0 */
<SYSC_IDLE_SMART>; <SYSC_IDLE_SMART>;
/* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>, clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>,
<&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>, <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>;
<&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 28>; clock-names = "fck", "ahclkx";
clock-names = "fck", "ahclkx", "ahclkr";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
ranges = <0x0 0x6c000 0x2000>, ranges = <0x0 0x6c000 0x2000>,
...@@ -2839,7 +2837,7 @@ mcasp4: mcasp@0 { ...@@ -2839,7 +2837,7 @@ mcasp4: mcasp@0 {
interrupt-names = "tx", "rx"; interrupt-names = "tx", "rx";
dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>; dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 22>, clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 0>,
<&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>; <&l4per2_clkctrl DRA7_L4PER2_MCASP4_CLKCTRL 24>;
clock-names = "fck", "ahclkx"; clock-names = "fck", "ahclkx";
status = "disabled"; status = "disabled";
...@@ -2856,9 +2854,8 @@ target-module@70000 { /* 0x48470000, ap 19 36.0 */ ...@@ -2856,9 +2854,8 @@ target-module@70000 { /* 0x48470000, ap 19 36.0 */
<SYSC_IDLE_SMART>; <SYSC_IDLE_SMART>;
/* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>, clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>,
<&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>, <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>;
<&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 28>; clock-names = "fck", "ahclkx";
clock-names = "fck", "ahclkx", "ahclkr";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
ranges = <0x0 0x70000 0x2000>, ranges = <0x0 0x70000 0x2000>,
...@@ -2874,7 +2871,7 @@ mcasp5: mcasp@0 { ...@@ -2874,7 +2871,7 @@ mcasp5: mcasp@0 {
interrupt-names = "tx", "rx"; interrupt-names = "tx", "rx";
dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>; dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 22>, clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 0>,
<&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>; <&l4per2_clkctrl DRA7_L4PER2_MCASP5_CLKCTRL 24>;
clock-names = "fck", "ahclkx"; clock-names = "fck", "ahclkx";
status = "disabled"; status = "disabled";
...@@ -2891,9 +2888,8 @@ target-module@74000 { /* 0x48474000, ap 35 14.0 */ ...@@ -2891,9 +2888,8 @@ target-module@74000 { /* 0x48474000, ap 35 14.0 */
<SYSC_IDLE_SMART>; <SYSC_IDLE_SMART>;
/* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>, clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>,
<&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>, <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>;
<&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 28>; clock-names = "fck", "ahclkx";
clock-names = "fck", "ahclkx", "ahclkr";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
ranges = <0x0 0x74000 0x2000>, ranges = <0x0 0x74000 0x2000>,
...@@ -2909,7 +2905,7 @@ mcasp6: mcasp@0 { ...@@ -2909,7 +2905,7 @@ mcasp6: mcasp@0 {
interrupt-names = "tx", "rx"; interrupt-names = "tx", "rx";
dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>; dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 22>, clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 0>,
<&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>; <&l4per2_clkctrl DRA7_L4PER2_MCASP6_CLKCTRL 24>;
clock-names = "fck", "ahclkx"; clock-names = "fck", "ahclkx";
status = "disabled"; status = "disabled";
...@@ -2926,9 +2922,8 @@ target-module@78000 { /* 0x48478000, ap 39 0c.0 */ ...@@ -2926,9 +2922,8 @@ target-module@78000 { /* 0x48478000, ap 39 0c.0 */
<SYSC_IDLE_SMART>; <SYSC_IDLE_SMART>;
/* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>, clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>,
<&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>, <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>;
<&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 28>; clock-names = "fck", "ahclkx";
clock-names = "fck", "ahclkx", "ahclkr";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
ranges = <0x0 0x78000 0x2000>, ranges = <0x0 0x78000 0x2000>,
...@@ -2944,7 +2939,7 @@ mcasp7: mcasp@0 { ...@@ -2944,7 +2939,7 @@ mcasp7: mcasp@0 {
interrupt-names = "tx", "rx"; interrupt-names = "tx", "rx";
dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>; dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 22>, clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 0>,
<&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>; <&l4per2_clkctrl DRA7_L4PER2_MCASP7_CLKCTRL 24>;
clock-names = "fck", "ahclkx"; clock-names = "fck", "ahclkx";
status = "disabled"; status = "disabled";
...@@ -2961,9 +2956,8 @@ target-module@7c000 { /* 0x4847c000, ap 43 04.0 */ ...@@ -2961,9 +2956,8 @@ target-module@7c000 { /* 0x4847c000, ap 43 04.0 */
<SYSC_IDLE_SMART>; <SYSC_IDLE_SMART>;
/* Domains (P, C): l4per_pwrdm, l4per2_clkdm */ /* Domains (P, C): l4per_pwrdm, l4per2_clkdm */
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>, clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>,
<&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>, <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>;
<&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 28>; clock-names = "fck", "ahclkx";
clock-names = "fck", "ahclkx", "ahclkr";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
ranges = <0x0 0x7c000 0x2000>, ranges = <0x0 0x7c000 0x2000>,
...@@ -2979,7 +2973,7 @@ mcasp8: mcasp@0 { ...@@ -2979,7 +2973,7 @@ mcasp8: mcasp@0 {
interrupt-names = "tx", "rx"; interrupt-names = "tx", "rx";
dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>; dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 22>, clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 0>,
<&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>; <&l4per2_clkctrl DRA7_L4PER2_MCASP8_CLKCTRL 24>;
clock-names = "fck", "ahclkx"; clock-names = "fck", "ahclkx";
status = "disabled"; status = "disabled";
......
...@@ -124,6 +124,7 @@ lcd: td028ttec1@0 { ...@@ -124,6 +124,7 @@ lcd: td028ttec1@0 {
spi-max-frequency = <100000>; spi-max-frequency = <100000>;
spi-cpol; spi-cpol;
spi-cpha; spi-cpha;
spi-cs-high;
backlight= <&backlight>; backlight= <&backlight>;
label = "lcd"; label = "lcd";
......
...@@ -8,6 +8,7 @@ ...@@ -8,6 +8,7 @@
#include <dt-bindings/mfd/dbx500-prcmu.h> #include <dt-bindings/mfd/dbx500-prcmu.h>
#include <dt-bindings/arm/ux500_pm_domains.h> #include <dt-bindings/arm/ux500_pm_domains.h>
#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/thermal/thermal.h>
/ { / {
#address-cells = <1>; #address-cells = <1>;
...@@ -59,8 +60,12 @@ thermal-zones { ...@@ -59,8 +60,12 @@ thermal-zones {
* cooling. * cooling.
*/ */
cpu_thermal: cpu-thermal { cpu_thermal: cpu-thermal {
polling-delay-passive = <0>; polling-delay-passive = <250>;
polling-delay = <1000>; /*
* This sensor fires interrupts to update the thermal
* zone, so no polling is needed.
*/
polling-delay = <0>;
thermal-sensors = <&thermal>; thermal-sensors = <&thermal>;
...@@ -79,7 +84,7 @@ cpu-crit { ...@@ -79,7 +84,7 @@ cpu-crit {
cooling-maps { cooling-maps {
trip = <&cpu_alert>; trip = <&cpu_alert>;
cooling-device = <&CPU0 0 2>; cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
contribution = <100>; contribution = <100>;
}; };
}; };
......
...@@ -228,7 +228,7 @@ CONFIG_RTC_DRV_OMAP=m ...@@ -228,7 +228,7 @@ CONFIG_RTC_DRV_OMAP=m
CONFIG_DMADEVICES=y CONFIG_DMADEVICES=y
CONFIG_TI_EDMA=y CONFIG_TI_EDMA=y
CONFIG_COMMON_CLK_PWM=m CONFIG_COMMON_CLK_PWM=m
CONFIG_REMOTEPROC=m CONFIG_REMOTEPROC=y
CONFIG_DA8XX_REMOTEPROC=m CONFIG_DA8XX_REMOTEPROC=m
CONFIG_MEMORY=y CONFIG_MEMORY=y
CONFIG_TI_AEMIF=m CONFIG_TI_AEMIF=m
......
...@@ -415,7 +415,7 @@ CONFIG_SPI_SH_MSIOF=m ...@@ -415,7 +415,7 @@ CONFIG_SPI_SH_MSIOF=m
CONFIG_SPI_SH_HSPI=y CONFIG_SPI_SH_HSPI=y
CONFIG_SPI_SIRF=y CONFIG_SPI_SIRF=y
CONFIG_SPI_STM32=m CONFIG_SPI_STM32=m
CONFIG_SPI_STM32_QSPI=m CONFIG_SPI_STM32_QSPI=y
CONFIG_SPI_SUN4I=y CONFIG_SPI_SUN4I=y
CONFIG_SPI_SUN6I=y CONFIG_SPI_SUN6I=y
CONFIG_SPI_TEGRA114=y CONFIG_SPI_TEGRA114=y
...@@ -933,7 +933,7 @@ CONFIG_BCM2835_MBOX=y ...@@ -933,7 +933,7 @@ CONFIG_BCM2835_MBOX=y
CONFIG_ROCKCHIP_IOMMU=y CONFIG_ROCKCHIP_IOMMU=y
CONFIG_TEGRA_IOMMU_GART=y CONFIG_TEGRA_IOMMU_GART=y
CONFIG_TEGRA_IOMMU_SMMU=y CONFIG_TEGRA_IOMMU_SMMU=y
CONFIG_REMOTEPROC=m CONFIG_REMOTEPROC=y
CONFIG_ST_REMOTEPROC=m CONFIG_ST_REMOTEPROC=m
CONFIG_RPMSG_VIRTIO=m CONFIG_RPMSG_VIRTIO=m
CONFIG_ASPEED_LPC_CTRL=m CONFIG_ASPEED_LPC_CTRL=m
......
...@@ -364,6 +364,7 @@ CONFIG_DRM_OMAP_PANEL_TPO_TD043MTEA1=m ...@@ -364,6 +364,7 @@ CONFIG_DRM_OMAP_PANEL_TPO_TD043MTEA1=m
CONFIG_DRM_OMAP_PANEL_NEC_NL8048HL11=m CONFIG_DRM_OMAP_PANEL_NEC_NL8048HL11=m
CONFIG_DRM_TILCDC=m CONFIG_DRM_TILCDC=m
CONFIG_DRM_PANEL_SIMPLE=m CONFIG_DRM_PANEL_SIMPLE=m
CONFIG_DRM_TI_TFP410=m
CONFIG_FB=y CONFIG_FB=y
CONFIG_FIRMWARE_EDID=y CONFIG_FIRMWARE_EDID=y
CONFIG_FB_MODE_HELPERS=y CONFIG_FB_MODE_HELPERS=y
...@@ -423,6 +424,7 @@ CONFIG_USB_SERIAL_GENERIC=y ...@@ -423,6 +424,7 @@ CONFIG_USB_SERIAL_GENERIC=y
CONFIG_USB_SERIAL_SIMPLE=m CONFIG_USB_SERIAL_SIMPLE=m
CONFIG_USB_SERIAL_FTDI_SIO=m CONFIG_USB_SERIAL_FTDI_SIO=m
CONFIG_USB_SERIAL_PL2303=m CONFIG_USB_SERIAL_PL2303=m
CONFIG_USB_SERIAL_OPTION=m
CONFIG_USB_TEST=m CONFIG_USB_TEST=m
CONFIG_NOP_USB_XCEIV=m CONFIG_NOP_USB_XCEIV=m
CONFIG_AM335X_PHY_USB=m CONFIG_AM335X_PHY_USB=m
...@@ -460,6 +462,7 @@ CONFIG_MMC_SDHCI_OMAP=y ...@@ -460,6 +462,7 @@ CONFIG_MMC_SDHCI_OMAP=y
CONFIG_NEW_LEDS=y CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=m CONFIG_LEDS_CLASS=m
CONFIG_LEDS_CPCAP=m CONFIG_LEDS_CPCAP=m
CONFIG_LEDS_LM3532=m
CONFIG_LEDS_GPIO=m CONFIG_LEDS_GPIO=m
CONFIG_LEDS_PCA963X=m CONFIG_LEDS_PCA963X=m
CONFIG_LEDS_PWM=m CONFIG_LEDS_PWM=m
...@@ -481,7 +484,7 @@ CONFIG_RTC_DRV_OMAP=m ...@@ -481,7 +484,7 @@ CONFIG_RTC_DRV_OMAP=m
CONFIG_RTC_DRV_CPCAP=m CONFIG_RTC_DRV_CPCAP=m
CONFIG_DMADEVICES=y CONFIG_DMADEVICES=y
CONFIG_OMAP_IOMMU=y CONFIG_OMAP_IOMMU=y
CONFIG_REMOTEPROC=m CONFIG_REMOTEPROC=y
CONFIG_OMAP_REMOTEPROC=m CONFIG_OMAP_REMOTEPROC=m
CONFIG_WKUP_M3_RPROC=m CONFIG_WKUP_M3_RPROC=m
CONFIG_SOC_TI=y CONFIG_SOC_TI=y
......
...@@ -763,7 +763,8 @@ static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = { ...@@ -763,7 +763,8 @@ static struct omap_hwmod_class_sysconfig am33xx_timer_sysc = {
.rev_offs = 0x0000, .rev_offs = 0x0000,
.sysc_offs = 0x0010, .sysc_offs = 0x0010,
.syss_offs = 0x0014, .syss_offs = 0x0014,
.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
SYSC_HAS_RESET_STATUS,
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
SIDLE_SMART_WKUP), SIDLE_SMART_WKUP),
.sysc_fields = &omap_hwmod_sysc_type2, .sysc_fields = &omap_hwmod_sysc_type2,
......
...@@ -231,8 +231,9 @@ static struct omap_hwmod am33xx_control_hwmod = { ...@@ -231,8 +231,9 @@ static struct omap_hwmod am33xx_control_hwmod = {
static struct omap_hwmod_class_sysconfig lcdc_sysc = { static struct omap_hwmod_class_sysconfig lcdc_sysc = {
.rev_offs = 0x0, .rev_offs = 0x0,
.sysc_offs = 0x54, .sysc_offs = 0x54,
.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE), .sysc_flags = SYSC_HAS_SIDLEMODE | SYSC_HAS_MIDLEMODE,
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), .idlemodes = SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART,
.sysc_fields = &omap_hwmod_sysc_type2, .sysc_fields = &omap_hwmod_sysc_type2,
}; };
......
...@@ -74,83 +74,6 @@ int omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused) ...@@ -74,83 +74,6 @@ int omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused)
return 0; return 0;
} }
/*
* This API is to be called during init to set the various voltage
* domains to the voltage as per the opp table. Typically we boot up
* at the nominal voltage. So this function finds out the rate of
* the clock associated with the voltage domain, finds out the correct
* opp entry and sets the voltage domain to the voltage specified
* in the opp entry
*/
static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name,
const char *oh_name)
{
struct voltagedomain *voltdm;
struct clk *clk;
struct dev_pm_opp *opp;
unsigned long freq, bootup_volt;
struct device *dev;
if (!vdd_name || !clk_name || !oh_name) {
pr_err("%s: invalid parameters\n", __func__);
goto exit;
}
if (!strncmp(oh_name, "mpu", 3))
/*
* All current OMAPs share voltage rail and clock
* source, so CPU0 is used to represent the MPU-SS.
*/
dev = get_cpu_device(0);
else
dev = omap_device_get_by_hwmod_name(oh_name);
if (IS_ERR(dev)) {
pr_err("%s: Unable to get dev pointer for hwmod %s\n",
__func__, oh_name);
goto exit;
}
voltdm = voltdm_lookup(vdd_name);
if (!voltdm) {
pr_err("%s: unable to get vdd pointer for vdd_%s\n",
__func__, vdd_name);
goto exit;
}
clk = clk_get(NULL, clk_name);
if (IS_ERR(clk)) {
pr_err("%s: unable to get clk %s\n", __func__, clk_name);
goto exit;
}
freq = clk_get_rate(clk);
clk_put(clk);
opp = dev_pm_opp_find_freq_ceil(dev, &freq);
if (IS_ERR(opp)) {
pr_err("%s: unable to find boot up OPP for vdd_%s\n",
__func__, vdd_name);
goto exit;
}
bootup_volt = dev_pm_opp_get_voltage(opp);
dev_pm_opp_put(opp);
if (!bootup_volt) {
pr_err("%s: unable to find voltage corresponding to the bootup OPP for vdd_%s\n",
__func__, vdd_name);
goto exit;
}
voltdm_scale(voltdm, bootup_volt);
return 0;
exit:
pr_err("%s: unable to set vdd_%s\n", __func__, vdd_name);
return -EINVAL;
}
#ifdef CONFIG_SUSPEND #ifdef CONFIG_SUSPEND
static int omap_pm_enter(suspend_state_t suspend_state) static int omap_pm_enter(suspend_state_t suspend_state)
{ {
...@@ -208,25 +131,6 @@ void omap_common_suspend_init(void *pm_suspend) ...@@ -208,25 +131,6 @@ void omap_common_suspend_init(void *pm_suspend)
} }
#endif /* CONFIG_SUSPEND */ #endif /* CONFIG_SUSPEND */
static void __init omap3_init_voltages(void)
{
if (!soc_is_omap34xx())
return;
omap2_set_init_voltage("mpu_iva", "dpll1_ck", "mpu");
omap2_set_init_voltage("core", "l3_ick", "l3_main");
}
static void __init omap4_init_voltages(void)
{
if (!soc_is_omap44xx())
return;
omap2_set_init_voltage("mpu", "dpll_mpu_ck", "mpu");
omap2_set_init_voltage("core", "l3_div_ck", "l3_main_1");
omap2_set_init_voltage("iva", "dpll_iva_m5x2_ck", "iva");
}
int __maybe_unused omap_pm_nop_init(void) int __maybe_unused omap_pm_nop_init(void)
{ {
return 0; return 0;
...@@ -246,10 +150,6 @@ int __init omap2_common_pm_late_init(void) ...@@ -246,10 +150,6 @@ int __init omap2_common_pm_late_init(void)
omap4_twl_init(); omap4_twl_init();
omap_voltage_late_init(); omap_voltage_late_init();
/* Initialize the voltages */
omap3_init_voltages();
omap4_init_voltages();
/* Smartreflex device init */ /* Smartreflex device init */
omap_devinit_smartreflex(); omap_devinit_smartreflex();
......
...@@ -723,7 +723,7 @@ CONFIG_TEGRA_IOMMU_SMMU=y ...@@ -723,7 +723,7 @@ CONFIG_TEGRA_IOMMU_SMMU=y
CONFIG_ARM_SMMU=y CONFIG_ARM_SMMU=y
CONFIG_ARM_SMMU_V3=y CONFIG_ARM_SMMU_V3=y
CONFIG_QCOM_IOMMU=y CONFIG_QCOM_IOMMU=y
CONFIG_REMOTEPROC=m CONFIG_REMOTEPROC=y
CONFIG_QCOM_Q6V5_MSS=m CONFIG_QCOM_Q6V5_MSS=m
CONFIG_QCOM_Q6V5_PAS=m CONFIG_QCOM_Q6V5_PAS=m
CONFIG_QCOM_SYSMON=m CONFIG_QCOM_SYSMON=m
......
...@@ -683,7 +683,7 @@ static const struct omap_clkctrl_reg_data dra7_l4per2_clkctrl_regs[] __initconst ...@@ -683,7 +683,7 @@ static const struct omap_clkctrl_reg_data dra7_l4per2_clkctrl_regs[] __initconst
{ DRA7_L4PER2_MCASP2_CLKCTRL, dra7_mcasp2_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:0154:22" }, { DRA7_L4PER2_MCASP2_CLKCTRL, dra7_mcasp2_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:0154:22" },
{ DRA7_L4PER2_MCASP3_CLKCTRL, dra7_mcasp3_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:015c:22" }, { DRA7_L4PER2_MCASP3_CLKCTRL, dra7_mcasp3_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:015c:22" },
{ DRA7_L4PER2_MCASP5_CLKCTRL, dra7_mcasp5_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:016c:22" }, { DRA7_L4PER2_MCASP5_CLKCTRL, dra7_mcasp5_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:016c:22" },
{ DRA7_L4PER2_MCASP8_CLKCTRL, dra7_mcasp8_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:0184:24" }, { DRA7_L4PER2_MCASP8_CLKCTRL, dra7_mcasp8_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:0184:22" },
{ DRA7_L4PER2_MCASP4_CLKCTRL, dra7_mcasp4_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:018c:22" }, { DRA7_L4PER2_MCASP4_CLKCTRL, dra7_mcasp4_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:018c:22" },
{ DRA7_L4PER2_UART7_CLKCTRL, dra7_uart7_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01c4:24" }, { DRA7_L4PER2_UART7_CLKCTRL, dra7_uart7_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01c4:24" },
{ DRA7_L4PER2_UART8_CLKCTRL, dra7_uart8_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01d4:24" }, { DRA7_L4PER2_UART8_CLKCTRL, dra7_uart8_bit_data, CLKF_SW_SUP, "l4per2-clkctrl:01d4:24" },
...@@ -828,8 +828,8 @@ static struct ti_dt_clk dra7xx_clks[] = { ...@@ -828,8 +828,8 @@ static struct ti_dt_clk dra7xx_clks[] = {
DT_CLK(NULL, "mcasp6_aux_gfclk_mux", "l4per2-clkctrl:01f8:22"), DT_CLK(NULL, "mcasp6_aux_gfclk_mux", "l4per2-clkctrl:01f8:22"),
DT_CLK(NULL, "mcasp7_ahclkx_mux", "l4per2-clkctrl:01fc:24"), DT_CLK(NULL, "mcasp7_ahclkx_mux", "l4per2-clkctrl:01fc:24"),
DT_CLK(NULL, "mcasp7_aux_gfclk_mux", "l4per2-clkctrl:01fc:22"), DT_CLK(NULL, "mcasp7_aux_gfclk_mux", "l4per2-clkctrl:01fc:22"),
DT_CLK(NULL, "mcasp8_ahclkx_mux", "l4per2-clkctrl:0184:22"), DT_CLK(NULL, "mcasp8_ahclkx_mux", "l4per2-clkctrl:0184:24"),
DT_CLK(NULL, "mcasp8_aux_gfclk_mux", "l4per2-clkctrl:0184:24"), DT_CLK(NULL, "mcasp8_aux_gfclk_mux", "l4per2-clkctrl:0184:22"),
DT_CLK(NULL, "mmc1_clk32k", "l3init-clkctrl:0008:8"), DT_CLK(NULL, "mmc1_clk32k", "l3init-clkctrl:0008:8"),
DT_CLK(NULL, "mmc1_fclk_div", "l3init-clkctrl:0008:25"), DT_CLK(NULL, "mmc1_fclk_div", "l3init-clkctrl:0008:25"),
DT_CLK(NULL, "mmc1_fclk_mux", "l3init-clkctrl:0008:24"), DT_CLK(NULL, "mmc1_fclk_mux", "l3init-clkctrl:0008:24"),
......
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