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Commit 448d64f8 authored by Paul Mackerras's avatar Paul Mackerras Committed by Ingo Molnar
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perf_counter: powerpc: Use unsigned long for register and constraint values 

This changes the powerpc perf_counter back-end to use unsigned long
types for hardware register values and for the value/mask pairs used
in checking whether a given set of events fit within the hardware
constraints.  This is in preparation for adding support for the PMU
on some 32-bit powerpc processors.  On 32-bit processors the hardware
registers are only 32 bits wide, and the PMU structure is generally
simpler, so 32 bits should be ample for expressing the hardware
constraints.  On 64-bit processors, unsigned long is 64 bits wide,
so using unsigned long vs. u64 (unsigned long long) makes no actual
difference.

This makes some other very minor changes: adjusting whitespace to line
things up in initialized structures, and simplifying some code in
hw_perf_disable().
Signed-off-by: default avatarPaul Mackerras <paulus@samba.org>
Cc: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: linuxppc-dev@ozlabs.org
Cc: benh@kernel.crashing.org
LKML-Reference: <19000.55473.26174.331511@cargo.ozlabs.ibm.com>
Signed-off-by: default avatarIngo Molnar <mingo@elte.hu>
parent 105988c0
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Showing with 229 additions and 212 deletions
arch/powerpc/include/asm/perf_counter.h
View file @ 448d64f8
...@@ -21,21 +21,22 @@ ...@@ -21,21 +21,22 @@
* describe the PMU on a particular POWER-family CPU. * describe the PMU on a particular POWER-family CPU.
*/ */
struct power_pmu { struct power_pmu {
int n_counter; int n_counter;
int max_alternatives; int max_alternatives;
u64 add_fields; unsigned long add_fields;
u64 test_adder; unsigned long test_adder;
int (*compute_mmcr)(u64 events[], int n_ev, int (*compute_mmcr)(u64 events[], int n_ev,
unsigned int hwc[], u64 mmcr[]); unsigned int hwc[], unsigned long mmcr[]);
int (*get_constraint)(u64 event, u64 *mskp, u64 *valp); int (*get_constraint)(u64 event, unsigned long *mskp,
int (*get_alternatives)(u64 event, unsigned int flags, unsigned long *valp);
u64 alt[]); int (*get_alternatives)(u64 event, unsigned int flags,
void (*disable_pmc)(unsigned int pmc, u64 mmcr[]); u64 alt[]);
int (*limited_pmc_event)(u64 event); void (*disable_pmc)(unsigned int pmc, unsigned long mmcr[]);
u32 flags; int (*limited_pmc_event)(u64 event);
int n_generic; u32 flags;
int *generic_events; int n_generic;
int (*cache_events)[PERF_COUNT_HW_CACHE_MAX] int *generic_events;
int (*cache_events)[PERF_COUNT_HW_CACHE_MAX]
[PERF_COUNT_HW_CACHE_OP_MAX] [PERF_COUNT_HW_CACHE_OP_MAX]
[PERF_COUNT_HW_CACHE_RESULT_MAX]; [PERF_COUNT_HW_CACHE_RESULT_MAX];
}; };
...@@ -68,8 +69,8 @@ extern unsigned long perf_instruction_pointer(struct pt_regs *regs); ...@@ -68,8 +69,8 @@ extern unsigned long perf_instruction_pointer(struct pt_regs *regs);
#endif #endif
/* /*
* The power_pmu.get_constraint function returns a 64-bit value and * The power_pmu.get_constraint function returns a 32/64-bit value and
* a 64-bit mask that express the constraints between this event and * a 32/64-bit mask that express the constraints between this event and
* other events. * other events.
* *
* The value and mask are divided up into (non-overlapping) bitfields * The value and mask are divided up into (non-overlapping) bitfields
......
arch/powerpc/kernel/perf_counter.c
View file @ 448d64f8
...@@ -29,7 +29,7 @@ struct cpu_hw_counters { ...@@ -29,7 +29,7 @@ struct cpu_hw_counters {
struct perf_counter *counter[MAX_HWCOUNTERS]; struct perf_counter *counter[MAX_HWCOUNTERS];
u64 events[MAX_HWCOUNTERS]; u64 events[MAX_HWCOUNTERS];
unsigned int flags[MAX_HWCOUNTERS]; unsigned int flags[MAX_HWCOUNTERS];
u64 mmcr[3]; unsigned long mmcr[3];
struct perf_counter *limited_counter[MAX_LIMITED_HWCOUNTERS]; struct perf_counter *limited_counter[MAX_LIMITED_HWCOUNTERS];
u8 limited_hwidx[MAX_LIMITED_HWCOUNTERS]; u8 limited_hwidx[MAX_LIMITED_HWCOUNTERS];
}; };
...@@ -135,15 +135,15 @@ static void write_pmc(int idx, unsigned long val) ...@@ -135,15 +135,15 @@ static void write_pmc(int idx, unsigned long val)
static int power_check_constraints(u64 event[], unsigned int cflags[], static int power_check_constraints(u64 event[], unsigned int cflags[],
int n_ev) int n_ev)
{ {
u64 mask, value, nv; unsigned long mask, value, nv;
u64 alternatives[MAX_HWCOUNTERS][MAX_EVENT_ALTERNATIVES]; u64 alternatives[MAX_HWCOUNTERS][MAX_EVENT_ALTERNATIVES];
u64 amasks[MAX_HWCOUNTERS][MAX_EVENT_ALTERNATIVES]; unsigned long amasks[MAX_HWCOUNTERS][MAX_EVENT_ALTERNATIVES];
u64 avalues[MAX_HWCOUNTERS][MAX_EVENT_ALTERNATIVES]; unsigned long avalues[MAX_HWCOUNTERS][MAX_EVENT_ALTERNATIVES];
u64 smasks[MAX_HWCOUNTERS], svalues[MAX_HWCOUNTERS]; unsigned long smasks[MAX_HWCOUNTERS], svalues[MAX_HWCOUNTERS];
int n_alt[MAX_HWCOUNTERS], choice[MAX_HWCOUNTERS]; int n_alt[MAX_HWCOUNTERS], choice[MAX_HWCOUNTERS];
int i, j; int i, j;
u64 addf = ppmu->add_fields; unsigned long addf = ppmu->add_fields;
u64 tadd = ppmu->test_adder; unsigned long tadd = ppmu->test_adder;
if (n_ev > ppmu->n_counter) if (n_ev > ppmu->n_counter)
return -1; return -1;
...@@ -403,14 +403,12 @@ static void write_mmcr0(struct cpu_hw_counters *cpuhw, unsigned long mmcr0) ...@@ -403,14 +403,12 @@ static void write_mmcr0(struct cpu_hw_counters *cpuhw, unsigned long mmcr0)
void hw_perf_disable(void) void hw_perf_disable(void)
{ {
struct cpu_hw_counters *cpuhw; struct cpu_hw_counters *cpuhw;
unsigned long ret;
unsigned long flags; unsigned long flags;
local_irq_save(flags); local_irq_save(flags);
cpuhw = &__get_cpu_var(cpu_hw_counters); cpuhw = &__get_cpu_var(cpu_hw_counters);
ret = cpuhw->disabled; if (!cpuhw->disabled) {
if (!ret) {
cpuhw->disabled = 1; cpuhw->disabled = 1;
cpuhw->n_added = 0; cpuhw->n_added = 0;
...@@ -1013,9 +1011,9 @@ static void record_and_restart(struct perf_counter *counter, long val, ...@@ -1013,9 +1011,9 @@ static void record_and_restart(struct perf_counter *counter, long val,
struct pt_regs *regs, int nmi) struct pt_regs *regs, int nmi)
{ {
u64 period = counter->hw.sample_period; u64 period = counter->hw.sample_period;
unsigned long mmcra, sdsync;
s64 prev, delta, left; s64 prev, delta, left;
int record = 0; int record = 0;
u64 mmcra, sdsync;
/* we don't have to worry about interrupts here */ /* we don't have to worry about interrupts here */
prev = atomic64_read(&counter->hw.prev_count); prev = atomic64_read(&counter->hw.prev_count);
......
arch/powerpc/kernel/power4-pmu.c
View file @ 448d64f8
...@@ -179,22 +179,22 @@ static short mmcr1_adder_bits[8] = { ...@@ -179,22 +179,22 @@ static short mmcr1_adder_bits[8] = {
*/ */
static struct unitinfo { static struct unitinfo {
u64 value, mask; unsigned long value, mask;
int unit; int unit;
int lowerbit; int lowerbit;
} p4_unitinfo[16] = { } p4_unitinfo[16] = {
[PM_FPU] = { 0x44000000000000ull, 0x88000000000000ull, PM_FPU, 0 }, [PM_FPU] = { 0x44000000000000ul, 0x88000000000000ul, PM_FPU, 0 },
[PM_ISU1] = { 0x20080000000000ull, 0x88000000000000ull, PM_ISU1, 0 }, [PM_ISU1] = { 0x20080000000000ul, 0x88000000000000ul, PM_ISU1, 0 },
[PM_ISU1_ALT] = [PM_ISU1_ALT] =
{ 0x20080000000000ull, 0x88000000000000ull, PM_ISU1, 0 }, { 0x20080000000000ul, 0x88000000000000ul, PM_ISU1, 0 },
[PM_IFU] = { 0x02200000000000ull, 0x08820000000000ull, PM_IFU, 41 }, [PM_IFU] = { 0x02200000000000ul, 0x08820000000000ul, PM_IFU, 41 },
[PM_IFU_ALT] = [PM_IFU_ALT] =
{ 0x02200000000000ull, 0x08820000000000ull, PM_IFU, 41 }, { 0x02200000000000ul, 0x08820000000000ul, PM_IFU, 41 },
[PM_IDU0] = { 0x10100000000000ull, 0x80840000000000ull, PM_IDU0, 1 }, [PM_IDU0] = { 0x10100000000000ul, 0x80840000000000ul, PM_IDU0, 1 },
[PM_ISU2] = { 0x10140000000000ull, 0x80840000000000ull, PM_ISU2, 0 }, [PM_ISU2] = { 0x10140000000000ul, 0x80840000000000ul, PM_ISU2, 0 },
[PM_LSU0] = { 0x01400000000000ull, 0x08800000000000ull, PM_LSU0, 0 }, [PM_LSU0] = { 0x01400000000000ul, 0x08800000000000ul, PM_LSU0, 0 },
[PM_LSU1] = { 0x00000000000000ull, 0x00010000000000ull, PM_LSU1, 40 }, [PM_LSU1] = { 0x00000000000000ul, 0x00010000000000ul, PM_LSU1, 40 },
[PM_GPS] = { 0x00000000000000ull, 0x00000000000000ull, PM_GPS, 0 } [PM_GPS] = { 0x00000000000000ul, 0x00000000000000ul, PM_GPS, 0 }
}; };
static unsigned char direct_marked_event[8] = { static unsigned char direct_marked_event[8] = {
...@@ -249,10 +249,11 @@ static int p4_marked_instr_event(u64 event) ...@@ -249,10 +249,11 @@ static int p4_marked_instr_event(u64 event)
return (mask >> (byte * 8 + bit)) & 1; return (mask >> (byte * 8 + bit)) & 1;
} }
static int p4_get_constraint(u64 event, u64 *maskp, u64 *valp) static int p4_get_constraint(u64 event, unsigned long *maskp,
unsigned long *valp)
{ {
int pmc, byte, unit, lower, sh; int pmc, byte, unit, lower, sh;
u64 mask = 0, value = 0; unsigned long mask = 0, value = 0;
int grp = -1; int grp = -1;
pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
...@@ -282,14 +283,14 @@ static int p4_get_constraint(u64 event, u64 *maskp, u64 *valp) ...@@ -282,14 +283,14 @@ static int p4_get_constraint(u64 event, u64 *maskp, u64 *valp)
value |= p4_unitinfo[unit].value; value |= p4_unitinfo[unit].value;
sh = p4_unitinfo[unit].lowerbit; sh = p4_unitinfo[unit].lowerbit;
if (sh > 1) if (sh > 1)
value |= (u64)lower << sh; value |= (unsigned long)lower << sh;
else if (lower != sh) else if (lower != sh)
return -1; return -1;
unit = p4_unitinfo[unit].unit; unit = p4_unitinfo[unit].unit;
/* Set byte lane select field */ /* Set byte lane select field */
mask |= 0xfULL << (28 - 4 * byte); mask |= 0xfULL << (28 - 4 * byte);
value |= (u64)unit << (28 - 4 * byte); value |= (unsigned long)unit << (28 - 4 * byte);
} }
if (grp == 0) { if (grp == 0) {
/* increment PMC1/2/5/6 field */ /* increment PMC1/2/5/6 field */
...@@ -353,9 +354,9 @@ static int p4_get_alternatives(u64 event, unsigned int flags, u64 alt[]) ...@@ -353,9 +354,9 @@ static int p4_get_alternatives(u64 event, unsigned int flags, u64 alt[])
} }
static int p4_compute_mmcr(u64 event[], int n_ev, static int p4_compute_mmcr(u64 event[], int n_ev,
unsigned int hwc[], u64 mmcr[]) unsigned int hwc[], unsigned long mmcr[])
{ {
u64 mmcr0 = 0, mmcr1 = 0, mmcra = 0; unsigned long mmcr0 = 0, mmcr1 = 0, mmcra = 0;
unsigned int pmc, unit, byte, psel, lower; unsigned int pmc, unit, byte, psel, lower;
unsigned int ttm, grp; unsigned int ttm, grp;
unsigned int pmc_inuse = 0; unsigned int pmc_inuse = 0;
...@@ -429,9 +430,11 @@ static int p4_compute_mmcr(u64 event[], int n_ev, ...@@ -429,9 +430,11 @@ static int p4_compute_mmcr(u64 event[], int n_ev,
return -1; return -1;
/* Set TTMxSEL fields. Note, units 1-3 => TTM0SEL codes 0-2 */ /* Set TTMxSEL fields. Note, units 1-3 => TTM0SEL codes 0-2 */
mmcr1 |= (u64)(unituse[3] * 2 + unituse[2]) << MMCR1_TTM0SEL_SH; mmcr1 |= (unsigned long)(unituse[3] * 2 + unituse[2])
mmcr1 |= (u64)(unituse[7] * 3 + unituse[6] * 2) << MMCR1_TTM1SEL_SH; << MMCR1_TTM0SEL_SH;
mmcr1 |= (u64)unituse[9] << MMCR1_TTM2SEL_SH; mmcr1 |= (unsigned long)(unituse[7] * 3 + unituse[6] * 2)
<< MMCR1_TTM1SEL_SH;
mmcr1 |= (unsigned long)unituse[9] << MMCR1_TTM2SEL_SH;
/* Set TTCxSEL fields. */ /* Set TTCxSEL fields. */
if (unitlower & 0xe) if (unitlower & 0xe)
...@@ -456,7 +459,8 @@ static int p4_compute_mmcr(u64 event[], int n_ev, ...@@ -456,7 +459,8 @@ static int p4_compute_mmcr(u64 event[], int n_ev,
ttm = unit - 1; /* 2->1, 3->2 */ ttm = unit - 1; /* 2->1, 3->2 */
else else
ttm = unit >> 2; ttm = unit >> 2;
mmcr1 |= (u64)ttm << (MMCR1_TD_CP_DBG0SEL_SH - 2*byte); mmcr1 |= (unsigned long)ttm
<< (MMCR1_TD_CP_DBG0SEL_SH - 2 * byte);
} }
} }
...@@ -519,7 +523,7 @@ static int p4_compute_mmcr(u64 event[], int n_ev, ...@@ -519,7 +523,7 @@ static int p4_compute_mmcr(u64 event[], int n_ev,
return 0; return 0;
} }
static void p4_disable_pmc(unsigned int pmc, u64 mmcr[]) static void p4_disable_pmc(unsigned int pmc, unsigned long mmcr[])
{ {
/* /*
* Setting the PMCxSEL field to 0 disables PMC x. * Setting the PMCxSEL field to 0 disables PMC x.
...@@ -584,15 +588,15 @@ static int power4_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { ...@@ -584,15 +588,15 @@ static int power4_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
}; };
struct power_pmu power4_pmu = { struct power_pmu power4_pmu = {
.n_counter = 8, .n_counter = 8,
.max_alternatives = 5, .max_alternatives = 5,
.add_fields = 0x0000001100005555ull, .add_fields = 0x0000001100005555ul,
.test_adder = 0x0011083300000000ull, .test_adder = 0x0011083300000000ul,
.compute_mmcr = p4_compute_mmcr, .compute_mmcr = p4_compute_mmcr,
.get_constraint = p4_get_constraint, .get_constraint = p4_get_constraint,
.get_alternatives = p4_get_alternatives, .get_alternatives = p4_get_alternatives,
.disable_pmc = p4_disable_pmc, .disable_pmc = p4_disable_pmc,
.n_generic = ARRAY_SIZE(p4_generic_events), .n_generic = ARRAY_SIZE(p4_generic_events),
.generic_events = p4_generic_events, .generic_events = p4_generic_events,
.cache_events = &power4_cache_events, .cache_events = &power4_cache_events,
}; };
arch/powerpc/kernel/power5+-pmu.c
View file @ 448d64f8
...@@ -126,20 +126,21 @@ static const int grsel_shift[8] = { ...@@ -126,20 +126,21 @@ static const int grsel_shift[8] = {
}; };
/* Masks and values for using events from the various units */ /* Masks and values for using events from the various units */
static u64 unit_cons[PM_LASTUNIT+1][2] = { static unsigned long unit_cons[PM_LASTUNIT+1][2] = {
[PM_FPU] = { 0x3200000000ull, 0x0100000000ull }, [PM_FPU] = { 0x3200000000ul, 0x0100000000ul },
[PM_ISU0] = { 0x0200000000ull, 0x0080000000ull }, [PM_ISU0] = { 0x0200000000ul, 0x0080000000ul },
[PM_ISU1] = { 0x3200000000ull, 0x3100000000ull }, [PM_ISU1] = { 0x3200000000ul, 0x3100000000ul },
[PM_IFU] = { 0x3200000000ull, 0x2100000000ull }, [PM_IFU] = { 0x3200000000ul, 0x2100000000ul },
[PM_IDU] = { 0x0e00000000ull, 0x0040000000ull }, [PM_IDU] = { 0x0e00000000ul, 0x0040000000ul },
[PM_GRS] = { 0x0e00000000ull, 0x0c40000000ull }, [PM_GRS] = { 0x0e00000000ul, 0x0c40000000ul },
}; };
static int power5p_get_constraint(u64 event, u64 *maskp, u64 *valp) static int power5p_get_constraint(u64 event, unsigned long *maskp,
unsigned long *valp)
{ {
int pmc, byte, unit, sh; int pmc, byte, unit, sh;
int bit, fmask; int bit, fmask;
u64 mask = 0, value = 0; unsigned long mask = 0, value = 0;
pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
if (pmc) { if (pmc) {
...@@ -171,17 +172,18 @@ static int power5p_get_constraint(u64 event, u64 *maskp, u64 *valp) ...@@ -171,17 +172,18 @@ static int power5p_get_constraint(u64 event, u64 *maskp, u64 *valp)
bit = event & 7; bit = event & 7;
fmask = (bit == 6)? 7: 3; fmask = (bit == 6)? 7: 3;
sh = grsel_shift[bit]; sh = grsel_shift[bit];
mask |= (u64)fmask << sh; mask |= (unsigned long)fmask << sh;
value |= (u64)((event >> PM_GRS_SH) & fmask) << sh; value |= (unsigned long)((event >> PM_GRS_SH) & fmask)
<< sh;
} }
/* Set byte lane select field */ /* Set byte lane select field */
mask |= 0xfULL << (24 - 4 * byte); mask |= 0xfUL << (24 - 4 * byte);
value |= (u64)unit << (24 - 4 * byte); value |= (unsigned long)unit << (24 - 4 * byte);
} }
if (pmc < 5) { if (pmc < 5) {
/* need a counter from PMC1-4 set */ /* need a counter from PMC1-4 set */
mask |= 0x8000000000000ull; mask |= 0x8000000000000ul;
value |= 0x1000000000000ull; value |= 0x1000000000000ul;
} }
*maskp = mask; *maskp = mask;
*valp = value; *valp = value;
...@@ -452,10 +454,10 @@ static int power5p_marked_instr_event(u64 event) ...@@ -452,10 +454,10 @@ static int power5p_marked_instr_event(u64 event)
} }
static int power5p_compute_mmcr(u64 event[], int n_ev, static int power5p_compute_mmcr(u64 event[], int n_ev,
unsigned int hwc[], u64 mmcr[]) unsigned int hwc[], unsigned long mmcr[])
{ {
u64 mmcr1 = 0; unsigned long mmcr1 = 0;
u64 mmcra = 0; unsigned long mmcra = 0;
unsigned int pmc, unit, byte, psel; unsigned int pmc, unit, byte, psel;
unsigned int ttm; unsigned int ttm;
int i, isbus, bit, grsel; int i, isbus, bit, grsel;
...@@ -517,7 +519,7 @@ static int power5p_compute_mmcr(u64 event[], int n_ev, ...@@ -517,7 +519,7 @@ static int power5p_compute_mmcr(u64 event[], int n_ev,
continue; continue;
if (ttmuse++) if (ttmuse++)
return -1; return -1;
mmcr1 |= (u64)i << MMCR1_TTM0SEL_SH; mmcr1 |= (unsigned long)i << MMCR1_TTM0SEL_SH;
} }
ttmuse = 0; ttmuse = 0;
for (; i <= PM_GRS; ++i) { for (; i <= PM_GRS; ++i) {
...@@ -525,7 +527,7 @@ static int power5p_compute_mmcr(u64 event[], int n_ev, ...@@ -525,7 +527,7 @@ static int power5p_compute_mmcr(u64 event[], int n_ev,
continue; continue;
if (ttmuse++) if (ttmuse++)
return -1; return -1;
mmcr1 |= (u64)(i & 3) << MMCR1_TTM1SEL_SH; mmcr1 |= (unsigned long)(i & 3) << MMCR1_TTM1SEL_SH;
} }
if (ttmuse > 1) if (ttmuse > 1)
return -1; return -1;
...@@ -540,10 +542,11 @@ static int power5p_compute_mmcr(u64 event[], int n_ev, ...@@ -540,10 +542,11 @@ static int power5p_compute_mmcr(u64 event[], int n_ev,
unit = PM_ISU0_ALT; unit = PM_ISU0_ALT;
} else if (unit == PM_LSU1 + 1) { } else if (unit == PM_LSU1 + 1) {
/* select lower word of LSU1 for this byte */ /* select lower word of LSU1 for this byte */
mmcr1 |= 1ull << (MMCR1_TTM3SEL_SH + 3 - byte); mmcr1 |= 1ul << (MMCR1_TTM3SEL_SH + 3 - byte);
} }
ttm = unit >> 2; ttm = unit >> 2;
mmcr1 |= (u64)ttm << (MMCR1_TD_CP_DBG0SEL_SH - 2 * byte); mmcr1 |= (unsigned long)ttm
<< (MMCR1_TD_CP_DBG0SEL_SH - 2 * byte);
} }
/* Second pass: assign PMCs, set PMCxSEL and PMCx_ADDER_SEL fields */ /* Second pass: assign PMCs, set PMCxSEL and PMCx_ADDER_SEL fields */
...@@ -568,7 +571,7 @@ static int power5p_compute_mmcr(u64 event[], int n_ev, ...@@ -568,7 +571,7 @@ static int power5p_compute_mmcr(u64 event[], int n_ev,
if (isbus && (byte & 2) && if (isbus && (byte & 2) &&
(psel == 8 || psel == 0x10 || psel == 0x28)) (psel == 8 || psel == 0x10 || psel == 0x28))
/* add events on higher-numbered bus */ /* add events on higher-numbered bus */
mmcr1 |= 1ull << (MMCR1_PMC1_ADDER_SEL_SH - pmc); mmcr1 |= 1ul << (MMCR1_PMC1_ADDER_SEL_SH - pmc);
} else { } else {
/* Instructions or run cycles on PMC5/6 */ /* Instructions or run cycles on PMC5/6 */
--pmc; --pmc;
...@@ -576,7 +579,7 @@ static int power5p_compute_mmcr(u64 event[], int n_ev, ...@@ -576,7 +579,7 @@ static int power5p_compute_mmcr(u64 event[], int n_ev,
if (isbus && unit == PM_GRS) { if (isbus && unit == PM_GRS) {
bit = psel & 7; bit = psel & 7;
grsel = (event[i] >> PM_GRS_SH) & PM_GRS_MSK; grsel = (event[i] >> PM_GRS_SH) & PM_GRS_MSK;
mmcr1 |= (u64)grsel << grsel_shift[bit]; mmcr1 |= (unsigned long)grsel << grsel_shift[bit];
} }
if (power5p_marked_instr_event(event[i])) if (power5p_marked_instr_event(event[i]))
mmcra |= MMCRA_SAMPLE_ENABLE; mmcra |= MMCRA_SAMPLE_ENABLE;
...@@ -599,7 +602,7 @@ static int power5p_compute_mmcr(u64 event[], int n_ev, ...@@ -599,7 +602,7 @@ static int power5p_compute_mmcr(u64 event[], int n_ev,
return 0; return 0;
} }
static void power5p_disable_pmc(unsigned int pmc, u64 mmcr[]) static void power5p_disable_pmc(unsigned int pmc, unsigned long mmcr[])
{ {
if (pmc <= 3) if (pmc <= 3)
mmcr[1] &= ~(0x7fUL << MMCR1_PMCSEL_SH(pmc)); mmcr[1] &= ~(0x7fUL << MMCR1_PMCSEL_SH(pmc));
...@@ -655,17 +658,17 @@ static int power5p_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { ...@@ -655,17 +658,17 @@ static int power5p_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
}; };
struct power_pmu power5p_pmu = { struct power_pmu power5p_pmu = {
.n_counter = 6, .n_counter = 6,
.max_alternatives = MAX_ALT, .max_alternatives = MAX_ALT,
.add_fields = 0x7000000000055ull, .add_fields = 0x7000000000055ul,
.test_adder = 0x3000040000000ull, .test_adder = 0x3000040000000ul,
.compute_mmcr = power5p_compute_mmcr, .compute_mmcr = power5p_compute_mmcr,
.get_constraint = power5p_get_constraint, .get_constraint = power5p_get_constraint,
.get_alternatives = power5p_get_alternatives, .get_alternatives = power5p_get_alternatives,
.disable_pmc = power5p_disable_pmc, .disable_pmc = power5p_disable_pmc,
.limited_pmc_event = power5p_limited_pmc_event, .limited_pmc_event = power5p_limited_pmc_event,
.flags = PPMU_LIMITED_PMC5_6, .flags = PPMU_LIMITED_PMC5_6,
.n_generic = ARRAY_SIZE(power5p_generic_events), .n_generic = ARRAY_SIZE(power5p_generic_events),
.generic_events = power5p_generic_events, .generic_events = power5p_generic_events,
.cache_events = &power5p_cache_events, .cache_events = &power5p_cache_events,
}; };
arch/powerpc/kernel/power5-pmu.c
View file @ 448d64f8
...@@ -130,20 +130,21 @@ static const int grsel_shift[8] = { ...@@ -130,20 +130,21 @@ static const int grsel_shift[8] = {
}; };
/* Masks and values for using events from the various units */ /* Masks and values for using events from the various units */
static u64 unit_cons[PM_LASTUNIT+1][2] = { static unsigned long unit_cons[PM_LASTUNIT+1][2] = {
[PM_FPU] = { 0xc0002000000000ull, 0x00001000000000ull }, [PM_FPU] = { 0xc0002000000000ul, 0x00001000000000ul },
[PM_ISU0] = { 0x00002000000000ull, 0x00000800000000ull }, [PM_ISU0] = { 0x00002000000000ul, 0x00000800000000ul },
[PM_ISU1] = { 0xc0002000000000ull, 0xc0001000000000ull }, [PM_ISU1] = { 0xc0002000000000ul, 0xc0001000000000ul },
[PM_IFU] = { 0xc0002000000000ull, 0x80001000000000ull }, [PM_IFU] = { 0xc0002000000000ul, 0x80001000000000ul },
[PM_IDU] = { 0x30002000000000ull, 0x00000400000000ull }, [PM_IDU] = { 0x30002000000000ul, 0x00000400000000ul },
[PM_GRS] = { 0x30002000000000ull, 0x30000400000000ull }, [PM_GRS] = { 0x30002000000000ul, 0x30000400000000ul },
}; };
static int power5_get_constraint(u64 event, u64 *maskp, u64 *valp) static int power5_get_constraint(u64 event, unsigned long *maskp,
unsigned long *valp)
{ {
int pmc, byte, unit, sh; int pmc, byte, unit, sh;
int bit, fmask; int bit, fmask;
u64 mask = 0, value = 0; unsigned long mask = 0, value = 0;
int grp = -1; int grp = -1;
pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
...@@ -178,8 +179,9 @@ static int power5_get_constraint(u64 event, u64 *maskp, u64 *valp) ...@@ -178,8 +179,9 @@ static int power5_get_constraint(u64 event, u64 *maskp, u64 *valp)
bit = event & 7; bit = event & 7;
fmask = (bit == 6)? 7: 3; fmask = (bit == 6)? 7: 3;
sh = grsel_shift[bit]; sh = grsel_shift[bit];
mask |= (u64)fmask << sh; mask |= (unsigned long)fmask << sh;
value |= (u64)((event >> PM_GRS_SH) & fmask) << sh; value |= (unsigned long)((event >> PM_GRS_SH) & fmask)
<< sh;
} }
/* /*
* Bus events on bytes 0 and 2 can be counted * Bus events on bytes 0 and 2 can be counted
...@@ -188,22 +190,22 @@ static int power5_get_constraint(u64 event, u64 *maskp, u64 *valp) ...@@ -188,22 +190,22 @@ static int power5_get_constraint(u64 event, u64 *maskp, u64 *valp)
if (!pmc) if (!pmc)
grp = byte & 1; grp = byte & 1;
/* Set byte lane select field */ /* Set byte lane select field */
mask |= 0xfULL << (24 - 4 * byte); mask |= 0xfUL << (24 - 4 * byte);
value |= (u64)unit << (24 - 4 * byte); value |= (unsigned long)unit << (24 - 4 * byte);
} }
if (grp == 0) { if (grp == 0) {
/* increment PMC1/2 field */ /* increment PMC1/2 field */
mask |= 0x200000000ull; mask |= 0x200000000ul;
value |= 0x080000000ull; value |= 0x080000000ul;
} else if (grp == 1) { } else if (grp == 1) {
/* increment PMC3/4 field */ /* increment PMC3/4 field */
mask |= 0x40000000ull; mask |= 0x40000000ul;
value |= 0x10000000ull; value |= 0x10000000ul;
} }
if (pmc < 5) { if (pmc < 5) {
/* need a counter from PMC1-4 set */ /* need a counter from PMC1-4 set */
mask |= 0x8000000000000ull; mask |= 0x8000000000000ul;
value |= 0x1000000000000ull; value |= 0x1000000000000ul;
} }
*maskp = mask; *maskp = mask;
*valp = value; *valp = value;
...@@ -383,10 +385,10 @@ static int power5_marked_instr_event(u64 event) ...@@ -383,10 +385,10 @@ static int power5_marked_instr_event(u64 event)
} }
static int power5_compute_mmcr(u64 event[], int n_ev, static int power5_compute_mmcr(u64 event[], int n_ev,
unsigned int hwc[], u64 mmcr[]) unsigned int hwc[], unsigned long mmcr[])
{ {
u64 mmcr1 = 0; unsigned long mmcr1 = 0;
u64 mmcra = 0; unsigned long mmcra = 0;
unsigned int pmc, unit, byte, psel; unsigned int pmc, unit, byte, psel;
unsigned int ttm, grp; unsigned int ttm, grp;
int i, isbus, bit, grsel; int i, isbus, bit, grsel;
...@@ -457,7 +459,7 @@ static int power5_compute_mmcr(u64 event[], int n_ev, ...@@ -457,7 +459,7 @@ static int power5_compute_mmcr(u64 event[], int n_ev,
continue; continue;
if (ttmuse++) if (ttmuse++)
return -1; return -1;
mmcr1 |= (u64)i << MMCR1_TTM0SEL_SH; mmcr1 |= (unsigned long)i << MMCR1_TTM0SEL_SH;
} }
ttmuse = 0; ttmuse = 0;
for (; i <= PM_GRS; ++i) { for (; i <= PM_GRS; ++i) {
...@@ -465,7 +467,7 @@ static int power5_compute_mmcr(u64 event[], int n_ev, ...@@ -465,7 +467,7 @@ static int power5_compute_mmcr(u64 event[], int n_ev,
continue; continue;
if (ttmuse++) if (ttmuse++)
return -1; return -1;
mmcr1 |= (u64)(i & 3) << MMCR1_TTM1SEL_SH; mmcr1 |= (unsigned long)(i & 3) << MMCR1_TTM1SEL_SH;
} }
if (ttmuse > 1) if (ttmuse > 1)
return -1; return -1;
...@@ -480,10 +482,11 @@ static int power5_compute_mmcr(u64 event[], int n_ev, ...@@ -480,10 +482,11 @@ static int power5_compute_mmcr(u64 event[], int n_ev,
unit = PM_ISU0_ALT; unit = PM_ISU0_ALT;
} else if (unit == PM_LSU1 + 1) { } else if (unit == PM_LSU1 + 1) {
/* select lower word of LSU1 for this byte */ /* select lower word of LSU1 for this byte */
mmcr1 |= 1ull << (MMCR1_TTM3SEL_SH + 3 - byte); mmcr1 |= 1ul << (MMCR1_TTM3SEL_SH + 3 - byte);
} }
ttm = unit >> 2; ttm = unit >> 2;
mmcr1 |= (u64)ttm << (MMCR1_TD_CP_DBG0SEL_SH - 2 * byte); mmcr1 |= (unsigned long)ttm
<< (MMCR1_TD_CP_DBG0SEL_SH - 2 * byte);
} }
/* Second pass: assign PMCs, set PMCxSEL and PMCx_ADDER_SEL fields */ /* Second pass: assign PMCs, set PMCxSEL and PMCx_ADDER_SEL fields */
...@@ -513,7 +516,7 @@ static int power5_compute_mmcr(u64 event[], int n_ev, ...@@ -513,7 +516,7 @@ static int power5_compute_mmcr(u64 event[], int n_ev,
--pmc; --pmc;
if ((psel == 8 || psel == 0x10) && isbus && (byte & 2)) if ((psel == 8 || psel == 0x10) && isbus && (byte & 2))
/* add events on higher-numbered bus */ /* add events on higher-numbered bus */
mmcr1 |= 1ull << (MMCR1_PMC1_ADDER_SEL_SH - pmc); mmcr1 |= 1ul << (MMCR1_PMC1_ADDER_SEL_SH - pmc);
} else { } else {
/* Instructions or run cycles on PMC5/6 */ /* Instructions or run cycles on PMC5/6 */
--pmc; --pmc;
...@@ -521,7 +524,7 @@ static int power5_compute_mmcr(u64 event[], int n_ev, ...@@ -521,7 +524,7 @@ static int power5_compute_mmcr(u64 event[], int n_ev,
if (isbus && unit == PM_GRS) { if (isbus && unit == PM_GRS) {
bit = psel & 7; bit = psel & 7;
grsel = (event[i] >> PM_GRS_SH) & PM_GRS_MSK; grsel = (event[i] >> PM_GRS_SH) & PM_GRS_MSK;
mmcr1 |= (u64)grsel << grsel_shift[bit]; mmcr1 |= (unsigned long)grsel << grsel_shift[bit];
} }
if (power5_marked_instr_event(event[i])) if (power5_marked_instr_event(event[i]))
mmcra |= MMCRA_SAMPLE_ENABLE; mmcra |= MMCRA_SAMPLE_ENABLE;
...@@ -541,7 +544,7 @@ static int power5_compute_mmcr(u64 event[], int n_ev, ...@@ -541,7 +544,7 @@ static int power5_compute_mmcr(u64 event[], int n_ev,
return 0; return 0;
} }
static void power5_disable_pmc(unsigned int pmc, u64 mmcr[]) static void power5_disable_pmc(unsigned int pmc, unsigned long mmcr[])
{ {
if (pmc <= 3) if (pmc <= 3)
mmcr[1] &= ~(0x7fUL << MMCR1_PMCSEL_SH(pmc)); mmcr[1] &= ~(0x7fUL << MMCR1_PMCSEL_SH(pmc));
...@@ -597,15 +600,15 @@ static int power5_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { ...@@ -597,15 +600,15 @@ static int power5_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
}; };
struct power_pmu power5_pmu = { struct power_pmu power5_pmu = {
.n_counter = 6, .n_counter = 6,
.max_alternatives = MAX_ALT, .max_alternatives = MAX_ALT,
.add_fields = 0x7000090000555ull, .add_fields = 0x7000090000555ul,
.test_adder = 0x3000490000000ull, .test_adder = 0x3000490000000ul,
.compute_mmcr = power5_compute_mmcr, .compute_mmcr = power5_compute_mmcr,
.get_constraint = power5_get_constraint, .get_constraint = power5_get_constraint,
.get_alternatives = power5_get_alternatives, .get_alternatives = power5_get_alternatives,
.disable_pmc = power5_disable_pmc, .disable_pmc = power5_disable_pmc,
.n_generic = ARRAY_SIZE(power5_generic_events), .n_generic = ARRAY_SIZE(power5_generic_events),
.generic_events = power5_generic_events, .generic_events = power5_generic_events,
.cache_events = &power5_cache_events, .cache_events = &power5_cache_events,
}; };
arch/powerpc/kernel/power6-pmu.c
View file @ 448d64f8
...@@ -41,9 +41,9 @@ ...@@ -41,9 +41,9 @@
#define MMCR1_NESTSEL_SH 45 #define MMCR1_NESTSEL_SH 45
#define MMCR1_NESTSEL_MSK 0x7 #define MMCR1_NESTSEL_MSK 0x7
#define MMCR1_NESTSEL(m) (((m) >> MMCR1_NESTSEL_SH) & MMCR1_NESTSEL_MSK) #define MMCR1_NESTSEL(m) (((m) >> MMCR1_NESTSEL_SH) & MMCR1_NESTSEL_MSK)
#define MMCR1_PMC1_LLA ((u64)1 << 44) #define MMCR1_PMC1_LLA (1ul << 44)
#define MMCR1_PMC1_LLA_VALUE ((u64)1 << 39) #define MMCR1_PMC1_LLA_VALUE (1ul << 39)
#define MMCR1_PMC1_ADDR_SEL ((u64)1 << 35) #define MMCR1_PMC1_ADDR_SEL (1ul << 35)
#define MMCR1_PMC1SEL_SH 24 #define MMCR1_PMC1SEL_SH 24
#define MMCR1_PMCSEL_SH(n) (MMCR1_PMC1SEL_SH - (n) * 8) #define MMCR1_PMCSEL_SH(n) (MMCR1_PMC1SEL_SH - (n) * 8)
#define MMCR1_PMCSEL_MSK 0xff #define MMCR1_PMCSEL_MSK 0xff
...@@ -173,10 +173,10 @@ static int power6_marked_instr_event(u64 event) ...@@ -173,10 +173,10 @@ static int power6_marked_instr_event(u64 event)
* Assign PMC numbers and compute MMCR1 value for a set of events * Assign PMC numbers and compute MMCR1 value for a set of events
*/ */
static int p6_compute_mmcr(u64 event[], int n_ev, static int p6_compute_mmcr(u64 event[], int n_ev,
unsigned int hwc[], u64 mmcr[]) unsigned int hwc[], unsigned long mmcr[])
{ {
u64 mmcr1 = 0; unsigned long mmcr1 = 0;
u64 mmcra = 0; unsigned long mmcra = 0;
int i; int i;
unsigned int pmc, ev, b, u, s, psel; unsigned int pmc, ev, b, u, s, psel;
unsigned int ttmset = 0; unsigned int ttmset = 0;
...@@ -215,7 +215,7 @@ static int p6_compute_mmcr(u64 event[], int n_ev, ...@@ -215,7 +215,7 @@ static int p6_compute_mmcr(u64 event[], int n_ev,
/* check for conflict on this byte of event bus */ /* check for conflict on this byte of event bus */
if ((ttmset & (1 << b)) && MMCR1_TTMSEL(mmcr1, b) != u) if ((ttmset & (1 << b)) && MMCR1_TTMSEL(mmcr1, b) != u)
return -1; return -1;
mmcr1 |= (u64)u << MMCR1_TTMSEL_SH(b); mmcr1 |= (unsigned long)u << MMCR1_TTMSEL_SH(b);
ttmset |= 1 << b; ttmset |= 1 << b;
if (u == 5) { if (u == 5) {
/* Nest events have a further mux */ /* Nest events have a further mux */
...@@ -224,7 +224,7 @@ static int p6_compute_mmcr(u64 event[], int n_ev, ...@@ -224,7 +224,7 @@ static int p6_compute_mmcr(u64 event[], int n_ev,
MMCR1_NESTSEL(mmcr1) != s) MMCR1_NESTSEL(mmcr1) != s)
return -1; return -1;
ttmset |= 0x10; ttmset |= 0x10;
mmcr1 |= (u64)s << MMCR1_NESTSEL_SH; mmcr1 |= (unsigned long)s << MMCR1_NESTSEL_SH;
} }
if (0x30 <= psel && psel <= 0x3d) { if (0x30 <= psel && psel <= 0x3d) {
/* these need the PMCx_ADDR_SEL bits */ /* these need the PMCx_ADDR_SEL bits */
...@@ -243,7 +243,7 @@ static int p6_compute_mmcr(u64 event[], int n_ev, ...@@ -243,7 +243,7 @@ static int p6_compute_mmcr(u64 event[], int n_ev,
if (power6_marked_instr_event(event[i])) if (power6_marked_instr_event(event[i]))
mmcra |= MMCRA_SAMPLE_ENABLE; mmcra |= MMCRA_SAMPLE_ENABLE;
if (pmc < 4) if (pmc < 4)
mmcr1 |= (u64)psel << MMCR1_PMCSEL_SH(pmc); mmcr1 |= (unsigned long)psel << MMCR1_PMCSEL_SH(pmc);
} }
mmcr[0] = 0; mmcr[0] = 0;
if (pmc_inuse & 1) if (pmc_inuse & 1)
...@@ -265,10 +265,11 @@ static int p6_compute_mmcr(u64 event[], int n_ev, ...@@ -265,10 +265,11 @@ static int p6_compute_mmcr(u64 event[], int n_ev,
* 20-23, 24-27, 28-31 ditto for bytes 1, 2, 3 * 20-23, 24-27, 28-31 ditto for bytes 1, 2, 3
* 32-34 select field: nest (subunit) event selector * 32-34 select field: nest (subunit) event selector
*/ */
static int p6_get_constraint(u64 event, u64 *maskp, u64 *valp) static int p6_get_constraint(u64 event, unsigned long *maskp,
unsigned long *valp)
{ {
int pmc, byte, sh, subunit; int pmc, byte, sh, subunit;
u64 mask = 0, value = 0; unsigned long mask = 0, value = 0;
pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
if (pmc) { if (pmc) {
...@@ -282,11 +283,11 @@ static int p6_get_constraint(u64 event, u64 *maskp, u64 *valp) ...@@ -282,11 +283,11 @@ static int p6_get_constraint(u64 event, u64 *maskp, u64 *valp)
byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK; byte = (event >> PM_BYTE_SH) & PM_BYTE_MSK;
sh = byte * 4 + (16 - PM_UNIT_SH); sh = byte * 4 + (16 - PM_UNIT_SH);
mask |= PM_UNIT_MSKS << sh; mask |= PM_UNIT_MSKS << sh;
value |= (u64)(event & PM_UNIT_MSKS) << sh; value |= (unsigned long)(event & PM_UNIT_MSKS) << sh;
if ((event & PM_UNIT_MSKS) == (5 << PM_UNIT_SH)) { if ((event & PM_UNIT_MSKS) == (5 << PM_UNIT_SH)) {
subunit = (event >> PM_SUBUNIT_SH) & PM_SUBUNIT_MSK; subunit = (event >> PM_SUBUNIT_SH) & PM_SUBUNIT_MSK;
mask |= (u64)PM_SUBUNIT_MSK << 32; mask |= (unsigned long)PM_SUBUNIT_MSK << 32;
value |= (u64)subunit << 32; value |= (unsigned long)subunit << 32;
} }
} }
if (pmc <= 4) { if (pmc <= 4) {
...@@ -458,7 +459,7 @@ static int p6_get_alternatives(u64 event, unsigned int flags, u64 alt[]) ...@@ -458,7 +459,7 @@ static int p6_get_alternatives(u64 event, unsigned int flags, u64 alt[])
return nalt; return nalt;
} }
static void p6_disable_pmc(unsigned int pmc, u64 mmcr[]) static void p6_disable_pmc(unsigned int pmc, unsigned long mmcr[])
{ {
/* Set PMCxSEL to 0 to disable PMCx */ /* Set PMCxSEL to 0 to disable PMCx */
if (pmc <= 3) if (pmc <= 3)
...@@ -516,17 +517,17 @@ static int power6_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { ...@@ -516,17 +517,17 @@ static int power6_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
}; };
struct power_pmu power6_pmu = { struct power_pmu power6_pmu = {
.n_counter = 6, .n_counter = 6,
.max_alternatives = MAX_ALT, .max_alternatives = MAX_ALT,
.add_fields = 0x1555, .add_fields = 0x1555,
.test_adder = 0x3000, .test_adder = 0x3000,
.compute_mmcr = p6_compute_mmcr, .compute_mmcr = p6_compute_mmcr,
.get_constraint = p6_get_constraint, .get_constraint = p6_get_constraint,
.get_alternatives = p6_get_alternatives, .get_alternatives = p6_get_alternatives,
.disable_pmc = p6_disable_pmc, .disable_pmc = p6_disable_pmc,
.limited_pmc_event = p6_limited_pmc_event, .limited_pmc_event = p6_limited_pmc_event,
.flags = PPMU_LIMITED_PMC5_6 | PPMU_ALT_SIPR, .flags = PPMU_LIMITED_PMC5_6 | PPMU_ALT_SIPR,
.n_generic = ARRAY_SIZE(power6_generic_events), .n_generic = ARRAY_SIZE(power6_generic_events),
.generic_events = power6_generic_events, .generic_events = power6_generic_events,
.cache_events = &power6_cache_events, .cache_events = &power6_cache_events,
}; };
arch/powerpc/kernel/power7-pmu.c
View file @ 448d64f8
...@@ -71,10 +71,11 @@ ...@@ -71,10 +71,11 @@
* 0-9: Count of events needing PMC1..PMC5 * 0-9: Count of events needing PMC1..PMC5
*/ */
static int power7_get_constraint(u64 event, u64 *maskp, u64 *valp) static int power7_get_constraint(u64 event, unsigned long *maskp,
unsigned long *valp)
{ {
int pmc, sh; int pmc, sh;
u64 mask = 0, value = 0; unsigned long mask = 0, value = 0;
pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
if (pmc) { if (pmc) {
...@@ -224,10 +225,10 @@ static int power7_marked_instr_event(u64 event) ...@@ -224,10 +225,10 @@ static int power7_marked_instr_event(u64 event)
} }
static int power7_compute_mmcr(u64 event[], int n_ev, static int power7_compute_mmcr(u64 event[], int n_ev,
unsigned int hwc[], u64 mmcr[]) unsigned int hwc[], unsigned long mmcr[])
{ {
u64 mmcr1 = 0; unsigned long mmcr1 = 0;
u64 mmcra = 0; unsigned long mmcra = 0;
unsigned int pmc, unit, combine, l2sel, psel; unsigned int pmc, unit, combine, l2sel, psel;
unsigned int pmc_inuse = 0; unsigned int pmc_inuse = 0;
int i; int i;
...@@ -265,11 +266,14 @@ static int power7_compute_mmcr(u64 event[], int n_ev, ...@@ -265,11 +266,14 @@ static int power7_compute_mmcr(u64 event[], int n_ev,
--pmc; --pmc;
} }
if (pmc <= 3) { if (pmc <= 3) {
mmcr1 |= (u64) unit << (MMCR1_TTM0SEL_SH - 4 * pmc); mmcr1 |= (unsigned long) unit
mmcr1 |= (u64) combine << (MMCR1_PMC1_COMBINE_SH - pmc); << (MMCR1_TTM0SEL_SH - 4 * pmc);
mmcr1 |= (unsigned long) combine
<< (MMCR1_PMC1_COMBINE_SH - pmc);
mmcr1 |= psel << MMCR1_PMCSEL_SH(pmc); mmcr1 |= psel << MMCR1_PMCSEL_SH(pmc);
if (unit == 6) /* L2 events */ if (unit == 6) /* L2 events */
mmcr1 |= (u64) l2sel << MMCR1_L2SEL_SH; mmcr1 |= (unsigned long) l2sel
<< MMCR1_L2SEL_SH;
} }
if (power7_marked_instr_event(event[i])) if (power7_marked_instr_event(event[i]))
mmcra |= MMCRA_SAMPLE_ENABLE; mmcra |= MMCRA_SAMPLE_ENABLE;
...@@ -287,10 +291,10 @@ static int power7_compute_mmcr(u64 event[], int n_ev, ...@@ -287,10 +291,10 @@ static int power7_compute_mmcr(u64 event[], int n_ev,
return 0; return 0;
} }
static void power7_disable_pmc(unsigned int pmc, u64 mmcr[]) static void power7_disable_pmc(unsigned int pmc, unsigned long mmcr[])
{ {
if (pmc <= 3) if (pmc <= 3)
mmcr[1] &= ~(0xffULL << MMCR1_PMCSEL_SH(pmc)); mmcr[1] &= ~(0xffUL << MMCR1_PMCSEL_SH(pmc));
} }
static int power7_generic_events[] = { static int power7_generic_events[] = {
...@@ -343,15 +347,15 @@ static int power7_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { ...@@ -343,15 +347,15 @@ static int power7_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
}; };
struct power_pmu power7_pmu = { struct power_pmu power7_pmu = {
.n_counter = 6, .n_counter = 6,
.max_alternatives = MAX_ALT + 1, .max_alternatives = MAX_ALT + 1,
.add_fields = 0x1555ull, .add_fields = 0x1555ul,
.test_adder = 0x3000ull, .test_adder = 0x3000ul,
.compute_mmcr = power7_compute_mmcr, .compute_mmcr = power7_compute_mmcr,
.get_constraint = power7_get_constraint, .get_constraint = power7_get_constraint,
.get_alternatives = power7_get_alternatives, .get_alternatives = power7_get_alternatives,
.disable_pmc = power7_disable_pmc, .disable_pmc = power7_disable_pmc,
.n_generic = ARRAY_SIZE(power7_generic_events), .n_generic = ARRAY_SIZE(power7_generic_events),
.generic_events = power7_generic_events, .generic_events = power7_generic_events,
.cache_events = &power7_cache_events, .cache_events = &power7_cache_events,
}; };
arch/powerpc/kernel/ppc970-pmu.c
View file @ 448d64f8
...@@ -183,7 +183,7 @@ static int p970_marked_instr_event(u64 event) ...@@ -183,7 +183,7 @@ static int p970_marked_instr_event(u64 event)
} }
/* Masks and values for using events from the various units */ /* Masks and values for using events from the various units */
static u64 unit_cons[PM_LASTUNIT+1][2] = { static unsigned long unit_cons[PM_LASTUNIT+1][2] = {
[PM_FPU] = { 0xc80000000000ull, 0x040000000000ull }, [PM_FPU] = { 0xc80000000000ull, 0x040000000000ull },
[PM_VPU] = { 0xc80000000000ull, 0xc40000000000ull }, [PM_VPU] = { 0xc80000000000ull, 0xc40000000000ull },
[PM_ISU] = { 0x080000000000ull, 0x020000000000ull }, [PM_ISU] = { 0x080000000000ull, 0x020000000000ull },
...@@ -192,10 +192,11 @@ static u64 unit_cons[PM_LASTUNIT+1][2] = { ...@@ -192,10 +192,11 @@ static u64 unit_cons[PM_LASTUNIT+1][2] = {
[PM_STS] = { 0x380000000000ull, 0x310000000000ull }, [PM_STS] = { 0x380000000000ull, 0x310000000000ull },
}; };
static int p970_get_constraint(u64 event, u64 *maskp, u64 *valp) static int p970_get_constraint(u64 event, unsigned long *maskp,
unsigned long *valp)
{ {
int pmc, byte, unit, sh, spcsel; int pmc, byte, unit, sh, spcsel;
u64 mask = 0, value = 0; unsigned long mask = 0, value = 0;
int grp = -1; int grp = -1;
pmc = (event >> PM_PMC_SH) & PM_PMC_MSK; pmc = (event >> PM_PMC_SH) & PM_PMC_MSK;
...@@ -222,7 +223,7 @@ static int p970_get_constraint(u64 event, u64 *maskp, u64 *valp) ...@@ -222,7 +223,7 @@ static int p970_get_constraint(u64 event, u64 *maskp, u64 *valp)
grp = byte & 1; grp = byte & 1;
/* Set byte lane select field */ /* Set byte lane select field */
mask |= 0xfULL << (28 - 4 * byte); mask |= 0xfULL << (28 - 4 * byte);
value |= (u64)unit << (28 - 4 * byte); value |= (unsigned long)unit << (28 - 4 * byte);
} }
if (grp == 0) { if (grp == 0) {
/* increment PMC1/2/5/6 field */ /* increment PMC1/2/5/6 field */
...@@ -236,7 +237,7 @@ static int p970_get_constraint(u64 event, u64 *maskp, u64 *valp) ...@@ -236,7 +237,7 @@ static int p970_get_constraint(u64 event, u64 *maskp, u64 *valp)
spcsel = (event >> PM_SPCSEL_SH) & PM_SPCSEL_MSK; spcsel = (event >> PM_SPCSEL_SH) & PM_SPCSEL_MSK;
if (spcsel) { if (spcsel) {
mask |= 3ull << 48; mask |= 3ull << 48;
value |= (u64)spcsel << 48; value |= (unsigned long)spcsel << 48;
} }
*maskp = mask; *maskp = mask;
*valp = value; *valp = value;
...@@ -257,9 +258,9 @@ static int p970_get_alternatives(u64 event, unsigned int flags, u64 alt[]) ...@@ -257,9 +258,9 @@ static int p970_get_alternatives(u64 event, unsigned int flags, u64 alt[])
} }
static int p970_compute_mmcr(u64 event[], int n_ev, static int p970_compute_mmcr(u64 event[], int n_ev,
unsigned int hwc[], u64 mmcr[]) unsigned int hwc[], unsigned long mmcr[])
{ {
u64 mmcr0 = 0, mmcr1 = 0, mmcra = 0; unsigned long mmcr0 = 0, mmcr1 = 0, mmcra = 0;
unsigned int pmc, unit, byte, psel; unsigned int pmc, unit, byte, psel;
unsigned int ttm, grp; unsigned int ttm, grp;
unsigned int pmc_inuse = 0; unsigned int pmc_inuse = 0;
...@@ -320,7 +321,7 @@ static int p970_compute_mmcr(u64 event[], int n_ev, ...@@ -320,7 +321,7 @@ static int p970_compute_mmcr(u64 event[], int n_ev,
continue; continue;
ttm = unitmap[i]; ttm = unitmap[i];
++ttmuse[(ttm >> 2) & 1]; ++ttmuse[(ttm >> 2) & 1];
mmcr1 |= (u64)(ttm & ~4) << MMCR1_TTM1SEL_SH; mmcr1 |= (unsigned long)(ttm & ~4) << MMCR1_TTM1SEL_SH;
} }
/* Check only one unit per TTMx */ /* Check only one unit per TTMx */
if (ttmuse[0] > 1 || ttmuse[1] > 1) if (ttmuse[0] > 1 || ttmuse[1] > 1)
...@@ -340,7 +341,8 @@ static int p970_compute_mmcr(u64 event[], int n_ev, ...@@ -340,7 +341,8 @@ static int p970_compute_mmcr(u64 event[], int n_ev,
if (unit == PM_LSU1L && byte >= 2) if (unit == PM_LSU1L && byte >= 2)
mmcr1 |= 1ull << (MMCR1_TTM3SEL_SH + 3 - byte); mmcr1 |= 1ull << (MMCR1_TTM3SEL_SH + 3 - byte);
} }
mmcr1 |= (u64)ttm << (MMCR1_TD_CP_DBG0SEL_SH - 2 * byte); mmcr1 |= (unsigned long)ttm
<< (MMCR1_TD_CP_DBG0SEL_SH - 2 * byte);
} }
/* Second pass: assign PMCs, set PMCxSEL and PMCx_ADDER_SEL fields */ /* Second pass: assign PMCs, set PMCxSEL and PMCx_ADDER_SEL fields */
...@@ -386,7 +388,8 @@ static int p970_compute_mmcr(u64 event[], int n_ev, ...@@ -386,7 +388,8 @@ static int p970_compute_mmcr(u64 event[], int n_ev,
for (pmc = 0; pmc < 2; ++pmc) for (pmc = 0; pmc < 2; ++pmc)
mmcr0 |= pmcsel[pmc] << (MMCR0_PMC1SEL_SH - 7 * pmc); mmcr0 |= pmcsel[pmc] << (MMCR0_PMC1SEL_SH - 7 * pmc);
for (; pmc < 8; ++pmc) for (; pmc < 8; ++pmc)
mmcr1 |= (u64)pmcsel[pmc] << (MMCR1_PMC3SEL_SH - 5 * (pmc - 2)); mmcr1 |= (unsigned long)pmcsel[pmc]
<< (MMCR1_PMC3SEL_SH - 5 * (pmc - 2));
if (pmc_inuse & 1) if (pmc_inuse & 1)
mmcr0 |= MMCR0_PMC1CE; mmcr0 |= MMCR0_PMC1CE;
if (pmc_inuse & 0xfe) if (pmc_inuse & 0xfe)
...@@ -401,7 +404,7 @@ static int p970_compute_mmcr(u64 event[], int n_ev, ...@@ -401,7 +404,7 @@ static int p970_compute_mmcr(u64 event[], int n_ev,
return 0; return 0;
} }
static void p970_disable_pmc(unsigned int pmc, u64 mmcr[]) static void p970_disable_pmc(unsigned int pmc, unsigned long mmcr[])
{ {
int shift, i; int shift, i;
...@@ -468,15 +471,15 @@ static int ppc970_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = { ...@@ -468,15 +471,15 @@ static int ppc970_cache_events[C(MAX)][C(OP_MAX)][C(RESULT_MAX)] = {
}; };
struct power_pmu ppc970_pmu = { struct power_pmu ppc970_pmu = {
.n_counter = 8, .n_counter = 8,
.max_alternatives = 2, .max_alternatives = 2,
.add_fields = 0x001100005555ull, .add_fields = 0x001100005555ull,
.test_adder = 0x013300000000ull, .test_adder = 0x013300000000ull,
.compute_mmcr = p970_compute_mmcr, .compute_mmcr = p970_compute_mmcr,
.get_constraint = p970_get_constraint, .get_constraint = p970_get_constraint,
.get_alternatives = p970_get_alternatives, .get_alternatives = p970_get_alternatives,
.disable_pmc = p970_disable_pmc, .disable_pmc = p970_disable_pmc,
.n_generic = ARRAY_SIZE(ppc970_generic_events), .n_generic = ARRAY_SIZE(ppc970_generic_events),
.generic_events = ppc970_generic_events, .generic_events = ppc970_generic_events,
.cache_events = &ppc970_cache_events, .cache_events = &ppc970_cache_events,
}; };
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