Commit 44a66fd5 authored by Russell King's avatar Russell King

[ARM] Select decompressor mmu handling based upon the architecture IDs.

parent af1371dc
...@@ -477,6 +477,12 @@ proc_types: ...@@ -477,6 +477,12 @@ proc_types:
@ b __arm6_cache_off @ b __arm6_cache_off
@ b __armv3_cache_flush @ b __armv3_cache_flush
.word 0x00000000 @ old ARM ID
.word 0x0000f000
mov pc, lr
mov pc, lr
mov pc, lr
.word 0x41007000 @ ARM7/710 .word 0x41007000 @ ARM7/710
.word 0xfff8fe00 .word 0xfff8fe00
b __arm7_cache_off b __arm7_cache_off
...@@ -489,6 +495,14 @@ proc_types: ...@@ -489,6 +495,14 @@ proc_types:
b __armv4_cache_off b __armv4_cache_off
mov pc, lr mov pc, lr
.word 0x00007000 @ ARM7 IDs
.word 0x0000f000
mov pc, lr
mov pc, lr
mov pc, lr
@ Everything from here on will be the new ID system.
.word 0x41129200 @ ARM920T .word 0x41129200 @ ARM920T
.word 0xff00fff0 .word 0xff00fff0
b __armv4_cache_on b __armv4_cache_on
...@@ -507,8 +521,16 @@ proc_types: ...@@ -507,8 +521,16 @@ proc_types:
b __armv4_cache_off b __armv4_cache_off
b __armv4_cache_flush b __armv4_cache_flush
.word 0x69050000 @ xscale @ These match on the architecture ID
.word 0xffff0000
.word 0x00050000 @ ARMv5TE
.word 0x000f0000
b __armv4_cache_on
b __armv4_cache_off
b __armv4_cache_flush
.word 0x00060000 @ ARMv5TEJ
.word 0x000f0000
b __armv4_cache_on b __armv4_cache_on
b __armv4_cache_off b __armv4_cache_off
b __armv4_cache_flush b __armv4_cache_flush
......
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