Commit 44e1e7ba authored by Chris Wilson's avatar Chris Wilson

drm/i915: Reorder media/render reset on g4x

Ville found a reference to WaMediaResetBeforeFullReset which we presume
means that we should simply do the media reset first.

References: https://bugs.freedesktop.org/show_bug.cgi?id=100942Suggested-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: default avatarMika Kuoppala <mika.kuoppala@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20170518204811.7408-2-chris@chris-wilson.co.uk
parent 9593a657
...@@ -1468,16 +1468,9 @@ static int g4x_do_reset(struct drm_i915_private *dev_priv, unsigned engine_mask) ...@@ -1468,16 +1468,9 @@ static int g4x_do_reset(struct drm_i915_private *dev_priv, unsigned engine_mask)
struct pci_dev *pdev = dev_priv->drm.pdev; struct pci_dev *pdev = dev_priv->drm.pdev;
int ret; int ret;
pci_write_config_byte(pdev, I915_GDRST,
GRDOM_RENDER | GRDOM_RESET_ENABLE);
ret = wait_for(g4x_reset_complete(pdev), 500);
if (ret) {
DRM_DEBUG_DRIVER("Wait for render reset failed\n");
goto out;
}
/* WaVcpClkGateDisableForMediaReset:ctg,elk */ /* WaVcpClkGateDisableForMediaReset:ctg,elk */
I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE); I915_WRITE(VDECCLK_GATE_D,
I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE);
POSTING_READ(VDECCLK_GATE_D); POSTING_READ(VDECCLK_GATE_D);
pci_write_config_byte(pdev, I915_GDRST, pci_write_config_byte(pdev, I915_GDRST,
...@@ -1485,14 +1478,24 @@ static int g4x_do_reset(struct drm_i915_private *dev_priv, unsigned engine_mask) ...@@ -1485,14 +1478,24 @@ static int g4x_do_reset(struct drm_i915_private *dev_priv, unsigned engine_mask)
ret = wait_for(g4x_reset_complete(pdev), 500); ret = wait_for(g4x_reset_complete(pdev), 500);
if (ret) { if (ret) {
DRM_DEBUG_DRIVER("Wait for media reset failed\n"); DRM_DEBUG_DRIVER("Wait for media reset failed\n");
goto out;
} }
/* WaVcpClkGateDisableForMediaReset:ctg,elk */ pci_write_config_byte(pdev, I915_GDRST,
I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE); GRDOM_RENDER | GRDOM_RESET_ENABLE);
POSTING_READ(VDECCLK_GATE_D); ret = wait_for(g4x_reset_complete(pdev), 500);
if (ret) {
DRM_DEBUG_DRIVER("Wait for render reset failed\n");
goto out;
}
out: out:
pci_write_config_byte(pdev, I915_GDRST, 0); pci_write_config_byte(pdev, I915_GDRST, 0);
I915_WRITE(VDECCLK_GATE_D,
I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE);
POSTING_READ(VDECCLK_GATE_D);
return ret; return ret;
} }
......
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