Commit 44ef2bf7 authored by Dave Jiang's avatar Dave Jiang Committed by James Bottomley

[SCSI] isci: Fix interrupt coalescing assumption of active TCs

We always assign a dummy task context to a port in order to address a
silicon issue. We have 4 ports per controller. So when idle, there are always
exactly 4 TCs "active". The adaptive interrupt coalescing code uses number of
active TCs to figure out the coalescing values. However, we never hit "0" TCs
because of the 4 dummy TCs. Putting in fix so that we calculate this correctly.
Reported-by: default avatarDan Melnic <dan@seamicro.com>
Signed-off-by: default avatarDave Jiang <dave.jiang@intel.com>
Signed-off-by: default avatarJames Bottomley <JBottomley@Parallels.com>
parent 54b46677
...@@ -1122,10 +1122,16 @@ void isci_host_completion_routine(unsigned long data) ...@@ -1122,10 +1122,16 @@ void isci_host_completion_routine(unsigned long data)
sci_controller_completion_handler(ihost); sci_controller_completion_handler(ihost);
spin_unlock_irq(&ihost->scic_lock); spin_unlock_irq(&ihost->scic_lock);
/* the coalesence timeout doubles at each encoding step, so /*
* we subtract SCI_MAX_PORTS to account for the number of dummy TCs
* issued for hardware issue workaround
*/
active = isci_tci_active(ihost) - SCI_MAX_PORTS;
/*
* the coalesence timeout doubles at each encoding step, so
* update it based on the ilog2 value of the outstanding requests * update it based on the ilog2 value of the outstanding requests
*/ */
active = isci_tci_active(ihost);
writel(SMU_ICC_GEN_VAL(NUMBER, active) | writel(SMU_ICC_GEN_VAL(NUMBER, active) |
SMU_ICC_GEN_VAL(TIMER, ISCI_COALESCE_BASE + ilog2(active)), SMU_ICC_GEN_VAL(TIMER, ISCI_COALESCE_BASE + ilog2(active)),
&ihost->smu_registers->interrupt_coalesce_control); &ihost->smu_registers->interrupt_coalesce_control);
......
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