Commit 44ff0ae6 authored by Alex Deucher's avatar Alex Deucher

drm/amdgpu/powerplay: FEATURE_MASK is 64 bit so use ULL

ULL is needed for 32 bit arches.
Reviewed-by: default avatarNicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent d7929c1e
...@@ -37,7 +37,7 @@ ...@@ -37,7 +37,7 @@
#include "asic_reg/mp/mp_11_0_sh_mask.h" #include "asic_reg/mp/mp_11_0_sh_mask.h"
#define FEATURE_MASK(feature) (1UL << feature) #define FEATURE_MASK(feature) (1ULL << feature)
#define SMC_DPM_FEATURE ( \ #define SMC_DPM_FEATURE ( \
FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \ FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \ FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \
......
...@@ -576,7 +576,7 @@ static int vega20_run_btc_afll(struct smu_context *smu) ...@@ -576,7 +576,7 @@ static int vega20_run_btc_afll(struct smu_context *smu)
return smu_send_smc_msg(smu, SMU_MSG_RunAfllBtc); return smu_send_smc_msg(smu, SMU_MSG_RunAfllBtc);
} }
#define FEATURE_MASK(feature) (1UL << feature) #define FEATURE_MASK(feature) (1ULL << feature)
static int static int
vega20_get_allowed_feature_mask(struct smu_context *smu, vega20_get_allowed_feature_mask(struct smu_context *smu,
uint32_t *feature_mask, uint32_t num) uint32_t *feature_mask, uint32_t num)
......
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