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Commit 467cbd20 authored by Linus Torvalds's avatar Linus Torvalds
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Merge branch 'x86-nuke-platforms-for-linus' of... 

Merge branch 'x86-nuke-platforms-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull x86 old platform removal from Peter Anvin:
 "This patchset removes support for several completely obsolete
  platforms, where the maintainers either have completely vanished or
  acked the removal.  For some of them it is questionable if there even
  exists functional specimens of the hardware"

Geert Uytterhoeven apparently thought this was a April Fool's pull request ;)

* 'x86-nuke-platforms-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86, platforms: Remove NUMAQ
  x86, platforms: Remove SGI Visual Workstation
  x86, apic: Remove support for IBM Summit/EXA chipset
  x86, apic: Remove support for ia32-based Unisys ES7000
parents 7125764c b5660ba7
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Documentation/00-INDEX
View file @ 467cbd20
......@@ -413,8 +413,6 @@ serial-console.txt
- how to set up Linux with a serial line console as the default.
sgi-ioc4.txt
- description of the SGI IOC4 PCI (multi function) device.
sgi-visws.txt
- short blurb on the SGI Visual Workstations.
sh/
- directory with info on porting Linux to a new architecture.
smsc_ece1099.txt
......
Documentation/sgi-visws.txt deleted 100644 → 0
View file @ 7125764c
The SGI Visual Workstations (models 320 and 540) are based around
the Cobalt, Lithium, and Arsenic ASICs. The Cobalt ASIC is the
main system ASIC which interfaces the 1-4 IA32 cpus, the memory
system, and the I/O system in the Lithium ASIC. The Cobalt ASIC
also contains the 3D gfx rendering engine which renders to main
system memory -- part of which is used as the frame buffer which
is DMA'ed to a video connector using the Arsenic ASIC. A PIIX4
chip and NS87307 are used to provide legacy device support (IDE,
serial, floppy, and parallel).
The Visual Workstation chipset largely conforms to the PC architecture
with some notable exceptions such as interrupt handling.
Documentation/sound/oss/vwsnd deleted 100644 → 0
View file @ 7125764c
This diff is collapsed.
MAINTAINERS
View file @ 467cbd20
......@@ -7840,13 +7840,6 @@ F: Documentation/ia64/serial.txt
F: drivers/tty/serial/ioc?_serial.c
F: include/linux/ioc?.h
SGI VISUAL WORKSTATION 320 AND 540
M: Andrey Panin <pazke@donpac.ru>
L: linux-visws-devel@lists.sf.net
W: http://linux-visws.sf.net
S: Maintained for 2.6.
F: Documentation/sgi-visws.txt
SGI XP/XPC/XPNET DRIVER
M: Cliff Whickman <cpw@sgi.com>
M: Robin Holt <robinmholt@gmail.com>
......
arch/x86/Kconfig
View file @ 467cbd20
......@@ -344,12 +344,9 @@ config X86_EXTENDED_PLATFORM
for the following (non-PC) 32 bit x86 platforms:
Goldfish (Android emulator)
AMD Elan
NUMAQ (IBM/Sequent)
RDC R-321x SoC
SGI 320/540 (Visual Workstation)
STA2X11-based (e.g. Northville)
Summit/EXA (IBM x440)
Unisys ES7000 IA32 series
Moorestown MID devices
If you have one of these systems, or if you want to build a
......@@ -487,49 +484,22 @@ config X86_32_NON_STANDARD
depends on X86_32 && SMP
depends on X86_EXTENDED_PLATFORM
---help---
This option compiles in the NUMAQ, Summit, bigsmp, ES7000,
STA2X11, default subarchitectures. It is intended for a generic
binary kernel. If you select them all, kernel will probe it
one by one and will fallback to default.
This option compiles in the bigsmp and STA2X11 default
subarchitectures. It is intended for a generic binary
kernel. If you select them all, kernel will probe it one by
one and will fallback to default.
# Alphabetically sorted list of Non standard 32 bit platforms
config X86_NUMAQ
bool "NUMAQ (IBM/Sequent)"
depends on X86_32_NON_STANDARD
depends on PCI
select NUMA
select X86_MPPARSE
---help---
This option is used for getting Linux to run on a NUMAQ (IBM/Sequent)
NUMA multiquad box. This changes the way that processors are
bootstrapped, and uses Clustered Logical APIC addressing mode instead
of Flat Logical. You will need a new lynxer.elf file to flash your
firmware with - send email to <Martin.Bligh@us.ibm.com>.
config X86_SUPPORTS_MEMORY_FAILURE
def_bool y
# MCE code calls memory_failure():
depends on X86_MCE
# On 32-bit this adds too big of NODES_SHIFT and we run out of page flags:
depends on !X86_NUMAQ
# On 32-bit SPARSEMEM adds too big of SECTIONS_WIDTH:
depends on X86_64 || !SPARSEMEM
select ARCH_SUPPORTS_MEMORY_FAILURE
config X86_VISWS
bool "SGI 320/540 (Visual Workstation)"
depends on X86_32 && PCI && X86_MPPARSE && PCI_GODIRECT
depends on X86_32_NON_STANDARD
---help---
The SGI Visual Workstation series is an IA32-based workstation
based on SGI systems chips with some legacy PC hardware attached.
Say Y here to create a kernel to run on the SGI 320 or 540.
A kernel compiled for the Visual Workstation will run on general
PCs as well. See <file:Documentation/sgi-visws.txt> for details.
config STA2X11
bool "STA2X11 Companion Chip Support"
depends on X86_32_NON_STANDARD && PCI
......@@ -546,20 +516,6 @@ config STA2X11
option is selected the kernel will still be able to boot on
standard PC machines.
config X86_SUMMIT
bool "Summit/EXA (IBM x440)"
depends on X86_32_NON_STANDARD
---help---
This option is needed for IBM systems that use the Summit/EXA chipset.
In particular, it is needed for the x440.
config X86_ES7000
bool "Unisys ES7000 IA32 series"
depends on X86_32_NON_STANDARD && X86_BIGSMP
---help---
Support for Unisys ES7000 systems. Say 'Y' here if this kernel is
supposed to run on an IA32-based Unisys ES7000 system.
config X86_32_IRIS
tristate "Eurobraille/Iris poweroff module"
depends on X86_32
......@@ -682,14 +638,6 @@ config MEMTEST
memtest=4, mean do 4 test patterns.
If you are unsure how to answer this question, answer N.
config X86_SUMMIT_NUMA
def_bool y
depends on X86_32 && NUMA && X86_32_NON_STANDARD
config X86_CYCLONE_TIMER
def_bool y
depends on X86_SUMMIT
source "arch/x86/Kconfig.cpu"
config HPET_TIMER
......@@ -818,7 +766,7 @@ config NR_CPUS
range 2 8192 if SMP && !MAXSMP && CPUMASK_OFFSTACK && X86_64
default "1" if !SMP
default "8192" if MAXSMP
default "32" if SMP && (X86_NUMAQ || X86_SUMMIT || X86_BIGSMP || X86_ES7000)
default "32" if SMP && X86_BIGSMP
default "8" if SMP
---help---
This allows you to specify the maximum number of CPUs which this
......@@ -882,10 +830,6 @@ config X86_IO_APIC
def_bool y
depends on X86_64 || SMP || X86_32_NON_STANDARD || X86_UP_IOAPIC || PCI_MSI
config X86_VISWS_APIC
def_bool y
depends on X86_32 && X86_VISWS
config X86_REROUTE_FOR_BROKEN_BOOT_IRQS
bool "Reroute for broken boot IRQs"
depends on X86_IO_APIC
......@@ -1103,13 +1047,11 @@ config X86_CPUID
choice
prompt "High Memory Support"
default HIGHMEM64G if X86_NUMAQ
default HIGHMEM4G
depends on X86_32
config NOHIGHMEM
bool "off"
depends on !X86_NUMAQ
---help---
Linux can use up to 64 Gigabytes of physical memory on x86 systems.
However, the address space of 32-bit x86 processors is only 4
......@@ -1146,7 +1088,6 @@ config NOHIGHMEM
config HIGHMEM4G
bool "4GB"
depends on !X86_NUMAQ
---help---
Select this if you have a 32-bit processor and between 1 and 4
gigabytes of physical RAM.
......@@ -1238,8 +1179,8 @@ config DIRECT_GBPAGES
config NUMA
bool "Numa Memory Allocation and Scheduler Support"
depends on SMP
depends on X86_64 || (X86_32 && HIGHMEM64G && (X86_NUMAQ || X86_BIGSMP || X86_SUMMIT && ACPI))
default y if (X86_NUMAQ || X86_SUMMIT || X86_BIGSMP)
depends on X86_64 || (X86_32 && HIGHMEM64G && X86_BIGSMP)
default y if X86_BIGSMP
---help---
Enable NUMA (Non Uniform Memory Access) support.
......@@ -1250,15 +1191,11 @@ config NUMA
For 64-bit this is recommended if the system is Intel Core i7
(or later), AMD Opteron, or EM64T NUMA.
For 32-bit this is only needed on (rare) 32-bit-only platforms
that support NUMA topologies, such as NUMAQ / Summit, or if you
boot a 32-bit kernel on a 64-bit NUMA platform.
For 32-bit this is only needed if you boot a 32-bit
kernel on a 64-bit NUMA platform.
Otherwise, you should say N.
comment "NUMA (Summit) requires SMP, 64GB highmem support, ACPI"
depends on X86_32 && X86_SUMMIT && (!HIGHMEM64G || !ACPI)
config AMD_NUMA
def_bool y
prompt "Old style AMD Opteron NUMA detection"
......@@ -1300,7 +1237,6 @@ config NODES_SHIFT
range 1 10
default "10" if MAXSMP
default "6" if X86_64
default "4" if X86_NUMAQ
default "3"
depends on NEED_MULTIPLE_NODES
---help---
......
arch/x86/Kconfig.cpu
View file @ 467cbd20
......@@ -359,7 +359,7 @@ config X86_P6_NOP
config X86_TSC
def_bool y
depends on ((MWINCHIP3D || MCRUSOE || MEFFICEON || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || MK8 || MVIAC3_2 || MVIAC7 || MGEODEGX1 || MGEODE_LX || MCORE2 || MATOM) && !X86_NUMAQ) || X86_64
depends on (MWINCHIP3D || MCRUSOE || MEFFICEON || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || MK8 || MVIAC3_2 || MVIAC7 || MGEODEGX1 || MGEODE_LX || MCORE2 || MATOM) || X86_64
config X86_CMPXCHG64
def_bool y
......
arch/x86/include/asm/fixmap.h
View file @ 467cbd20
......@@ -89,12 +89,6 @@ enum fixed_addresses {
#ifdef CONFIG_X86_IO_APIC
FIX_IO_APIC_BASE_0,
FIX_IO_APIC_BASE_END = FIX_IO_APIC_BASE_0 + MAX_IO_APICS - 1,
#endif
#ifdef CONFIG_X86_VISWS_APIC
FIX_CO_CPU, /* Cobalt timer */
FIX_CO_APIC, /* Cobalt APIC Redirection Table */
FIX_LI_PCIA, /* Lithium PCI Bridge A */
FIX_LI_PCIB, /* Lithium PCI Bridge B */
#endif
FIX_RO_IDT, /* Virtual mapping for read-only IDT */
#ifdef CONFIG_X86_32
......
arch/x86/include/asm/hw_irq.h
View file @ 467cbd20
......@@ -98,7 +98,6 @@ extern void trace_call_function_single_interrupt(void);
#define IO_APIC_IRQ(x) (((x) >= NR_IRQS_LEGACY) || ((1<<(x)) & io_apic_irqs))
extern unsigned long io_apic_irqs;
extern void init_VISWS_APIC_irqs(void);
extern void setup_IO_APIC(void);
extern void disable_IO_APIC(void);
......
arch/x86/include/asm/mmzone_32.h
View file @ 467cbd20
......@@ -11,9 +11,6 @@
#ifdef CONFIG_NUMA
extern struct pglist_data *node_data[];
#define NODE_DATA(nid) (node_data[nid])
#include <asm/numaq.h>
#endif /* CONFIG_NUMA */
#ifdef CONFIG_DISCONTIGMEM
......
arch/x86/include/asm/mpspec.h
View file @ 467cbd20
......@@ -25,12 +25,6 @@ extern int pic_mode;
extern unsigned int def_to_bigsmp;
#ifdef CONFIG_X86_NUMAQ
extern int mp_bus_id_to_node[MAX_MP_BUSSES];
extern int mp_bus_id_to_local[MAX_MP_BUSSES];
extern int quad_local_to_mp_bus_id [NR_CPUS/4][4];
#endif
#else /* CONFIG_X86_64: */
#define MAX_MP_BUSSES 256
......
arch/x86/include/asm/numaq.h deleted 100644 → 0
View file @ 7125764c
/*
* Written by: Patricia Gaughen, IBM Corporation
*
* Copyright (C) 2002, IBM Corp.
*
* All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
* NON INFRINGEMENT. See the GNU General Public License for more
* details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*
* Send feedback to <gone@us.ibm.com>
*/
#ifndef _ASM_X86_NUMAQ_H
#define _ASM_X86_NUMAQ_H
#ifdef CONFIG_X86_NUMAQ
extern int found_numaq;
extern int numaq_numa_init(void);
extern int pci_numaq_init(void);
extern void *xquad_portio;
#define XQUAD_PORTIO_BASE 0xfe400000
#define XQUAD_PORTIO_QUAD 0x40000 /* 256k per quad. */
#define XQUAD_PORT_ADDR(port, quad) (xquad_portio + (XQUAD_PORTIO_QUAD*quad) + port)
/*
* SYS_CFG_DATA_PRIV_ADDR, struct eachquadmem, and struct sys_cfg_data are the
*/
#define SYS_CFG_DATA_PRIV_ADDR 0x0009d000 /* place for scd in private
quad space */
/*
* Communication area for each processor on lynxer-processor tests.
*
* NOTE: If you change the size of this eachproc structure you need
* to change the definition for EACH_QUAD_SIZE.
*/
struct eachquadmem {
unsigned int priv_mem_start; /* Starting address of this */
/* quad's private memory. */
/* This is always 0. */
/* In MB. */
unsigned int priv_mem_size; /* Size of this quad's */
/* private memory. */
/* In MB. */
unsigned int low_shrd_mem_strp_start;/* Starting address of this */
/* quad's low shared block */
/* (untranslated). */
/* In MB. */
unsigned int low_shrd_mem_start; /* Starting address of this */
/* quad's low shared memory */
/* (untranslated). */
/* In MB. */
unsigned int low_shrd_mem_size; /* Size of this quad's low */
/* shared memory. */
/* In MB. */
unsigned int lmmio_copb_start; /* Starting address of this */
/* quad's local memory */
/* mapped I/O in the */
/* compatibility OPB. */
/* In MB. */
unsigned int lmmio_copb_size; /* Size of this quad's local */
/* memory mapped I/O in the */
/* compatibility OPB. */
/* In MB. */
unsigned int lmmio_nopb_start; /* Starting address of this */
/* quad's local memory */
/* mapped I/O in the */
/* non-compatibility OPB. */
/* In MB. */
unsigned int lmmio_nopb_size; /* Size of this quad's local */
/* memory mapped I/O in the */
/* non-compatibility OPB. */
/* In MB. */
unsigned int io_apic_0_start; /* Starting address of I/O */
/* APIC 0. */
unsigned int io_apic_0_sz; /* Size I/O APIC 0. */
unsigned int io_apic_1_start; /* Starting address of I/O */
/* APIC 1. */
unsigned int io_apic_1_sz; /* Size I/O APIC 1. */
unsigned int hi_shrd_mem_start; /* Starting address of this */
/* quad's high shared memory.*/
/* In MB. */
unsigned int hi_shrd_mem_size; /* Size of this quad's high */
/* shared memory. */
/* In MB. */
unsigned int mps_table_addr; /* Address of this quad's */
/* MPS tables from BIOS, */
/* in system space.*/
unsigned int lcl_MDC_pio_addr; /* Port-I/O address for */
/* local access of MDC. */
unsigned int rmt_MDC_mmpio_addr; /* MM-Port-I/O address for */
/* remote access of MDC. */
unsigned int mm_port_io_start; /* Starting address of this */
/* quad's memory mapped Port */
/* I/O space. */
unsigned int mm_port_io_size; /* Size of this quad's memory*/
/* mapped Port I/O space. */
unsigned int mm_rmt_io_apic_start; /* Starting address of this */
/* quad's memory mapped */
/* remote I/O APIC space. */
unsigned int mm_rmt_io_apic_size; /* Size of this quad's memory*/
/* mapped remote I/O APIC */
/* space. */
unsigned int mm_isa_start; /* Starting address of this */
/* quad's memory mapped ISA */
/* space (contains MDC */
/* memory space). */
unsigned int mm_isa_size; /* Size of this quad's memory*/
/* mapped ISA space (contains*/
/* MDC memory space). */
unsigned int rmt_qmi_addr; /* Remote addr to access QMI.*/
unsigned int lcl_qmi_addr; /* Local addr to access QMI. */
};
/*
* Note: This structure must be NOT be changed unless the multiproc and
* OS are changed to reflect the new structure.
*/
struct sys_cfg_data {
unsigned int quad_id;
unsigned int bsp_proc_id; /* Boot Strap Processor in this quad. */
unsigned int scd_version; /* Version number of this table. */
unsigned int first_quad_id;
unsigned int quads_present31_0; /* 1 bit for each quad */
unsigned int quads_present63_32; /* 1 bit for each quad */
unsigned int config_flags;
unsigned int boot_flags;
unsigned int csr_start_addr; /* Absolute value (not in MB) */
unsigned int csr_size; /* Absolute value (not in MB) */
unsigned int lcl_apic_start_addr; /* Absolute value (not in MB) */
unsigned int lcl_apic_size; /* Absolute value (not in MB) */
unsigned int low_shrd_mem_base; /* 0 or 512MB or 1GB */
unsigned int low_shrd_mem_quad_offset; /* 0,128M,256M,512M,1G */
/* may not be totally populated */
unsigned int split_mem_enbl; /* 0 for no low shared memory */
unsigned int mmio_sz; /* Size of total system memory mapped I/O */
/* (in MB). */
unsigned int quad_spin_lock; /* Spare location used for quad */
/* bringup. */
unsigned int nonzero55; /* For checksumming. */
unsigned int nonzeroaa; /* For checksumming. */
unsigned int scd_magic_number;
unsigned int system_type;
unsigned int checksum;
/*
* memory configuration area for each quad
*/
struct eachquadmem eq[MAX_NUMNODES]; /* indexed by quad id */
};
void numaq_tsc_disable(void);
#endif /* CONFIG_X86_NUMAQ */
#endif /* _ASM_X86_NUMAQ_H */
arch/x86/include/asm/setup.h
View file @ 467cbd20
......@@ -39,12 +39,6 @@ static inline void vsmp_init(void) { }
void setup_bios_corruption_check(void);
#ifdef CONFIG_X86_VISWS
extern void visws_early_detect(void);
#else
static inline void visws_early_detect(void) { }
#endif
extern unsigned long saved_video_mode;
extern void reserve_standard_io_resources(void);
......
arch/x86/include/asm/visws/cobalt.h deleted 100644 → 0
View file @ 7125764c
#ifndef _ASM_X86_VISWS_COBALT_H
#define _ASM_X86_VISWS_COBALT_H
#include <asm/fixmap.h>
/*
* Cobalt SGI Visual Workstation system ASIC
*/
#define CO_CPU_NUM_PHYS 0x1e00
#define CO_CPU_TAB_PHYS (CO_CPU_NUM_PHYS + 2)
#define CO_CPU_MAX 4
#define CO_CPU_PHYS 0xc2000000
#define CO_APIC_PHYS 0xc4000000
/* see set_fixmap() and asm/fixmap.h */
#define CO_CPU_VADDR (fix_to_virt(FIX_CO_CPU))
#define CO_APIC_VADDR (fix_to_virt(FIX_CO_APIC))
/* Cobalt CPU registers -- relative to CO_CPU_VADDR, use co_cpu_*() */
#define CO_CPU_REV 0x08
#define CO_CPU_CTRL 0x10
#define CO_CPU_STAT 0x20
#define CO_CPU_TIMEVAL 0x30
/* CO_CPU_CTRL bits */
#define CO_CTRL_TIMERUN 0x04 /* 0 == disabled */
#define CO_CTRL_TIMEMASK 0x08 /* 0 == unmasked */
/* CO_CPU_STATUS bits */
#define CO_STAT_TIMEINTR 0x02 /* (r) 1 == int pend, (w) 0 == clear */
/* CO_CPU_TIMEVAL value */
#define CO_TIME_HZ 100000000 /* Cobalt core rate */
/* Cobalt APIC registers -- relative to CO_APIC_VADDR, use co_apic_*() */
#define CO_APIC_HI(n) (((n) * 0x10) + 4)
#define CO_APIC_LO(n) ((n) * 0x10)
#define CO_APIC_ID 0x0ffc
/* CO_APIC_ID bits */
#define CO_APIC_ENABLE 0x00000100
/* CO_APIC_LO bits */
#define CO_APIC_MASK 0x00010000 /* 0 = enabled */
#define CO_APIC_LEVEL 0x00008000 /* 0 = edge */
/*
* Where things are physically wired to Cobalt
* #defines with no board _<type>_<rev>_ are common to all (thus far)
*/
#define CO_APIC_IDE0 4
#define CO_APIC_IDE1 2 /* Only on 320 */
#define CO_APIC_8259 12 /* serial, floppy, par-l-l */
/* Lithium PCI Bridge A -- "the one with 82557 Ethernet" */
#define CO_APIC_PCIA_BASE0 0 /* and 1 */ /* slot 0, line 0 */
#define CO_APIC_PCIA_BASE123 5 /* and 6 */ /* slot 0, line 1 */
#define CO_APIC_PIIX4_USB 7 /* this one is weird */
/* Lithium PCI Bridge B -- "the one with PIIX4" */
#define CO_APIC_PCIB_BASE0 8 /* and 9-12 *//* slot 0, line 0 */
#define CO_APIC_PCIB_BASE123 13 /* 14.15 */ /* slot 0, line 1 */
#define CO_APIC_VIDOUT0 16
#define CO_APIC_VIDOUT1 17
#define CO_APIC_VIDIN0 18
#define CO_APIC_VIDIN1 19
#define CO_APIC_LI_AUDIO 22
#define CO_APIC_AS 24
#define CO_APIC_RE 25
#define CO_APIC_CPU 28 /* Timer and Cache interrupt */
#define CO_APIC_NMI 29
#define CO_APIC_LAST CO_APIC_NMI
/*
* This is how irqs are assigned on the Visual Workstation.
* Legacy devices get irq's 1-15 (system clock is 0 and is CO_APIC_CPU).
* All other devices (including PCI) go to Cobalt and are irq's 16 on up.
*/
#define CO_IRQ_APIC0 16 /* irq of apic entry 0 */
#define IS_CO_APIC(irq) ((irq) >= CO_IRQ_APIC0)
#define CO_IRQ(apic) (CO_IRQ_APIC0 + (apic)) /* apic ent to irq */
#define CO_APIC(irq) ((irq) - CO_IRQ_APIC0) /* irq to apic ent */
#define CO_IRQ_IDE0 14 /* knowledge of... */
#define CO_IRQ_IDE1 15 /* ... ide driver defaults! */
#define CO_IRQ_8259 CO_IRQ(CO_APIC_8259)
#ifdef CONFIG_X86_VISWS_APIC
static inline void co_cpu_write(unsigned long reg, unsigned long v)
{
*((volatile unsigned long *)(CO_CPU_VADDR+reg))=v;
}
static inline unsigned long co_cpu_read(unsigned long reg)
{
return *((volatile unsigned long *)(CO_CPU_VADDR+reg));
}
static inline void co_apic_write(unsigned long reg, unsigned long v)
{
*((volatile unsigned long *)(CO_APIC_VADDR+reg))=v;
}
static inline unsigned long co_apic_read(unsigned long reg)
{
return *((volatile unsigned long *)(CO_APIC_VADDR+reg));
}
#endif
extern char visws_board_type;
#define VISWS_320 0
#define VISWS_540 1
extern char visws_board_rev;
extern int pci_visws_init(void);
#endif /* _ASM_X86_VISWS_COBALT_H */
arch/x86/include/asm/visws/lithium.h deleted 100644 → 0
View file @ 7125764c
#ifndef _ASM_X86_VISWS_LITHIUM_H
#define _ASM_X86_VISWS_LITHIUM_H
#include <asm/fixmap.h>
/*
* Lithium is the SGI Visual Workstation I/O ASIC
*/
#define LI_PCI_A_PHYS 0xfc000000 /* Enet is dev 3 */
#define LI_PCI_B_PHYS 0xfd000000 /* PIIX4 is here */
/* see set_fixmap() and asm/fixmap.h */
#define LI_PCIA_VADDR (fix_to_virt(FIX_LI_PCIA))
#define LI_PCIB_VADDR (fix_to_virt(FIX_LI_PCIB))
/* Not a standard PCI? (not in linux/pci.h) */
#define LI_PCI_BUSNUM 0x44 /* lo8: primary, hi8: sub */
#define LI_PCI_INTEN 0x46
/* LI_PCI_INTENT bits */
#define LI_INTA_0 0x0001
#define LI_INTA_1 0x0002
#define LI_INTA_2 0x0004
#define LI_INTA_3 0x0008
#define LI_INTA_4 0x0010
#define LI_INTB 0x0020
#define LI_INTC 0x0040
#define LI_INTD 0x0080
/* More special purpose macros... */
static inline void li_pcia_write16(unsigned long reg, unsigned short v)
{
*((volatile unsigned short *)(LI_PCIA_VADDR+reg))=v;
}
static inline unsigned short li_pcia_read16(unsigned long reg)
{
return *((volatile unsigned short *)(LI_PCIA_VADDR+reg));
}
static inline void li_pcib_write16(unsigned long reg, unsigned short v)
{
*((volatile unsigned short *)(LI_PCIB_VADDR+reg))=v;
}
static inline unsigned short li_pcib_read16(unsigned long reg)
{
return *((volatile unsigned short *)(LI_PCIB_VADDR+reg));
}
#endif /* _ASM_X86_VISWS_LITHIUM_H */
arch/x86/include/asm/visws/piix4.h deleted 100644 → 0
View file @ 7125764c
#ifndef _ASM_X86_VISWS_PIIX4_H
#define _ASM_X86_VISWS_PIIX4_H
/*
* PIIX4 as used on SGI Visual Workstations
*/
#define PIIX_PM_START 0x0F80
#define SIO_GPIO_START 0x0FC0
#define SIO_PM_START 0x0FC8
#define PMBASE PIIX_PM_START
#define GPIREG0 (PMBASE+0x30)
#define GPIREG(x) (GPIREG0+((x)/8))
#define GPIBIT(x) (1 << ((x)%8))
#define PIIX_GPI_BD_ID1 18
#define PIIX_GPI_BD_ID2 19
#define PIIX_GPI_BD_ID3 20
#define PIIX_GPI_BD_ID4 21
#define PIIX_GPI_BD_REG GPIREG(PIIX_GPI_BD_ID1)
#define PIIX_GPI_BD_MASK (GPIBIT(PIIX_GPI_BD_ID1) | \
GPIBIT(PIIX_GPI_BD_ID2) | \
GPIBIT(PIIX_GPI_BD_ID3) | \
GPIBIT(PIIX_GPI_BD_ID4) )
#define PIIX_GPI_BD_SHIFT (PIIX_GPI_BD_ID1 % 8)
#define SIO_INDEX 0x2e
#define SIO_DATA 0x2f
#define SIO_DEV_SEL 0x7
#define SIO_DEV_ENB 0x30
#define SIO_DEV_MSB 0x60
#define SIO_DEV_LSB 0x61
#define SIO_GP_DEV 0x7
#define SIO_GP_BASE SIO_GPIO_START
#define SIO_GP_MSB (SIO_GP_BASE>>8)
#define SIO_GP_LSB (SIO_GP_BASE&0xff)
#define SIO_GP_DATA1 (SIO_GP_BASE+0)
#define SIO_PM_DEV 0x8
#define SIO_PM_BASE SIO_PM_START
#define SIO_PM_MSB (SIO_PM_BASE>>8)
#define SIO_PM_LSB (SIO_PM_BASE&0xff)
#define SIO_PM_INDEX (SIO_PM_BASE+0)
#define SIO_PM_DATA (SIO_PM_BASE+1)
#define SIO_PM_FER2 0x1
#define SIO_PM_GP_EN 0x80
/*
* This is the dev/reg where generating a config cycle will
* result in a PCI special cycle.
*/
#define SPECIAL_DEV 0xff
#define SPECIAL_REG 0x00
/*
* PIIX4 needs to see a special cycle with the following data
* to be convinced the processor has gone into the stop grant
* state. PIIX4 insists on seeing this before it will power
* down a system.
*/
#define PIIX_SPECIAL_STOP 0x00120002
#define PIIX4_RESET_PORT 0xcf9
#define PIIX4_RESET_VAL 0x6
#define PMSTS_PORT 0xf80 // 2 bytes PM Status
#define PMEN_PORT 0xf82 // 2 bytes PM Enable
#define PMCNTRL_PORT 0xf84 // 2 bytes PM Control
#define PM_SUSPEND_ENABLE 0x2000 // start sequence to suspend state
/*
* PMSTS and PMEN I/O bit definitions.
* (Bits are the same in both registers)
*/
#define PM_STS_RSM (1<<15) // Resume Status
#define PM_STS_PWRBTNOR (1<<11) // Power Button Override
#define PM_STS_RTC (1<<10) // RTC status
#define PM_STS_PWRBTN (1<<8) // Power Button Pressed?
#define PM_STS_GBL (1<<5) // Global Status
#define PM_STS_BM (1<<4) // Bus Master Status
#define PM_STS_TMROF (1<<0) // Timer Overflow Status.
/*
* Stop clock GPI register
*/
#define PIIX_GPIREG0 (0xf80 + 0x30)
/*
* Stop clock GPI bit in GPIREG0
*/
#define PIIX_GPI_STPCLK 0x4 // STPCLK signal routed back in
#endif /* _ASM_X86_VISWS_PIIX4_H */
arch/x86/include/asm/visws/sgivw.h deleted 100644 → 0
View file @ 7125764c
/*
* Frame buffer position and size:
*/
extern unsigned long sgivwfb_mem_phys;
extern unsigned long sgivwfb_mem_size;
arch/x86/kernel/acpi/boot.c
View file @ 467cbd20
......@@ -903,10 +903,6 @@ static int __init acpi_parse_madt_lapic_entries(void)
#ifdef CONFIG_X86_IO_APIC
#define MP_ISA_BUS 0
#ifdef CONFIG_X86_ES7000
extern int es7000_plat;
#endif
void __init mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, u32 gsi)
{
int ioapic;
......@@ -956,14 +952,6 @@ void __init mp_config_acpi_legacy_irqs(void)
set_bit(MP_ISA_BUS, mp_bus_not_pci);
pr_debug("Bus #%d is ISA\n", MP_ISA_BUS);
#ifdef CONFIG_X86_ES7000
/*
* Older generations of ES7000 have no legacy identity mappings
*/
if (es7000_plat == 1)
return;
#endif
/*
* Use the default configuration for the IRQs 0-15. Unless
* overridden by (MADT) interrupt source override entries.
......
arch/x86/kernel/apic/Makefile
View file @ 467cbd20
......@@ -18,10 +18,7 @@ obj-y += apic_flat_64.o
endif
# APIC probe will depend on the listing order here
obj-$(CONFIG_X86_NUMAQ) += numaq_32.o
obj-$(CONFIG_X86_SUMMIT) += summit_32.o
obj-$(CONFIG_X86_BIGSMP) += bigsmp_32.o
obj-$(CONFIG_X86_ES7000) += es7000_32.o
# For 32bit, probe_32 need to be listed last
obj-$(CONFIG_X86_LOCAL_APIC) += probe_$(BITS).o
arch/x86/kernel/apic/apic.c
View file @ 467cbd20
......@@ -2136,7 +2136,6 @@ int generic_processor_info(int apicid, int version)
*
* - arch/x86/kernel/mpparse.c: MP_processor_info()
* - arch/x86/mm/amdtopology.c: amd_numa_init()
* - arch/x86/platform/visws/visws_quirks.c: MP_processor_info()
*
* This function is executed with the modified
* boot_cpu_physical_apicid. So, disabled_cpu_apicid kernel
......
arch/x86/kernel/apic/es7000_32.c deleted 100644 → 0
View file @ 7125764c
This diff is collapsed.
arch/x86/kernel/apic/numaq_32.c deleted 100644 → 0
View file @ 7125764c
This diff is collapsed.
arch/x86/kernel/apic/summit_32.c deleted 100644 → 0
View file @ 7125764c
This diff is collapsed.
arch/x86/kernel/cpu/intel.c
View file @ 467cbd20
......@@ -274,10 +274,6 @@ static void intel_workarounds(struct cpuinfo_x86 *c)
}
#endif
#ifdef CONFIG_X86_NUMAQ
numaq_tsc_disable();
#endif
intel_smp_check(c);
}
#else
......
arch/x86/kernel/setup.c
View file @ 467cbd20
......@@ -869,7 +869,6 @@ void __init setup_arch(char **cmdline_p)
#ifdef CONFIG_X86_32
memcpy(&boot_cpu_data, &new_cpu_data, sizeof(new_cpu_data));
visws_early_detect();
/*
* copy kernel address range established so far and switch
......
arch/x86/mm/numa.c
View file @ 467cbd20
......@@ -687,10 +687,6 @@ static int __init dummy_numa_init(void)
void __init x86_numa_init(void)
{
if (!numa_off) {
#ifdef CONFIG_X86_NUMAQ
if (!numa_init(numaq_numa_init))
return;
#endif
#ifdef CONFIG_ACPI_NUMA
if (!numa_init(x86_acpi_numa_init))
return;
......
arch/x86/pci/Makefile
View file @ 467cbd20
......@@ -13,9 +13,6 @@ obj-y += legacy.o irq.o
obj-$(CONFIG_STA2X11) += sta2x11-fixup.o
obj-$(CONFIG_X86_VISWS) += visws.o
obj-$(CONFIG_X86_NUMAQ) += numaq_32.o
obj-$(CONFIG_X86_NUMACHIP) += numachip.o
obj-$(CONFIG_X86_INTEL_MID) += intel_mid_pci.o
......
arch/x86/pci/common.c
View file @ 467cbd20
......@@ -567,7 +567,6 @@ char * __init pcibios_setup(char *str)
pci_probe |= PCI_PROBE_NOEARLY;
return NULL;
}
#ifndef CONFIG_X86_VISWS
else if (!strcmp(str, "usepirqmask")) {
pci_probe |= PCI_USE_PIRQ_MASK;
return NULL;
......@@ -577,9 +576,7 @@ char * __init pcibios_setup(char *str)
} else if (!strncmp(str, "lastbus=", 8)) {
pcibios_last_bus = simple_strtol(str+8, NULL, 0);
return NULL;
}
#endif
else if (!strcmp(str, "rom")) {
} else if (!strcmp(str, "rom")) {
pci_probe |= PCI_ASSIGN_ROMS;
return NULL;
} else if (!strcmp(str, "norom")) {
......
arch/x86/pci/numaq_32.c deleted 100644 → 0
View file @ 7125764c
/*
* numaq_32.c - Low-level PCI access for NUMA-Q machines
*/
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/nodemask.h>
#include <asm/apic.h>
#include <asm/mpspec.h>
#include <asm/pci_x86.h>
#include <asm/numaq.h>
#define BUS2QUAD(global) (mp_bus_id_to_node[global])
#define BUS2LOCAL(global) (mp_bus_id_to_local[global])
#define QUADLOCAL2BUS(quad,local) (quad_local_to_mp_bus_id[quad][local])
#define PCI_CONF1_MQ_ADDRESS(bus, devfn, reg) \
(0x80000000 | (BUS2LOCAL(bus) << 16) | (devfn << 8) | (reg & ~3))
static void write_cf8(unsigned bus, unsigned devfn, unsigned reg)
{
unsigned val = PCI_CONF1_MQ_ADDRESS(bus, devfn, reg);
if (xquad_portio)
writel(val, XQUAD_PORT_ADDR(0xcf8, BUS2QUAD(bus)));
else
outl(val, 0xCF8);
}
static int pci_conf1_mq_read(unsigned int seg, unsigned int bus,
unsigned int devfn, int reg, int len, u32 *value)
{
unsigned long flags;
void *adr __iomem = XQUAD_PORT_ADDR(0xcfc, BUS2QUAD(bus));
WARN_ON(seg);
if (!value || (bus >= MAX_MP_BUSSES) || (devfn > 255) || (reg > 255))
return -EINVAL;
raw_spin_lock_irqsave(&pci_config_lock, flags);
write_cf8(bus, devfn, reg);
switch (len) {
case 1:
if (xquad_portio)
*value = readb(adr + (reg & 3));
else
*value = inb(0xCFC + (reg & 3));
break;
case 2:
if (xquad_portio)
*value = readw(adr + (reg & 2));
else
*value = inw(0xCFC + (reg & 2));
break;
case 4:
if (xquad_portio)
*value = readl(adr);
else
*value = inl(0xCFC);
break;
}
raw_spin_unlock_irqrestore(&pci_config_lock, flags);
return 0;
}
static int pci_conf1_mq_write(unsigned int seg, unsigned int bus,
unsigned int devfn, int reg, int len, u32 value)
{
unsigned long flags;
void *adr __iomem = XQUAD_PORT_ADDR(0xcfc, BUS2QUAD(bus));
WARN_ON(seg);
if ((bus >= MAX_MP_BUSSES) || (devfn > 255) || (reg > 255))
return -EINVAL;
raw_spin_lock_irqsave(&pci_config_lock, flags);
write_cf8(bus, devfn, reg);
switch (len) {
case 1:
if (xquad_portio)
writeb(value, adr + (reg & 3));
else
outb((u8)value, 0xCFC + (reg & 3));
break;
case 2:
if (xquad_portio)
writew(value, adr + (reg & 2));
else
outw((u16)value, 0xCFC + (reg & 2));
break;
case 4:
if (xquad_portio)
writel(value, adr + reg);
else
outl((u32)value, 0xCFC);
break;
}
raw_spin_unlock_irqrestore(&pci_config_lock, flags);
return 0;
}
#undef PCI_CONF1_MQ_ADDRESS
static const struct pci_raw_ops pci_direct_conf1_mq = {
.read = pci_conf1_mq_read,
.write = pci_conf1_mq_write
};
static void pci_fixup_i450nx(struct pci_dev *d)
{
/*
* i450NX -- Find and scan all secondary buses on all PXB's.
*/
int pxb, reg;
u8 busno, suba, subb;
int quad = BUS2QUAD(d->bus->number);
dev_info(&d->dev, "searching for i450NX host bridges\n");
reg = 0xd0;
for(pxb=0; pxb<2; pxb++) {
pci_read_config_byte(d, reg++, &busno);
pci_read_config_byte(d, reg++, &suba);
pci_read_config_byte(d, reg++, &subb);
dev_dbg(&d->dev, "i450NX PXB %d: %02x/%02x/%02x\n",
pxb, busno, suba, subb);
if (busno) {
/* Bus A */
pcibios_scan_root(QUADLOCAL2BUS(quad, busno));
}
if (suba < subb) {
/* Bus B */
pcibios_scan_root(QUADLOCAL2BUS(quad, suba+1));
}
}
pcibios_last_bus = -1;
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82451NX, pci_fixup_i450nx);
int __init pci_numaq_init(void)
{
int quad;
raw_pci_ops = &pci_direct_conf1_mq;
pcibios_scan_root(0);
if (num_online_nodes() > 1)
for_each_online_node(quad) {
if (quad == 0)
continue;
printk("Scanning PCI bus %d for quad %d\n",
QUADLOCAL2BUS(quad,0), quad);
pcibios_scan_root(QUADLOCAL2BUS(quad, 0));
}
return 0;
}
arch/x86/pci/visws.c deleted 100644 → 0
View file @ 7125764c
/*
* Low-Level PCI Support for SGI Visual Workstation
*
* (c) 1999--2000 Martin Mares <mj@ucw.cz>
*/
#include <linux/kernel.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <asm/setup.h>
#include <asm/pci_x86.h>
#include <asm/visws/cobalt.h>
#include <asm/visws/lithium.h>
static int pci_visws_enable_irq(struct pci_dev *dev) { return 0; }
static void pci_visws_disable_irq(struct pci_dev *dev) { }
/* int (*pcibios_enable_irq)(struct pci_dev *dev) = &pci_visws_enable_irq; */
/* void (*pcibios_disable_irq)(struct pci_dev *dev) = &pci_visws_disable_irq; */
/* void __init pcibios_penalize_isa_irq(int irq, int active) {} */
unsigned int pci_bus0, pci_bus1;
static int __init visws_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
int irq, bus = dev->bus->number;
pin--;
/* Nothing useful at PIIX4 pin 1 */
if (bus == pci_bus0 && slot == 4 && pin == 0)
return -1;
/* PIIX4 USB is on Bus 0, Slot 4, Line 3 */
if (bus == pci_bus0 && slot == 4 && pin == 3) {
irq = CO_IRQ(CO_APIC_PIIX4_USB);
goto out;
}
/* First pin spread down 1 APIC entry per slot */
if (pin == 0) {
irq = CO_IRQ((bus == pci_bus0 ? CO_APIC_PCIB_BASE0 :
CO_APIC_PCIA_BASE0) + slot);
goto out;
}
/* lines 1,2,3 from any slot is shared in this twirly pattern */
if (bus == pci_bus1) {
/* lines 1-3 from devices 0 1 rotate over 2 apic entries */
irq = CO_IRQ(CO_APIC_PCIA_BASE123 + ((slot + (pin - 1)) % 2));
} else { /* bus == pci_bus0 */
/* lines 1-3 from devices 0-3 rotate over 3 apic entries */
if (slot == 0)
slot = 3; /* same pattern */
irq = CO_IRQ(CO_APIC_PCIA_BASE123 + ((3 - slot) + (pin - 1) % 3));
}
out:
printk(KERN_DEBUG "PCI: Bus %d Slot %d Line %d -> IRQ %d\n", bus, slot, pin, irq);
return irq;
}
int __init pci_visws_init(void)
{
pcibios_enable_irq = &pci_visws_enable_irq;
pcibios_disable_irq = &pci_visws_disable_irq;
/* The VISWS supports configuration access type 1 only */
pci_probe = (pci_probe | PCI_PROBE_CONF1) &
~(PCI_PROBE_BIOS | PCI_PROBE_CONF2);
pci_bus0 = li_pcib_read16(LI_PCI_BUSNUM) & 0xff;
pci_bus1 = li_pcia_read16(LI_PCI_BUSNUM) & 0xff;
printk(KERN_INFO "PCI: Lithium bridge A bus: %u, "
"bridge B (PIIX4) bus: %u\n", pci_bus1, pci_bus0);
raw_pci_ops = &pci_direct_conf1;
pcibios_scan_root(pci_bus0);
pcibios_scan_root(pci_bus1);
pci_fixup_irqs(pci_common_swizzle, visws_map_irq);
pcibios_resource_survey();
/* Request bus scan */
return 1;
}
arch/x86/platform/Makefile
View file @ 467cbd20
......@@ -9,5 +9,4 @@ obj-y += olpc/
obj-y += scx200/
obj-y += sfi/
obj-y += ts5500/
obj-y += visws/
obj-y += uv/
arch/x86/platform/visws/Makefile deleted 100644 → 0
View file @ 7125764c
obj-$(CONFIG_X86_VISWS) += visws_quirks.o
arch/x86/platform/visws/visws_quirks.c deleted 100644 → 0
View file @ 7125764c
This diff is collapsed.
arch/x86/xen/Kconfig
View file @ 467cbd20
......@@ -7,7 +7,7 @@ config XEN
depends on PARAVIRT
select PARAVIRT_CLOCK
select XEN_HAVE_PVMMU
depends on X86_64 || (X86_32 && X86_PAE && !X86_VISWS)
depends on X86_64 || (X86_32 && X86_PAE)
depends on X86_TSC
help
This is the Linux Xen port. Enabling this will allow the
......
drivers/clocksource/Makefile
View file @ 467cbd20
obj-$(CONFIG_CLKSRC_OF) += clksrc-of.o
obj-$(CONFIG_ATMEL_TCB_CLKSRC) += tcb_clksrc.o
obj-$(CONFIG_X86_CYCLONE_TIMER) += cyclone.o
obj-$(CONFIG_X86_PM_TIMER) += acpi_pm.o
obj-$(CONFIG_SCx200HR_TIMER) += scx200_hrt.o
obj-$(CONFIG_CS5535_CLOCK_EVENT_SRC) += cs5535-clockevt.o
......
drivers/clocksource/cyclone.c deleted 100644 → 0
View file @ 7125764c
#include <linux/clocksource.h>
#include <linux/string.h>
#include <linux/errno.h>
#include <linux/timex.h>
#include <linux/init.h>
#include <asm/pgtable.h>
#include <asm/io.h>
#include <asm/mach_timer.h>
#define CYCLONE_CBAR_ADDR 0xFEB00CD0 /* base address ptr */
#define CYCLONE_PMCC_OFFSET 0x51A0 /* offset to control register */
#define CYCLONE_MPCS_OFFSET 0x51A8 /* offset to select register */
#define CYCLONE_MPMC_OFFSET 0x51D0 /* offset to count register */
#define CYCLONE_TIMER_FREQ 99780000 /* 100Mhz, but not really */
#define CYCLONE_TIMER_MASK CLOCKSOURCE_MASK(32) /* 32 bit mask */
int use_cyclone = 0;
static void __iomem *cyclone_ptr;
static cycle_t read_cyclone(struct clocksource *cs)
{
return (cycle_t)readl(cyclone_ptr);
}
static struct clocksource clocksource_cyclone = {
.name = "cyclone",
.rating = 250,
.read = read_cyclone,
.mask = CYCLONE_TIMER_MASK,
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
};
static int __init init_cyclone_clocksource(void)
{
unsigned long base; /* saved value from CBAR */
unsigned long offset;
u32 __iomem* volatile cyclone_timer; /* Cyclone MPMC0 register */
u32 __iomem* reg;
int i;
/* make sure we're on a summit box: */
if (!use_cyclone)
return -ENODEV;
printk(KERN_INFO "Summit chipset: Starting Cyclone Counter.\n");
/* find base address: */
offset = CYCLONE_CBAR_ADDR;
reg = ioremap_nocache(offset, sizeof(reg));
if (!reg) {
printk(KERN_ERR "Summit chipset: Could not find valid CBAR register.\n");
return -ENODEV;
}
/* even on 64bit systems, this is only 32bits: */
base = readl(reg);
iounmap(reg);
if (!base) {
printk(KERN_ERR "Summit chipset: Could not find valid CBAR value.\n");
return -ENODEV;
}
/* setup PMCC: */
offset = base + CYCLONE_PMCC_OFFSET;
reg = ioremap_nocache(offset, sizeof(reg));
if (!reg) {
printk(KERN_ERR "Summit chipset: Could not find valid PMCC register.\n");
return -ENODEV;
}
writel(0x00000001,reg);
iounmap(reg);
/* setup MPCS: */
offset = base + CYCLONE_MPCS_OFFSET;
reg = ioremap_nocache(offset, sizeof(reg));
if (!reg) {
printk(KERN_ERR "Summit chipset: Could not find valid MPCS register.\n");
return -ENODEV;
}
writel(0x00000001,reg);
iounmap(reg);
/* map in cyclone_timer: */
offset = base + CYCLONE_MPMC_OFFSET;
cyclone_timer = ioremap_nocache(offset, sizeof(u64));
if (!cyclone_timer) {
printk(KERN_ERR "Summit chipset: Could not find valid MPMC register.\n");
return -ENODEV;
}
/* quick test to make sure its ticking: */
for (i = 0; i < 3; i++){
u32 old = readl(cyclone_timer);
int stall = 100;
while (stall--)
barrier();
if (readl(cyclone_timer) == old) {
printk(KERN_ERR "Summit chipset: Counter not counting! DISABLED\n");
iounmap(cyclone_timer);
cyclone_timer = NULL;
return -ENODEV;
}
}
cyclone_ptr = cyclone_timer;
return clocksource_register_hz(&clocksource_cyclone,
CYCLONE_TIMER_FREQ);
}
arch_initcall(init_cyclone_clocksource);
drivers/pci/Makefile
View file @ 467cbd20
......@@ -38,7 +38,6 @@ obj-$(CONFIG_ARM) += setup-irq.o
obj-$(CONFIG_UNICORE32) += setup-irq.o
obj-$(CONFIG_SUPERH) += setup-irq.o
obj-$(CONFIG_MIPS) += setup-irq.o
obj-$(CONFIG_X86_VISWS) += setup-irq.o
obj-$(CONFIG_TILE) += setup-irq.o
obj-$(CONFIG_SPARC_LEON) += setup-irq.o
obj-$(CONFIG_M68K) += setup-irq.o
......
drivers/scsi/qla1280.c
View file @ 467cbd20
......@@ -379,14 +379,7 @@
#define DEBUG_PRINT_NVRAM 0
#define DEBUG_QLA1280 0
/*
* The SGI VISWS is broken and doesn't support MMIO ;-(
*/
#ifdef CONFIG_X86_VISWS
#define MEMORY_MAPPED_IO 0
#else
#define MEMORY_MAPPED_IO 1
#endif
#include "qla1280.h"
......
drivers/video/Kconfig
View file @ 467cbd20
......@@ -796,18 +796,9 @@ config FB_HGA
As this card technology is at least 25 years old,
most people will answer N here.
config FB_SGIVW
tristate "SGI Visual Workstation framebuffer support"
depends on FB && X86_VISWS
select FB_CFB_FILLRECT
select FB_CFB_COPYAREA
select FB_CFB_IMAGEBLIT
help
SGI Visual Workstation support for framebuffer graphics.
config FB_GBE
bool "SGI Graphics Backend frame buffer support"
depends on (FB = y) && (SGI_IP32 || X86_VISWS)
depends on (FB = y) && SGI_IP32
select FB_CFB_FILLRECT
select FB_CFB_COPYAREA
select FB_CFB_IMAGEBLIT
......
drivers/video/Makefile
View file @ 467cbd20
......@@ -75,7 +75,6 @@ obj-$(CONFIG_FB_CG14) += cg14.o sbuslib.o
obj-$(CONFIG_FB_P9100) += p9100.o sbuslib.o
obj-$(CONFIG_FB_TCX) += tcx.o sbuslib.o
obj-$(CONFIG_FB_LEO) += leo.o sbuslib.o
obj-$(CONFIG_FB_SGIVW) += sgivwfb.o
obj-$(CONFIG_FB_ACORN) += acornfb.o
obj-$(CONFIG_FB_ATARI) += atafb.o c2p_iplan2.o atafb_mfb.o \
atafb_iplan2p2.o atafb_iplan2p4.o atafb_iplan2p8.o
......
drivers/video/gbefb.c
View file @ 467cbd20
......@@ -45,10 +45,6 @@ struct gbefb_par {
#define GBE_BASE 0x16000000 /* SGI O2 */
#endif
#ifdef CONFIG_X86_VISWS
#define GBE_BASE 0xd0000000 /* SGI Visual Workstation */
#endif
/* macro for fastest write-though access to the framebuffer */
#ifdef CONFIG_MIPS
#ifdef CONFIG_CPU_R10000
......
drivers/video/logo/Kconfig
View file @ 467cbd20
......@@ -54,7 +54,7 @@ config LOGO_PARISC_CLUT224
config LOGO_SGI_CLUT224
bool "224-color SGI Linux logo"
depends on SGI_IP22 || SGI_IP27 || SGI_IP32 || X86_VISWS
depends on SGI_IP22 || SGI_IP27 || SGI_IP32
default y
config LOGO_SUN_CLUT224
......
drivers/video/logo/logo.c
View file @ 467cbd20
......@@ -81,7 +81,7 @@ const struct linux_logo * __init_refok fb_find_logo(int depth)
logo = &logo_parisc_clut224;
#endif
#ifdef CONFIG_LOGO_SGI_CLUT224
/* SGI Linux logo on MIPS/MIPS64 and VISWS */
/* SGI Linux logo on MIPS/MIPS64 */
logo = &logo_sgi_clut224;
#endif
#ifdef CONFIG_LOGO_SUN_CLUT224
......
drivers/video/sgivwfb.c deleted 100644 → 0
View file @ 7125764c
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include/video/sgivw.h deleted 100644 → 0
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sound/oss/Kconfig
View file @ 467cbd20
......@@ -13,15 +13,6 @@ config SOUND_BCM_CS4297A
note that CONFIG_KGDB should not be enabled at the same
time, since it also attempts to use this UART port.
config SOUND_VWSND
tristate "SGI Visual Workstation Sound"
depends on X86_VISWS
help
Say Y or M if you have an SGI Visual Workstation and you want to be
able to use its on-board audio. Read
<file:Documentation/sound/oss/vwsnd> for more info on this driver's
capabilities.
config SOUND_MSNDCLAS
tristate "Support for Turtle Beach MultiSound Classic, Tahiti, Monterey"
depends on (m || !STANDALONE) && ISA
......
sound/oss/Makefile
View file @ 467cbd20
......@@ -24,7 +24,6 @@ obj-$(CONFIG_SOUND_VIDC) += vidc_mod.o
obj-$(CONFIG_SOUND_WAVEARTIST) += waveartist.o
obj-$(CONFIG_SOUND_MSNDCLAS) += msnd.o msnd_classic.o
obj-$(CONFIG_SOUND_MSNDPIN) += msnd.o msnd_pinnacle.o
obj-$(CONFIG_SOUND_VWSND) += vwsnd.o
obj-$(CONFIG_SOUND_BCM_CS4297A) += swarm_cs4297a.o
obj-$(CONFIG_DMASOUND) += dmasound/
......
sound/oss/vwsnd.c deleted 100644 → 0
View file @ 7125764c
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