Commit 46f8c3c7 authored by Archit Taneja's avatar Archit Taneja Committed by Paul Walmsley

ARM: OMAP: ctrl: Fix CONTROL_DSIPHY register fields

Fix the shift and mask macros for DSIx_PPID fields in CONTROL_DSIPHY. The
OMAP4430 Public TRM vV has these fields mentioned correctly.
Signed-off-by: default avatarArchit Taneja <archit@ti.com>
Acked-by: default avatarBenoit Cousson <b-cousson@ti.com>
Acked-by: default avatarSantosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: default avatarPaul Walmsley <paul@pwsan.com>
parent be732460
...@@ -941,10 +941,10 @@ ...@@ -941,10 +941,10 @@
#define OMAP4_DSI2_LANEENABLE_MASK (0x7 << 29) #define OMAP4_DSI2_LANEENABLE_MASK (0x7 << 29)
#define OMAP4_DSI1_LANEENABLE_SHIFT 24 #define OMAP4_DSI1_LANEENABLE_SHIFT 24
#define OMAP4_DSI1_LANEENABLE_MASK (0x1f << 24) #define OMAP4_DSI1_LANEENABLE_MASK (0x1f << 24)
#define OMAP4_DSI1_PIPD_SHIFT 19 #define OMAP4_DSI2_PIPD_SHIFT 19
#define OMAP4_DSI1_PIPD_MASK (0x1f << 19) #define OMAP4_DSI2_PIPD_MASK (0x1f << 19)
#define OMAP4_DSI2_PIPD_SHIFT 14 #define OMAP4_DSI1_PIPD_SHIFT 14
#define OMAP4_DSI2_PIPD_MASK (0x1f << 14) #define OMAP4_DSI1_PIPD_MASK (0x1f << 14)
/* CONTROL_MCBSPLP */ /* CONTROL_MCBSPLP */
#define OMAP4_ALBCTRLRX_FSX_SHIFT 31 #define OMAP4_ALBCTRLRX_FSX_SHIFT 31
......
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