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Commit 470b1603 authored by Ralf Baechle's avatar Ralf Baechle
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[MIPS] Remove support for NEC DDB5476. 

As warned several times before.
Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent eaff3888
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Showing with 2 additions and 2480 deletions
Documentation/feature-removal-schedule.txt
View file @ 470b1603
......@@ -212,15 +212,6 @@ Who: Greg Kroah-Hartman <gregkh@suse.de>
---------------------------
What: Support for NEC DDB5476 evaluation boards.
When: June 2006
Why: Board specific code doesn't build anymore since ~2.6.0 and no
users have complained indicating there is no more need for these
boards. This should really be considered a last call.
Who: Ralf Baechle <ralf@linux-mips.org>
---------------------------
What: USB driver API moves to EXPORT_SYMBOL_GPL
When: Febuary 2008
Files: include/linux/usb.h, drivers/usb/core/driver.c
......
arch/mips/Kconfig
View file @ 470b1603
......@@ -469,27 +469,6 @@ config PNX8550_JBS
select PNX8550
select SYS_SUPPORTS_LITTLE_ENDIAN
config DDB5476
bool "NEC DDB Vrc-5476"
select DDB5XXX_COMMON
select DMA_NONCOHERENT
select HAVE_STD_PC_SERIAL_PORT
select HW_HAS_PCI
select IRQ_CPU
select I8259
select ISA
select SYS_HAS_CPU_R5432
select SYS_SUPPORTS_32BIT_KERNEL
select SYS_SUPPORTS_64BIT_KERNEL if EXPERIMENTAL
select SYS_SUPPORTS_LITTLE_ENDIAN
help
This enables support for the R5432-based NEC DDB Vrc-5476
evaluation board.
Features : kernel debugging, serial terminal, NFS root fs, on-board
ether port USB, AC97, PCI, PCI VGA card & framebuffer console,
IDE controller, PS2 keyboard, PS2 mouse, etc.
config DDB5477
bool "NEC DDB Vrc-5477"
select DDB5XXX_COMMON
......
arch/mips/Makefile
View file @ 470b1603
......@@ -403,12 +403,6 @@ load-$(CONFIG_MOMENCO_JAGUAR_ATX) += 0xffffffff80100000
#
core-$(CONFIG_DDB5XXX_COMMON) += arch/mips/ddb5xxx/common/
#
# NEC DDB Vrc-5476
#
core-$(CONFIG_DDB5476) += arch/mips/ddb5xxx/ddb5476/
load-$(CONFIG_DDB5476) += 0xffffffff80080000
#
# NEC DDB Vrc-5477
#
......
arch/mips/configs/atlas_defconfig
View file @ 470b1603
......@@ -41,7 +41,6 @@ CONFIG_MIPS_ATLAS=y
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_V2PCI is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_DDB5476 is not set
# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
......
arch/mips/configs/bigsur_defconfig
View file @ 470b1603
......@@ -41,7 +41,6 @@ CONFIG_MIPS=y
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_V2PCI is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_DDB5476 is not set
# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
......
arch/mips/configs/capcella_defconfig
View file @ 470b1603
......@@ -41,7 +41,6 @@ CONFIG_MIPS=y
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_V2PCI is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_DDB5476 is not set
# CONFIG_DDB5477 is not set
CONFIG_MACH_VR41XX=y
# CONFIG_PMC_YOSEMITE is not set
......
arch/mips/configs/cobalt_defconfig
View file @ 470b1603
......@@ -41,7 +41,6 @@ CONFIG_MIPS_COBALT=y
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_V2PCI is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_DDB5476 is not set
# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
......
arch/mips/configs/db1000_defconfig
View file @ 470b1603
......@@ -41,7 +41,6 @@ CONFIG_MIPS_DB1000=y
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_V2PCI is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_DDB5476 is not set
# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
......
arch/mips/configs/db1100_defconfig
View file @ 470b1603
......@@ -41,7 +41,6 @@ CONFIG_MIPS_DB1100=y
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_V2PCI is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_DDB5476 is not set
# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
......
arch/mips/configs/db1200_defconfig
View file @ 470b1603
......@@ -41,7 +41,6 @@ CONFIG_MIPS_DB1200=y
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_V2PCI is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_DDB5476 is not set
# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
......
arch/mips/configs/db1500_defconfig
View file @ 470b1603
......@@ -41,7 +41,6 @@ CONFIG_MIPS_DB1500=y
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_V2PCI is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_DDB5476 is not set
# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
......
arch/mips/configs/db1550_defconfig
View file @ 470b1603
......@@ -41,7 +41,6 @@ CONFIG_MIPS_DB1550=y
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_V2PCI is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_DDB5476 is not set
# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
......
arch/mips/configs/ddb5476_defconfig deleted 100644 → 0
View file @ eaff3888
This diff is collapsed.
arch/mips/configs/ddb5477_defconfig
View file @ 470b1603
......@@ -41,7 +41,6 @@ CONFIG_MIPS=y
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_V2PCI is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_DDB5476 is not set
CONFIG_DDB5477=y
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
......
arch/mips/configs/decstation_defconfig
View file @ 470b1603
......@@ -41,7 +41,6 @@ CONFIG_MACH_DECSTATION=y
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_V2PCI is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_DDB5476 is not set
# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
......
arch/mips/configs/e55_defconfig
View file @ 470b1603
......@@ -41,7 +41,6 @@ CONFIG_MIPS=y
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_V2PCI is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_DDB5476 is not set
# CONFIG_DDB5477 is not set
CONFIG_MACH_VR41XX=y
# CONFIG_PMC_YOSEMITE is not set
......
arch/mips/configs/ev64120_defconfig
View file @ 470b1603
......@@ -41,7 +41,6 @@ CONFIG_MIPS_EV64120=y
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_V2PCI is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_DDB5476 is not set
# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
......
arch/mips/configs/ev96100_defconfig
View file @ 470b1603
......@@ -41,7 +41,6 @@ CONFIG_MIPS_EV96100=y
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_V2PCI is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_DDB5476 is not set
# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
......
arch/mips/configs/ip22_defconfig
View file @ 470b1603
......@@ -41,7 +41,6 @@ CONFIG_MIPS=y
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_V2PCI is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_DDB5476 is not set
# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
......
arch/mips/configs/ip27_defconfig
View file @ 470b1603
......@@ -41,7 +41,6 @@ CONFIG_MIPS=y
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_V2PCI is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_DDB5476 is not set
# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
......
arch/mips/configs/ip32_defconfig
View file @ 470b1603
......@@ -41,7 +41,6 @@ CONFIG_MIPS=y
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_V2PCI is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_DDB5476 is not set
# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
......
arch/mips/configs/it8172_defconfig
View file @ 470b1603
......@@ -41,7 +41,6 @@ CONFIG_MIPS_ITE8172=y
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_V2PCI is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_DDB5476 is not set
# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
......
arch/mips/configs/ivr_defconfig
View file @ 470b1603
......@@ -41,7 +41,6 @@ CONFIG_MIPS_IVR=y
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_V2PCI is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_DDB5476 is not set
# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
......
arch/mips/configs/jaguar-atx_defconfig
View file @ 470b1603
......@@ -41,7 +41,6 @@ CONFIG_MOMENCO_JAGUAR_ATX=y
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_V2PCI is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_DDB5476 is not set
# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
......
arch/mips/configs/jmr3927_defconfig
View file @ 470b1603
......@@ -41,7 +41,6 @@ CONFIG_MIPS=y
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_V2PCI is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_DDB5476 is not set
# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
......
arch/mips/configs/lasat200_defconfig
View file @ 470b1603
......@@ -41,7 +41,6 @@ CONFIG_LASAT=y
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_V2PCI is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_DDB5476 is not set
# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
......
arch/mips/configs/malta_defconfig
View file @ 470b1603
......@@ -41,7 +41,6 @@ CONFIG_MIPS_MALTA=y
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_V2PCI is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_DDB5476 is not set
# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
......
arch/mips/configs/mipssim_defconfig
View file @ 470b1603
......@@ -41,7 +41,6 @@ CONFIG_MIPS_SIM=y
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_V2PCI is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_DDB5476 is not set
# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
......
arch/mips/configs/mpc30x_defconfig
View file @ 470b1603
......@@ -41,7 +41,6 @@ CONFIG_MIPS=y
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_V2PCI is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_DDB5476 is not set
# CONFIG_DDB5477 is not set
CONFIG_MACH_VR41XX=y
# CONFIG_PMC_YOSEMITE is not set
......
arch/mips/configs/ocelot_3_defconfig
View file @ 470b1603
......@@ -41,7 +41,6 @@ CONFIG_MOMENCO_OCELOT_3=y
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_V2PCI is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_DDB5476 is not set
# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
......
arch/mips/configs/ocelot_c_defconfig
View file @ 470b1603
......@@ -41,7 +41,6 @@ CONFIG_MOMENCO_OCELOT_C=y
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_V2PCI is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_DDB5476 is not set
# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
......
arch/mips/configs/ocelot_defconfig
View file @ 470b1603
......@@ -41,7 +41,6 @@ CONFIG_MOMENCO_OCELOT=y
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_V2PCI is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_DDB5476 is not set
# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
......
arch/mips/configs/ocelot_g_defconfig
View file @ 470b1603
......@@ -41,7 +41,6 @@ CONFIG_MOMENCO_OCELOT_G=y
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_V2PCI is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_DDB5476 is not set
# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
......
arch/mips/configs/pb1100_defconfig
View file @ 470b1603
......@@ -41,7 +41,6 @@ CONFIG_MIPS_PB1100=y
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_V2PCI is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_DDB5476 is not set
# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
......
arch/mips/configs/pb1500_defconfig
View file @ 470b1603
......@@ -41,7 +41,6 @@ CONFIG_MIPS_PB1500=y
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_V2PCI is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_DDB5476 is not set
# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
......
arch/mips/configs/pb1550_defconfig
View file @ 470b1603
......@@ -41,7 +41,6 @@ CONFIG_MIPS_PB1550=y
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_V2PCI is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_DDB5476 is not set
# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
......
arch/mips/configs/pnx8550-jbs_defconfig
View file @ 470b1603
......@@ -41,7 +41,6 @@ CONFIG_MIPS=y
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_V2PCI is not set
CONFIG_PNX8550_JBS=y
# CONFIG_DDB5476 is not set
# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
......
arch/mips/configs/pnx8550-v2pci_defconfig
View file @ 470b1603
......@@ -41,7 +41,6 @@ CONFIG_MIPS=y
# CONFIG_MIPS_XXS1500 is not set
CONFIG_PNX8550_V2PCI=y
# CONFIG_PNX8550_JBS is not set
# CONFIG_DDB5476 is not set
# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
......
arch/mips/configs/qemu_defconfig
View file @ 470b1603
......@@ -41,7 +41,6 @@ CONFIG_MIPS=y
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_V2PCI is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_DDB5476 is not set
# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
......
arch/mips/configs/rbhma4500_defconfig
View file @ 470b1603
......@@ -41,7 +41,6 @@ CONFIG_MIPS=y
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_V2PCI is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_DDB5476 is not set
# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
......
arch/mips/configs/rm200_defconfig
View file @ 470b1603
......@@ -41,7 +41,6 @@ CONFIG_MIPS=y
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_V2PCI is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_DDB5476 is not set
# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
......
arch/mips/configs/sb1250-swarm_defconfig
View file @ 470b1603
......@@ -41,7 +41,6 @@ CONFIG_MIPS=y
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_V2PCI is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_DDB5476 is not set
# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
......
arch/mips/configs/sead_defconfig
View file @ 470b1603
......@@ -41,7 +41,6 @@ CONFIG_MIPS_SEAD=y
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_V2PCI is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_DDB5476 is not set
# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
......
arch/mips/configs/tb0226_defconfig
View file @ 470b1603
......@@ -41,7 +41,6 @@ CONFIG_MIPS=y
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_V2PCI is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_DDB5476 is not set
# CONFIG_DDB5477 is not set
CONFIG_MACH_VR41XX=y
# CONFIG_PMC_YOSEMITE is not set
......
arch/mips/configs/tb0229_defconfig
View file @ 470b1603
......@@ -41,7 +41,6 @@ CONFIG_MIPS=y
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_V2PCI is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_DDB5476 is not set
# CONFIG_DDB5477 is not set
CONFIG_MACH_VR41XX=y
# CONFIG_PMC_YOSEMITE is not set
......
arch/mips/configs/tb0287_defconfig
View file @ 470b1603
......@@ -41,7 +41,6 @@ CONFIG_MIPS=y
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_V2PCI is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_DDB5476 is not set
# CONFIG_DDB5477 is not set
CONFIG_MACH_VR41XX=y
# CONFIG_PMC_YOSEMITE is not set
......
arch/mips/configs/workpad_defconfig
View file @ 470b1603
......@@ -41,7 +41,6 @@ CONFIG_MIPS=y
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_V2PCI is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_DDB5476 is not set
# CONFIG_DDB5477 is not set
CONFIG_MACH_VR41XX=y
# CONFIG_PMC_YOSEMITE is not set
......
arch/mips/configs/wrppmc_defconfig
View file @ 470b1603
......@@ -42,7 +42,6 @@ CONFIG_WR_PPMC=y
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_V2PCI is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_DDB5476 is not set
# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
......
arch/mips/configs/yosemite_defconfig
View file @ 470b1603
......@@ -41,7 +41,6 @@ CONFIG_MIPS=y
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_V2PCI is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_DDB5476 is not set
# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
CONFIG_PMC_YOSEMITE=y
......
arch/mips/ddb5xxx/common/prom.c
View file @ 470b1603
......@@ -56,10 +56,7 @@ void __init prom_init(void)
mips_machgroup = MACH_GROUP_NEC_DDB;
#if defined(CONFIG_DDB5476)
mips_machtype = MACH_NEC_DDB5476;
add_memory_region(0, DDB_SDRAM_SIZE, BOOT_MEM_RAM);
#elif defined(CONFIG_DDB5477)
#if defined(CONFIG_DDB5477)
ddb5477_runtime_detection();
add_memory_region(0, board_ram_size, BOOT_MEM_RAM);
#endif
......
arch/mips/ddb5xxx/ddb5476/Makefile deleted 100644 → 0
View file @ eaff3888
#
# Makefile for the NEC DDB Vrc-5476 specific kernel interface routines
# under Linux.
#
obj-y += setup.o irq.o nile4_pic.o vrc5476_irq.o
obj-$(CONFIG_KGDB) += dbg_io.o
EXTRA_AFLAGS := $(CFLAGS)
arch/mips/ddb5xxx/ddb5476/dbg_io.c deleted 100644 → 0
View file @ eaff3888
/*
* kgdb io functions for DDB5476. We use the second serial port.
*
* Copyright (C) 2001 MontaVista Software Inc.
* Author: jsun@mvista.com or jsun@junsun.net
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
/* ======================= CONFIG ======================== */
/* [jsun] we use the second serial port for kdb */
#define BASE 0xa60002f8
#define MAX_BAUD 115200
/* distance in bytes between two serial registers */
#define REG_OFFSET 1
/*
* 0 - kgdb does serial init
* 1 - kgdb skip serial init
*/
static int remoteDebugInitialized = 0;
/*
* the default baud rate *if* kgdb does serial init
*/
#define BAUD_DEFAULT UART16550_BAUD_38400
/* ======================= END OF CONFIG ======================== */
typedef unsigned char uint8;
typedef unsigned int uint32;
#define UART16550_BAUD_2400 2400
#define UART16550_BAUD_4800 4800
#define UART16550_BAUD_9600 9600
#define UART16550_BAUD_19200 19200
#define UART16550_BAUD_38400 38400
#define UART16550_BAUD_57600 57600
#define UART16550_BAUD_115200 115200
#define UART16550_PARITY_NONE 0
#define UART16550_PARITY_ODD 0x08
#define UART16550_PARITY_EVEN 0x18
#define UART16550_PARITY_MARK 0x28
#define UART16550_PARITY_SPACE 0x38
#define UART16550_DATA_5BIT 0x0
#define UART16550_DATA_6BIT 0x1
#define UART16550_DATA_7BIT 0x2
#define UART16550_DATA_8BIT 0x3
#define UART16550_STOP_1BIT 0x0
#define UART16550_STOP_2BIT 0x4
/* register offset */
#define OFS_RCV_BUFFER 0
#define OFS_TRANS_HOLD 0
#define OFS_SEND_BUFFER 0
#define OFS_INTR_ENABLE (1*REG_OFFSET)
#define OFS_INTR_ID (2*REG_OFFSET)
#define OFS_DATA_FORMAT (3*REG_OFFSET)
#define OFS_LINE_CONTROL (3*REG_OFFSET)
#define OFS_MODEM_CONTROL (4*REG_OFFSET)
#define OFS_RS232_OUTPUT (4*REG_OFFSET)
#define OFS_LINE_STATUS (5*REG_OFFSET)
#define OFS_MODEM_STATUS (6*REG_OFFSET)
#define OFS_RS232_INPUT (6*REG_OFFSET)
#define OFS_SCRATCH_PAD (7*REG_OFFSET)
#define OFS_DIVISOR_LSB (0*REG_OFFSET)
#define OFS_DIVISOR_MSB (1*REG_OFFSET)
/* memory-mapped read/write of the port */
#define UART16550_READ(y) (*((volatile uint8*)(BASE + y)))
#define UART16550_WRITE(y, z) ((*((volatile uint8*)(BASE + y))) = z)
void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
{
/* disable interrupts */
UART16550_WRITE(OFS_INTR_ENABLE, 0);
/* set up baud rate */
{
uint32 divisor;
/* set DIAB bit */
UART16550_WRITE(OFS_LINE_CONTROL, 0x80);
/* set divisor */
divisor = MAX_BAUD / baud;
UART16550_WRITE(OFS_DIVISOR_LSB, divisor & 0xff);
UART16550_WRITE(OFS_DIVISOR_MSB, (divisor & 0xff00) >> 8);
/* clear DIAB bit */
UART16550_WRITE(OFS_LINE_CONTROL, 0x0);
}
/* set data format */
UART16550_WRITE(OFS_DATA_FORMAT, data | parity | stop);
}
uint8 getDebugChar(void)
{
if (!remoteDebugInitialized) {
remoteDebugInitialized = 1;
debugInit(BAUD_DEFAULT,
UART16550_DATA_8BIT,
UART16550_PARITY_NONE, UART16550_STOP_1BIT);
}
while ((UART16550_READ(OFS_LINE_STATUS) & 0x1) == 0);
return UART16550_READ(OFS_RCV_BUFFER);
}
int putDebugChar(uint8 byte)
{
if (!remoteDebugInitialized) {
remoteDebugInitialized = 1;
debugInit(BAUD_DEFAULT,
UART16550_DATA_8BIT,
UART16550_PARITY_NONE, UART16550_STOP_1BIT);
}
while ((UART16550_READ(OFS_LINE_STATUS) & 0x20) == 0);
UART16550_WRITE(OFS_SEND_BUFFER, byte);
return 1;
}
arch/mips/ddb5xxx/ddb5476/irq.c deleted 100644 → 0
View file @ eaff3888
/*
* arch/mips/ddb5476/irq.c -- NEC DDB Vrc-5476 interrupt routines
*
* Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
* Sony Software Development Center Europe (SDCE), Brussels
*
* Re-write the whole thing to use new irq.c file.
* Copyright (C) 2001 MontaVista Software Inc.
* Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
*
*/
#include <linux/init.h>
#include <linux/sched.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <asm/i8259.h>
#include <asm/io.h>
#include <asm/ptrace.h>
#include <asm/ddb5xxx/ddb5xxx.h>
#define M1543_PNP_CONFIG 0x03f0 /* PnP Config Port */
#define M1543_PNP_INDEX 0x03f0 /* PnP Index Port */
#define M1543_PNP_DATA 0x03f1 /* PnP Data Port */
#define M1543_PNP_ALT_CONFIG 0x0370 /* Alternative PnP Config Port */
#define M1543_PNP_ALT_INDEX 0x0370 /* Alternative PnP Index Port */
#define M1543_PNP_ALT_DATA 0x0371 /* Alternative PnP Data Port */
#define M1543_INT1_MASTER_CTRL 0x0020 /* INT_1 (master) Control Register */
#define M1543_INT1_MASTER_MASK 0x0021 /* INT_1 (master) Mask Register */
#define M1543_INT1_SLAVE_CTRL 0x00a0 /* INT_1 (slave) Control Register */
#define M1543_INT1_SLAVE_MASK 0x00a1 /* INT_1 (slave) Mask Register */
#define M1543_INT1_MASTER_ELCR 0x04d0 /* INT_1 (master) Edge/Level Control */
#define M1543_INT1_SLAVE_ELCR 0x04d1 /* INT_1 (slave) Edge/Level Control */
static void m1543_irq_setup(void)
{
/*
* The ALI M1543 has 13 interrupt inputs, IRQ1..IRQ13. Not all
* the possible IO sources in the M1543 are in use by us. We will
* use the following mapping:
*
* IRQ1 - keyboard (default set by M1543)
* IRQ3 - reserved for UART B (default set by M1543) (note that
* the schematics for the DDB Vrc-5476 board seem to
* indicate that IRQ3 is connected to the DS1386
* watchdog timer interrupt output so we might have
* a conflict)
* IRQ4 - reserved for UART A (default set by M1543)
* IRQ5 - parallel (default set by M1543)
* IRQ8 - DS1386 time of day (RTC) interrupt
* IRQ9 - USB (hardwired in ddb_setup)
* IRQ10 - PMU (hardwired in ddb_setup)
* IRQ12 - mouse
* IRQ14,15 - IDE controller (need to be confirmed, jsun)
*/
/*
* Assing mouse interrupt to IRQ12
*/
/* Enter configuration mode */
outb(0x51, M1543_PNP_CONFIG);
outb(0x23, M1543_PNP_CONFIG);
/* Select logical device 7 (Keyboard) */
outb(0x07, M1543_PNP_INDEX);
outb(0x07, M1543_PNP_DATA);
/* Select IRQ12 */
outb(0x72, M1543_PNP_INDEX);
outb(0x0c, M1543_PNP_DATA);
/* Leave configration mode */
outb(0xbb, M1543_PNP_CONFIG);
}
static void nile4_irq_setup(void)
{
int i;
/* Map all interrupts to CPU int #0 (IP2) */
nile4_map_irq_all(0);
/* PCI INTA#-E# must be level triggered */
nile4_set_pci_irq_level_or_edge(0, 1);
nile4_set_pci_irq_level_or_edge(1, 1);
nile4_set_pci_irq_level_or_edge(2, 1);
nile4_set_pci_irq_level_or_edge(3, 1);
/* PCI INTA#, B#, D# must be active low, INTC# must be active high */
nile4_set_pci_irq_polarity(0, 0);
nile4_set_pci_irq_polarity(1, 0);
nile4_set_pci_irq_polarity(2, 1);
nile4_set_pci_irq_polarity(3, 0);
for (i = 0; i < 16; i++)
nile4_clear_irq(i);
/* Enable CPU int #0 */
nile4_enable_irq_output(0);
/* memory resource acquire in ddb_setup */
}
static struct irqaction irq_cascade = { no_action, 0, CPU_MASK_NONE, "cascade", NULL, NULL };
static struct irqaction irq_error = { no_action, 0, CPU_MASK_NONE, "error", NULL, NULL };
extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
extern void mips_cpu_irq_init(u32 irq_base);
extern void vrc5476_irq_init(u32 irq_base);
extern void vrc5476_irq_dispatch(struct pt_regs *regs);
asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
{
unsigned int pending = read_c0_cause() & read_c0_status();
if (pending & STATUSF_IP7)
do_IRQ(CPU_IRQ_BASE + 7, regs);
else if (pending & STATUSF_IP2)
vrc5476_irq_dispatch(regs);
else if (pending & STATUSF_IP3)
do_IRQ(CPU_IRQ_BASE + 3, regs);
else if (pending & STATUSF_IP4)
do_IRQ(CPU_IRQ_BASE + 4, regs);
else if (pending & STATUSF_IP5)
do_IRQ(CPU_IRQ_BASE + 5, regs);
else if (pending & STATUSF_IP6)
do_IRQ(CPU_IRQ_BASE + 6, regs);
else if (pending & STATUSF_IP0)
do_IRQ(CPU_IRQ_BASE, regs);
else if (pending & STATUSF_IP1)
do_IRQ(CPU_IRQ_BASE + 1, regs);
vrc5476_irq_dispatch(regs);
}
void __init arch_init_irq(void)
{
/* hardware initialization */
nile4_irq_setup();
m1543_irq_setup();
/* controller setup */
init_i8259_irqs();
vrc5476_irq_init(VRC5476_IRQ_BASE);
mips_cpu_irq_init(CPU_IRQ_BASE);
/* setup cascade interrupts */
setup_irq(VRC5476_IRQ_BASE + VRC5476_I8259_CASCADE, &irq_cascade);
setup_irq(CPU_IRQ_BASE + CPU_VRC5476_CASCADE, &irq_cascade);
/* setup error interrupts for debugging */
setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_CPCE, &irq_error);
setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_CNTD, &irq_error);
setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_MCE, &irq_error);
setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_LBRT, &irq_error);
setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_PCIS, &irq_error);
setup_irq(VRC5476_IRQ_BASE + VRC5476_IRQ_PCI, &irq_error);
}
arch/mips/ddb5xxx/ddb5476/nile4_pic.c deleted 100644 → 0
View file @ eaff3888
/*
* arch/mips/ddb5476/nile4.c --
* low-level PIC code for NEC Vrc-5476 (Nile 4)
*
* Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
* Sony Software Development Center Europe (SDCE), Brussels
*
* Copyright 2001 MontaVista Software Inc.
* Author: jsun@mvista.com or jsun@junsun.net
*
*/
#include <linux/config.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <asm/addrspace.h>
#include <asm/ddb5xxx/ddb5xxx.h>
/*
* Interrupt Programming
*/
void nile4_map_irq(int nile4_irq, int cpu_irq)
{
u32 offset, t;
offset = DDB_INTCTRL;
if (nile4_irq >= 8) {
offset += 4;
nile4_irq -= 8;
}
t = ddb_in32(offset);
t &= ~(7 << (nile4_irq * 4));
t |= cpu_irq << (nile4_irq * 4);
ddb_out32(offset, t);
}
void nile4_map_irq_all(int cpu_irq)
{
u32 all, t;
all = cpu_irq;
all |= all << 4;
all |= all << 8;
all |= all << 16;
t = ddb_in32(DDB_INTCTRL);
t &= 0x88888888;
t |= all;
ddb_out32(DDB_INTCTRL, t);
t = ddb_in32(DDB_INTCTRL + 4);
t &= 0x88888888;
t |= all;
ddb_out32(DDB_INTCTRL + 4, t);
}
void nile4_enable_irq(int nile4_irq)
{
u32 offset, t;
offset = DDB_INTCTRL;
if (nile4_irq >= 8) {
offset += 4;
nile4_irq -= 8;
}
t = ddb_in32(offset);
t |= 8 << (nile4_irq * 4);
ddb_out32(offset, t);
}
void nile4_disable_irq(int nile4_irq)
{
u32 offset, t;
offset = DDB_INTCTRL;
if (nile4_irq >= 8) {
offset += 4;
nile4_irq -= 8;
}
t = ddb_in32(offset);
t &= ~(8 << (nile4_irq * 4));
ddb_out32(offset, t);
}
void nile4_disable_irq_all(void)
{
ddb_out32(DDB_INTCTRL, 0);
ddb_out32(DDB_INTCTRL + 4, 0);
}
u16 nile4_get_irq_stat(int cpu_irq)
{
return ddb_in16(DDB_INTSTAT0 + cpu_irq * 2);
}
void nile4_enable_irq_output(int cpu_irq)
{
u32 t;
t = ddb_in32(DDB_INTSTAT1 + 4);
t |= 1 << (16 + cpu_irq);
ddb_out32(DDB_INTSTAT1, t);
}
void nile4_disable_irq_output(int cpu_irq)
{
u32 t;
t = ddb_in32(DDB_INTSTAT1 + 4);
t &= ~(1 << (16 + cpu_irq));
ddb_out32(DDB_INTSTAT1, t);
}
void nile4_set_pci_irq_polarity(int pci_irq, int high)
{
u32 t;
t = ddb_in32(DDB_INTPPES);
if (high)
t &= ~(1 << (pci_irq * 2));
else
t |= 1 << (pci_irq * 2);
ddb_out32(DDB_INTPPES, t);
}
void nile4_set_pci_irq_level_or_edge(int pci_irq, int level)
{
u32 t;
t = ddb_in32(DDB_INTPPES);
if (level)
t |= 2 << (pci_irq * 2);
else
t &= ~(2 << (pci_irq * 2));
ddb_out32(DDB_INTPPES, t);
}
void nile4_clear_irq(int nile4_irq)
{
ddb_out32(DDB_INTCLR, 1 << nile4_irq);
}
void nile4_clear_irq_mask(u32 mask)
{
ddb_out32(DDB_INTCLR, mask);
}
u8 nile4_i8259_iack(void)
{
u8 irq;
u32 reg;
/* Set window 0 for interrupt acknowledge */
reg = ddb_in32(DDB_PCIINIT0);
ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IACK, 0, DDB_PCI_ACCESS_32);
irq = *(volatile u8 *) KSEG1ADDR(DDB_PCI_IACK_BASE);
/* restore window 0 for PCI I/O space */
// ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IO, 0, DDB_PCI_ACCESS_32);
ddb_out32(DDB_PCIINIT0, reg);
/* i8269.c set the base vector to be 0x0 */
return irq + I8259_IRQ_BASE;
}
#if defined(CONFIG_RUNTIME_DEBUG)
void nile4_dump_irq_status(void)
{
printk(KERN_DEBUG "
CPUSTAT = %p:%p\n", (void *) ddb_in32(DDB_CPUSTAT + 4),
(void *) ddb_in32(DDB_CPUSTAT));
printk(KERN_DEBUG "
INTCTRL = %p:%p\n", (void *) ddb_in32(DDB_INTCTRL + 4),
(void *) ddb_in32(DDB_INTCTRL));
printk(KERN_DEBUG
"INTSTAT0 = %p:%p\n",
(void *) ddb_in32(DDB_INTSTAT0 + 4),
(void *) ddb_in32(DDB_INTSTAT0));
printk(KERN_DEBUG
"INTSTAT1 = %p:%p\n",
(void *) ddb_in32(DDB_INTSTAT1 + 4),
(void *) ddb_in32(DDB_INTSTAT1));
printk(KERN_DEBUG
"INTCLR = %p:%p\n", (void *) ddb_in32(DDB_INTCLR + 4),
(void *) ddb_in32(DDB_INTCLR));
printk(KERN_DEBUG
"INTPPES = %p:%p\n", (void *) ddb_in32(DDB_INTPPES + 4),
(void *) ddb_in32(DDB_INTPPES));
}
#endif
arch/mips/ddb5xxx/ddb5476/setup.c deleted 100644 → 0
View file @ eaff3888
/*
* arch/mips/ddb5476/setup.c -- NEC DDB Vrc-5476 setup routines
*
* Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
* Sony Software Development Center Europe (SDCE), Brussels
*/
#include <linux/init.h>
#include <linux/kbd_ll.h>
#include <linux/kernel.h>
#include <linux/kdev_t.h>
#include <linux/types.h>
#include <linux/sched.h>
#include <linux/pci.h>
#include <linux/pm.h>
#include <asm/addrspace.h>
#include <asm/bcache.h>
#include <asm/irq.h>
#include <asm/reboot.h>
#include <asm/gdb-stub.h>
#include <asm/time.h>
#include <asm/debug.h>
#include <asm/traps.h>
#include <asm/ddb5xxx/ddb5xxx.h>
// #define USE_CPU_COUNTER_TIMER /* whether we use cpu counter */
#ifdef USE_CPU_COUNTER_TIMER
#define CPU_COUNTER_FREQUENCY 83000000
#else
/* otherwise we use general purpose timer */
#define TIMER_FREQUENCY 83000000
#define TIMER_BASE DDB_T2CTRL
#define TIMER_IRQ (VRC5476_IRQ_BASE + VRC5476_IRQ_GPT)
#endif
static void (*back_to_prom) (void) = (void (*)(void)) 0xbfc00000;
static void ddb_machine_restart(char *command)
{
u32 t;
/* PCI cold reset */
t = ddb_in32(DDB_PCICTRL + 4);
t |= 0x40000000;
ddb_out32(DDB_PCICTRL + 4, t);
/* CPU cold reset */
t = ddb_in32(DDB_CPUSTAT);
t |= 1;
ddb_out32(DDB_CPUSTAT, t);
/* Call the PROM */
back_to_prom();
}
static void ddb_machine_halt(void)
{
printk(KERN_NOTICE "DDB Vrc-5476 halted.\n");
while (1);
}
static void ddb_machine_power_off(void)
{
printk(KERN_NOTICE "DDB Vrc-5476 halted. Please turn off the power.\n");
while (1);
}
extern void rtc_ds1386_init(unsigned long base);
static void __init ddb_time_init(void)
{
#if defined(USE_CPU_COUNTER_TIMER)
mips_hpt_frequency = CPU_COUNTER_FREQUENCY;
#endif
/* we have ds1396 RTC chip */
rtc_ds1386_init(KSEG1ADDR(DDB_PCI_MEM_BASE));
}
extern int setup_irq(unsigned int irq, struct irqaction *irqaction);
static void __init ddb_timer_setup(struct irqaction *irq)
{
#if defined(USE_CPU_COUNTER_TIMER)
unsigned int count;
/* we are using the cpu counter for timer interrupts */
setup_irq(CPU_IRQ_BASE + 7, irq);
/* to generate the first timer interrupt */
count = read_c0_count();
write_c0_compare(count + 1000);
#else
ddb_out32(TIMER_BASE, TIMER_FREQUENCY/HZ);
ddb_out32(TIMER_BASE+4, 0x1); /* enable timer */
setup_irq(TIMER_IRQ, irq);
#endif
}
static struct {
struct resource dma1;
struct resource timer;
struct resource rtc;
struct resource dma_page_reg;
struct resource dma2;
} ddb5476_ioport = {
{
.start = 0x00,
.end = 0x1f,
.name = "dma1",
.flags = IORESOURCE_BUSY
}, {
.start = 0x40,
.end = 0x5f,
.name = "timer",
.flags = IORESOURCE_BUSY
}, {
.start = 0x70,
.end = 0x7f,
.name = "rtc",
.flags = IORESOURCE_BUSY
}, {
.start = 0x80,
.end = 0x8f,
.name = "dma page reg",
.flags = IORESOURCE_BUSY
}, {
.start = 0xc0,
.end = 0xdf,
.name = "dma2",
.flags = IORESOURCE_BUSY
}
};
static struct {
struct resource nile4;
} ddb5476_iomem = {
{
.start = DDB_BASE,
.end = DDB_BASE + DDB_SIZE - 1,
.name = "Nile 4",
.flags = IORESOURCE_BUSY
}
};
static void ddb5476_board_init(void);
void __init plat_mem_setup(void)
{
set_io_port_base(KSEG1ADDR(DDB_PCI_IO_BASE));
board_time_init = ddb_time_init;
board_timer_setup = ddb_timer_setup;
_machine_restart = ddb_machine_restart;
_machine_halt = ddb_machine_halt;
pm_power_off = ddb_machine_power_off;
/* request io port/mem resources */
if (request_resource(&ioport_resource, &ddb5476_ioport.dma1) ||
request_resource(&ioport_resource, &ddb5476_ioport.timer) ||
request_resource(&ioport_resource, &ddb5476_ioport.rtc) ||
request_resource(&ioport_resource,
&ddb5476_ioport.dma_page_reg)
|| request_resource(&ioport_resource, &ddb5476_ioport.dma2)
|| request_resource(&iomem_resource, &ddb5476_iomem.nile4)) {
printk
("ddb_setup - requesting oo port resources failed.\n");
for (;;);
}
/* Reboot on panic */
panic_timeout = 180;
/* [jsun] we need to set BAR0 so that SDRAM 0 appears at 0x0 in PCI */
/* *(long*)0xbfa00218 = 0x8; */
/* board initialization stuff */
ddb5476_board_init();
}
/*
* We don't trust bios. We essentially does hardware re-initialization
* as complete as possible, as far as we know we can safely do.
*/
static void ddb5476_board_init(void)
{
/* ----------- setup PDARs ------------ */
/* check SDRAM0, whether we are on MEM bus does not matter */
db_assert((ddb_in32(DDB_SDRAM0) & 0xffffffef) ==
ddb_calc_pdar(DDB_SDRAM_BASE, DDB_SDRAM_SIZE, 32, 0, 1));
/* SDRAM1 should be turned off. What is this for anyway ? */
db_assert( (ddb_in32(DDB_SDRAM1) & 0xf) == 0);
/* flash 1&2, DDB status, DDB control */
ddb_set_pdar(DDB_DCS2, DDB_DCS2_BASE, DDB_DCS2_SIZE, 16, 0, 0);
ddb_set_pdar(DDB_DCS3, DDB_DCS3_BASE, DDB_DCS3_SIZE, 16, 0, 0);
ddb_set_pdar(DDB_DCS4, DDB_DCS4_BASE, DDB_DCS4_SIZE, 8, 0, 0);
ddb_set_pdar(DDB_DCS5, DDB_DCS5_BASE, DDB_DCS5_SIZE, 8, 0, 0);
/* shut off other pdar so they don't accidentally get into the way */
ddb_set_pdar(DDB_DCS6, 0xffffffff, 0, 32, 0, 0);
ddb_set_pdar(DDB_DCS7, 0xffffffff, 0, 32, 0, 0);
ddb_set_pdar(DDB_DCS8, 0xffffffff, 0, 32, 0, 0);
/* verify VRC5477 base addr */
/* don't care about some details */
db_assert((ddb_in32(DDB_INTCS) & 0xffffff0f) ==
ddb_calc_pdar(DDB_INTCS_BASE, DDB_INTCS_SIZE, 8, 0, 0));
/* verify BOOT ROM addr */
/* don't care about some details */
db_assert((ddb_in32(DDB_BOOTCS) & 0xffffff0f) ==
ddb_calc_pdar(DDB_BOOTCS_BASE, DDB_BOOTCS_SIZE, 8, 0, 0));
/* setup PCI windows - window1 for MEM/config, window0 for IO */
ddb_set_pdar(DDB_PCIW0, DDB_PCI_IO_BASE, DDB_PCI_IO_SIZE, 32, 0, 1);
ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IO, 0, DDB_PCI_ACCESS_32);
ddb_set_pdar(DDB_PCIW1, DDB_PCI_MEM_BASE, DDB_PCI_MEM_SIZE, 32, 0, 1);
ddb_set_pmr(DDB_PCIINIT1, DDB_PCICMD_MEM, DDB_PCI_MEM_BASE, DDB_PCI_ACCESS_32);
/* ----------- setup PDARs ------------ */
/* this is problematic - it will reset Aladin which cause we loose
* serial port, and we don't know how to set up Aladin chip again.
*/
// ddb_pci_reset_bus();
ddb_out32(DDB_BAR0, 0x00000008);
ddb_out32(DDB_BARC, 0xffffffff);
ddb_out32(DDB_BARB, 0xffffffff);
ddb_out32(DDB_BAR1, 0xffffffff);
ddb_out32(DDB_BAR2, 0xffffffff);
ddb_out32(DDB_BAR3, 0xffffffff);
ddb_out32(DDB_BAR4, 0xffffffff);
ddb_out32(DDB_BAR5, 0xffffffff);
ddb_out32(DDB_BAR6, 0xffffffff);
ddb_out32(DDB_BAR7, 0xffffffff);
ddb_out32(DDB_BAR8, 0xffffffff);
/* ----------- switch PCI1 to PCI CONFIG space ------------ */
ddb_set_pdar(DDB_PCIW1, DDB_PCI_CONFIG_BASE, DDB_PCI_CONFIG_SIZE, 32, 0, 1);
ddb_set_pmr(DDB_PCIINIT1, DDB_PCICMD_CFG, 0x0, DDB_PCI_ACCESS_32);
/* ----- M1543 PCI setup ------ */
/* we know M1543 PCI-ISA controller is at addr:18 */
/* xxxx1010 makes USB at addr:13 and PMU at addr:14 */
*(volatile unsigned char *) 0xa8040072 &= 0xf0;
*(volatile unsigned char *) 0xa8040072 |= 0xa;
/* setup USB interrupt to IRQ 9, (bit 0:3 - 0001)
* no IOCHRDY signal, (bit 7 - 1)
* M1543C & M7101 VID and Subsys Device ID are read-only (bit 6 - 1)
* Make USB Master INTAJ level to edge conversion (bit 4 - 1)
*/
*(unsigned char *) 0xa8040074 = 0xd1;
/* setup PMU(SCI to IRQ 10 (bit 0:3 - 0011)
* SCI routing to IRQ 13 disabled (bit 7 - 1)
* SCI interrupt level to edge conversion bypassed (bit 4 - 0)
*/
*(unsigned char *) 0xa8040076 = 0x83;
/* setup IDE controller
* enable IDE controller (bit 6 - 1)
* IDE IDSEL to be addr:24 (bit 4:5 - 11)
* no IDE ATA Secondary Bus Signal Pad Control (bit 3 - 0)
* no IDE ATA Primary Bus Signal Pad Control (bit 2 - 0)
* primary IRQ is 14, secondary is 15 (bit 1:0 - 01
*/
// *(unsigned char*)0xa8040058 = 0x71;
// *(unsigned char*)0xa8040058 = 0x79;
// *(unsigned char*)0xa8040058 = 0x74; // use SIRQ, primary tri-state
*(unsigned char *) 0xa8040058 = 0x75; // primary tri-state
#if 0
/* this is not necessary if M5229 does not use SIRQ */
*(unsigned char *) 0xa8040044 = 0x0d; // primary to IRQ 14
*(unsigned char *) 0xa8040075 = 0x0d; // secondary to IRQ 14
#endif
/* enable IDE in the M5229 config register 0x50 (bit 0 - 1) */
/* M5229 IDSEL is addr:24; see above setting */
*(unsigned char *) 0xa9000050 |= 0x1;
/* enable bus master (bit 2) and IO decoding (bit 0) */
*(unsigned char *) 0xa9000004 |= 0x5;
/* enable native, copied from arch/ppc/k2boot/head.S */
/* TODO - need volatile, need to be portable */
*(unsigned char *) 0xa9000009 = 0xff;
/* ----- end of M1543 PCI setup ------ */
/* ----- reset on-board ether chip ------ */
*((volatile u32 *) 0xa8020004) |= 1; /* decode I/O */
*((volatile u32 *) 0xa8020010) = 0; /* set BAR address */
/* send reset command */
*((volatile u32 *) 0xa6000000) = 1; /* do a soft reset */
/* disable ether chip */
*((volatile u32 *) 0xa8020004) = 0; /* disable any decoding */
/* put it into sleep */
*((volatile u32 *) 0xa8020040) = 0x80000000;
/* ----- end of reset on-board ether chip ------ */
/* ----------- switch PCI1 back to PCI MEM space ------------ */
ddb_set_pdar(DDB_PCIW1, DDB_PCI_MEM_BASE, DDB_PCI_MEM_SIZE, 32, 0, 1);
ddb_set_pmr(DDB_PCIINIT1, DDB_PCICMD_MEM, DDB_PCI_MEM_BASE, DDB_PCI_ACCESS_32);
}
arch/mips/ddb5xxx/ddb5476/vrc5476_irq.c deleted 100644 → 0
View file @ eaff3888
/*
* The irq controller for vrc5476.
*
* Copyright (C) 2001 MontaVista Software Inc.
* Author: jsun@mvista.com or jsun@junsun.net
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/types.h>
#include <linux/ptrace.h>
#include <asm/system.h>
#include <asm/ddb5xxx/ddb5xxx.h>
static int irq_base;
static void vrc5476_irq_enable(uint irq)
{
nile4_enable_irq(irq - irq_base);
}
static void vrc5476_irq_disable(uint irq)
{
nile4_disable_irq(irq - irq_base);
}
static unsigned int vrc5476_irq_startup(uint irq)
{
nile4_enable_irq(irq - irq_base);
return 0;
}
#define vrc5476_irq_shutdown vrc5476_irq_disable
static void vrc5476_irq_ack(uint irq)
{
nile4_clear_irq(irq - irq_base);
nile4_disable_irq(irq - irq_base);
}
static void vrc5476_irq_end(uint irq)
{
if(!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
vrc5476_irq_enable(irq);
}
static hw_irq_controller vrc5476_irq_controller = {
.typename = "vrc5476",
.startup = vrc5476_irq_startup,
.shutdown = vrc5476_irq_shutdown,
.enable = vrc5476_irq_enable,
.disable = vrc5476_irq_disable,
.ack = vrc5476_irq_ack,
.end = vrc5476_irq_end
};
void __init
vrc5476_irq_init(u32 base)
{
u32 i;
irq_base = base;
for (i= base; i< base + NUM_VRC5476_IRQ; i++) {
irq_desc[i].status = IRQ_DISABLED;
irq_desc[i].action = NULL;
irq_desc[i].depth = 1;
irq_desc[i].handler = &vrc5476_irq_controller;
}
}
void
vrc5476_irq_dispatch(struct pt_regs *regs)
{
u32 mask;
int nile4_irq;
mask = nile4_get_irq_stat(0);
/* quick check for possible time interrupt */
if (mask & (1 << VRC5476_IRQ_GPT)) {
do_IRQ(VRC5476_IRQ_BASE + VRC5476_IRQ_GPT, regs);
return;
}
/* check for i8259 interrupts */
if (mask & (1 << VRC5476_I8259_CASCADE)) {
int i8259_irq = nile4_i8259_iack();
do_IRQ(I8259_IRQ_BASE + i8259_irq, regs);
return;
}
/* regular nile4 interrupts (we should not really have any */
for (nile4_irq = 0; mask; nile4_irq++, mask >>= 1) {
if (mask & 1) {
do_IRQ(VRC5476_IRQ_BASE + nile4_irq, regs);
return;
}
}
spurious_interrupt(regs);
}
arch/mips/defconfig
View file @ 470b1603
......@@ -41,7 +41,6 @@ CONFIG_MIPS=y
# CONFIG_MIPS_XXS1500 is not set
# CONFIG_PNX8550_V2PCI is not set
# CONFIG_PNX8550_JBS is not set
# CONFIG_DDB5476 is not set
# CONFIG_DDB5477 is not set
# CONFIG_MACH_VR41XX is not set
# CONFIG_PMC_YOSEMITE is not set
......
arch/mips/pci/Makefile
View file @ 470b1603
......@@ -22,7 +22,6 @@ obj-$(CONFIG_NEC_CMBVR4133) += fixup-vr4133.o
#
# These are still pretty much in the old state, watch, go blind.
#
obj-$(CONFIG_DDB5476) += ops-ddb5476.o pci-ddb5476.o
obj-$(CONFIG_DDB5477) += fixup-ddb5477.o pci-ddb5477.o ops-ddb5477.o
obj-$(CONFIG_LASAT) += pci-lasat.o
obj-$(CONFIG_MIPS_ATLAS) += fixup-atlas.o
......
arch/mips/pci/ops-ddb5476.c deleted 100644 → 0
View file @ eaff3888
/*
* Copyright 2001 MontaVista Software Inc.
* Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
*
* arch/mips/ddb5xxx/ddb5476/pci_ops.c
* Define the pci_ops for DB5477.
*
* Much of the code is derived from the original DDB5074 port by
* Geert Uytterhoeven <geert@sonycom.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
#include <linux/pci.h>
#include <linux/kernel.h>
#include <linux/types.h>
#include <asm/addrspace.h>
#include <asm/debug.h>
#include <asm/ddb5xxx/ddb5xxx.h>
/*
* config_swap structure records what set of pdar/pmr are used
* to access pci config space. It also provides a place hold the
* original values for future restoring.
*/
struct pci_config_swap {
u32 pdar;
u32 pmr;
u32 config_base;
u32 config_size;
u32 pdar_backup;
u32 pmr_backup;
};
/*
* On DDB5476, we have one set of swap registers
*/
struct pci_config_swap ext_pci_swap = {
DDB_PCIW0,
DDB_PCIINIT0,
DDB_PCI_CONFIG_BASE,
DDB_PCI_CONFIG_SIZE
};
static int pci_config_workaround = 1;
/*
* access config space
*/
static inline u32 ddb_access_config_base(struct pci_config_swap *swap, u32 bus, /* 0 means top level bus */
u32 slot_num)
{
u32 pci_addr = 0;
u32 pciinit_offset = 0;
u32 virt_addr = swap->config_base;
u32 option;
if (pci_config_workaround) {
/* [jsun] work around Vrc5476 controller itself, returnning
* slot 0 essentially makes vrc5476 invisible
*/
if (slot_num == 12)
slot_num = 0;
#if 0
/* BUG : skip P2P bridge for now */
if (slot_num == 5)
slot_num = 0;
#endif
} else {
/* now we have to be hornest, returning the true
* PCI config headers for vrc5476
*/
if (slot_num == 12) {
swap->pdar_backup = ddb_in32(swap->pdar);
swap->pmr_backup = ddb_in32(swap->pmr);
return DDB_BASE + DDB_PCI_BASE;
}
}
/* minimum pdar (window) size is 2MB */
db_assert(swap->config_size >= (2 << 20));
db_assert(slot_num < (1 << 5));
db_assert(bus < (1 << 8));
/* backup registers */
swap->pdar_backup = ddb_in32(swap->pdar);
swap->pmr_backup = ddb_in32(swap->pmr);
/* set the pdar (pci window) register */
ddb_set_pdar(swap->pdar, swap->config_base, swap->config_size, 32, /* 32 bit wide */
0, /* not on local memory bus */
0); /* not visible from PCI bus (N/A) */
/*
* calcuate the absolute pci config addr;
* according to the spec, we start scanning from adr:11 (0x800)
*/
if (bus == 0) {
/* type 0 config */
pci_addr = 0x800 << slot_num;
} else {
/* type 1 config */
pci_addr = (bus << 16) | (slot_num << 11);
/* panic("ddb_access_config_base: we don't support type 1 config Yet"); */
}
/*
* if pci_addr is less than pci config window size, we set
* pciinit_offset to 0 and adjust the virt_address.
* Otherwise we will try to adjust pciinit_offset.
*/
if (pci_addr < swap->config_size) {
virt_addr = KSEG1ADDR(swap->config_base + pci_addr);
pciinit_offset = 0;
} else {
db_assert((pci_addr & (swap->config_size - 1)) == 0);
virt_addr = KSEG1ADDR(swap->config_base);
pciinit_offset = pci_addr;
}
/* set the pmr register */
option = DDB_PCI_ACCESS_32;
if (bus != 0)
option |= DDB_PCI_CFGTYPE1;
ddb_set_pmr(swap->pmr, DDB_PCICMD_CFG, pciinit_offset, option);
return virt_addr;
}
static inline void ddb_close_config_base(struct pci_config_swap *swap)
{
ddb_out32(swap->pdar, swap->pdar_backup);
ddb_out32(swap->pmr, swap->pmr_backup);
}
static int read_config_dword(struct pci_config_swap *swap,
struct pci_dev *dev, u32 where, u32 * val)
{
u32 bus, slot_num, func_num;
u32 base;
db_assert((where & 3) == 0);
db_assert(where < (1 << 8));
/* check if the bus is top-level */
if (dev->bus->parent != NULL) {
bus = dev->bus->number;
db_assert(bus != 0);
} else {
bus = 0;
}
slot_num = PCI_SLOT(dev->devfn);
func_num = PCI_FUNC(dev->devfn);
base = ddb_access_config_base(swap, bus, slot_num);
*val = *(volatile u32 *) (base + (func_num << 8) + where);
ddb_close_config_base(swap);
return PCIBIOS_SUCCESSFUL;
}
static int read_config_word(struct pci_config_swap *swap,
struct pci_dev *dev, u32 where, u16 * val)
{
int status;
u32 result;
db_assert((where & 1) == 0);
status = read_config_dword(swap, dev, where & ~3, &result);
if (where & 2)
result >>= 16;
*val = result & 0xffff;
return status;
}
static int read_config_byte(struct pci_config_swap *swap,
struct pci_dev *dev, u32 where, u8 * val)
{
int status;
u32 result;
status = read_config_dword(swap, dev, where & ~3, &result);
if (where & 1)
result >>= 8;
if (where & 2)
result >>= 16;
*val = result & 0xff;
return status;
}
static int write_config_dword(struct pci_config_swap *swap,
struct pci_dev *dev, u32 where, u32 val)
{
u32 bus, slot_num, func_num;
u32 base;
db_assert((where & 3) == 0);
db_assert(where < (1 << 8));
/* check if the bus is top-level */
if (dev->bus->parent != NULL) {
bus = dev->bus->number;
db_assert(bus != 0);
} else {
bus = 0;
}
slot_num = PCI_SLOT(dev->devfn);
func_num = PCI_FUNC(dev->devfn);
base = ddb_access_config_base(swap, bus, slot_num);
*(volatile u32 *) (base + (func_num << 8) + where) = val;
ddb_close_config_base(swap);
return PCIBIOS_SUCCESSFUL;
}
static int write_config_word(struct pci_config_swap *swap,
struct pci_dev *dev, u32 where, u16 val)
{
int status, shift = 0;
u32 result;
db_assert((where & 1) == 0);
status = read_config_dword(swap, dev, where & ~3, &result);
if (status != PCIBIOS_SUCCESSFUL)
return status;
if (where & 2)
shift += 16;
result &= ~(0xffff << shift);
result |= val << shift;
return write_config_dword(swap, dev, where & ~3, result);
}
static int write_config_byte(struct pci_config_swap *swap,
struct pci_dev *dev, u32 where, u8 val)
{
int status, shift = 0;
u32 result;
status = read_config_dword(swap, dev, where & ~3, &result);
if (status != PCIBIOS_SUCCESSFUL)
return status;
if (where & 2)
shift += 16;
if (where & 1)
shift += 8;
result &= ~(0xff << shift);
result |= val << shift;
return write_config_dword(swap, dev, where & ~3, result);
}
#define MAKE_PCI_OPS(prefix, rw, unitname, unittype, pciswap) \
static int prefix##_##rw##_config_##unitname(struct pci_dev *dev, int where, unittype val) \
{ \
return rw##_config_##unitname(pciswap, \
dev, \
where, \
val); \
}
MAKE_PCI_OPS(extpci, read, byte, u8 *, &ext_pci_swap)
MAKE_PCI_OPS(extpci, read, word, u16 *, &ext_pci_swap)
MAKE_PCI_OPS(extpci, read, dword, u32 *, &ext_pci_swap)
MAKE_PCI_OPS(extpci, write, byte, u8, &ext_pci_swap)
MAKE_PCI_OPS(extpci, write, word, u16, &ext_pci_swap)
MAKE_PCI_OPS(extpci, write, dword, u32, &ext_pci_swap)
struct pci_ops ddb5476_ext_pci_ops = {
extpci_read_config_byte,
extpci_read_config_word,
extpci_read_config_dword,
extpci_write_config_byte,
extpci_write_config_word,
extpci_write_config_dword
};
arch/mips/pci/pci-ddb5476.c deleted 100644 → 0
View file @ eaff3888
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <asm/debug.h>
#include <asm/ddb5xxx/ddb5xxx.h>
static struct resource extpci_io_resource = {
.start = 0x1000, /* leave some room for ISA bus */
.end = DDB_PCI_IO_SIZE - 1,
.name = "pci IO space",
.flags = IORESOURCE_IO
};
static struct resource extpci_mem_resource = {
.start = DDB_PCI_MEM_BASE + 0x00100000, /* leave 1 MB for RTC */
.end = DDB_PCI_MEM_BASE + DDB_PCI_MEM_SIZE - 1,
.name = "pci memory space",
.flags = IORESOURCE_MEM
};
extern struct pci_ops ddb5476_ext_pci_ops;
struct pci_controller ddb5476_controller = {
.pci_ops = &ddb5476_ext_pci_ops,
.io_resource = &extpci_io_resource,
.mem_resource = &extpci_mem_resource
};
/*
* we fix up irqs based on the slot number.
* The first entry is at AD:11.
*
* This does not work for devices on sub-buses yet.
*/
/*
* temporary
*/
#define PCI_EXT_INTA 8
#define PCI_EXT_INTB 9
#define PCI_EXT_INTC 10
#define PCI_EXT_INTD 11
#define PCI_EXT_INTE 12
/*
* based on ddb5477 manual page 11
*/
#define MAX_SLOT_NUM 21
static unsigned char irq_map[MAX_SLOT_NUM] = {
[ 2] = 9, /* AD:13 USB */
[ 3] = 10, /* AD:14 PMU */
[ 5] = 0, /* AD:16 P2P bridge */
[ 6] = nile4_to_irq(PCI_EXT_INTB), /* AD:17 */
[ 7] = nile4_to_irq(PCI_EXT_INTC), /* AD:18 */
[ 8] = nile4_to_irq(PCI_EXT_INTD), /* AD:19 */
[ 9] = nile4_to_irq(PCI_EXT_INTA), /* AD:20 */
[13] = 14, /* AD:24 HD controller, M5229 */
};
int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
{
return irq_map[slot];
}
/* Do platform specific device initialization at pci_enable_device() time */
int pcibios_plat_dev_init(struct pci_dev *dev)
{
return 0;
}
void __init ddb_pci_reset_bus(void)
{
u32 temp;
/*
* I am not sure about the "official" procedure, the following
* steps work as far as I know:
* We first set PCI cold reset bit (bit 31) in PCICTRL-H.
* Then we clear the PCI warm reset bit (bit 30) to 0 in PCICTRL-H.
* The same is true for both PCI channels.
*/
temp = ddb_in32(DDB_PCICTRL + 4);
temp |= 0x80000000;
ddb_out32(DDB_PCICTRL + 4, temp);
temp &= ~0xc0000000;
ddb_out32(DDB_PCICTRL + 4, temp);
}
drivers/net/tulip/tulip_core.c
View file @ 470b1603
......@@ -1483,14 +1483,6 @@ static int __devinit tulip_init_one (struct pci_dev *pdev,
sa_offset = 2; /* Grrr, damn Matrox boards. */
multiport_cnt = 4;
}
#ifdef CONFIG_DDB5476
if ((pdev->bus->number == 0) && (PCI_SLOT(pdev->devfn) == 6)) {
/* DDB5476 MAC address in first EEPROM locations. */
sa_offset = 0;
/* No media table either */
tp->flags &= ~HAS_MEDIA_TABLE;
}
#endif
#ifdef CONFIG_DDB5477
if ((pdev->bus->number == 0) && (PCI_SLOT(pdev->devfn) == 4)) {
/* DDB5477 MAC address in first EEPROM locations. */
......
include/asm-mips/ddb5xxx/ddb5476.h deleted 100644 → 0
View file @ eaff3888
/*
* header file specific for ddb5476
*
* Copyright (C) 2001 MontaVista Software Inc.
* Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*
*/
/*
* Memory map (physical address)
*
* Note most of the following address must be properly aligned by the
* corresponding size. For example, if PCI_IO_SIZE is 16MB, then
* PCI_IO_BASE must be aligned along 16MB boundary.
*/
#define DDB_SDRAM_BASE 0x00000000
#define DDB_SDRAM_SIZE 0x04000000 /* 64MB */
#define DDB_DCS3_BASE 0x04000000 /* flash 1 */
#define DDB_DCS3_SIZE 0x01000000 /* 16MB */
#define DDB_DCS2_BASE 0x05000000 /* flash 2 */
#define DDB_DCS2_SIZE 0x01000000 /* 16MB */
#define DDB_PCI_IO_BASE 0x06000000
#define DDB_PCI_IO_SIZE 0x02000000 /* 32 MB */
#define DDB_PCI_MEM_BASE 0x08000000
#define DDB_PCI_MEM_SIZE 0x08000000 /* 128 MB */
#define DDB_DCS5_BASE 0x13000000 /* DDB status regs */
#define DDB_DCS5_SIZE 0x00200000 /* 2MB, 8-bit */
#define DDB_DCS4_BASE 0x14000000 /* DDB control regs */
#define DDB_DCS4_SIZE 0x00200000 /* 2MB, 8-bit */
#define DDB_INTCS_BASE 0x1fa00000 /* VRC5476 control regs */
#define DDB_INTCS_SIZE 0x00200000 /* 2MB */
#define DDB_BOOTCS_BASE 0x1fc00000 /* Boot ROM / EPROM /Flash */
#define DDB_BOOTCS_SIZE 0x00200000 /* 2 MB - doc says 4MB */
/* aliases */
#define DDB_PCI_CONFIG_BASE DDB_PCI_MEM_BASE
#define DDB_PCI_CONFIG_SIZE DDB_PCI_MEM_SIZE
/* PCI intr ack share PCIW0 with PCI IO */
#define DDB_PCI_IACK_BASE DDB_PCI_IO_BASE
/*
* Interrupt mapping
*
* We have three interrupt controllers:
*
* . CPU itself - 8 sources
* . i8259 - 16 sources
* . vrc5476 - 16 sources
*
* They connected as follows:
* all vrc5476 interrupts are routed to cpu IP2 (by software setting)
* all i2869 are routed to INTC in vrc5476 (by hardware connection)
*
* All VRC5476 PCI interrupts are level-triggered (no ack needed).
* All PCI irq but INTC are active low.
*/
/*
* irq number block assignment
*/
#define NUM_CPU_IRQ 8
#define NUM_I8259_IRQ 16
#define NUM_VRC5476_IRQ 16
#define DDB_IRQ_BASE 0
#define I8259_IRQ_BASE DDB_IRQ_BASE
#define VRC5476_IRQ_BASE (I8259_IRQ_BASE + NUM_I8259_IRQ)
#define CPU_IRQ_BASE (VRC5476_IRQ_BASE + NUM_VRC5476_IRQ)
/*
* vrc5476 irq defs, see page 52-64 of Vrc5074 system controller manual
*/
#define VRC5476_IRQ_CPCE 0 /* cpu parity error */
#define VRC5476_IRQ_CNTD 1 /* cpu no target */
#define VRC5476_IRQ_MCE 2 /* memory check error */
#define VRC5476_IRQ_DMA 3 /* DMA */
#define VRC5476_IRQ_UART 4 /* vrc5476 builtin UART, not used */
#define VRC5476_IRQ_WDOG 5 /* watchdog timer */
#define VRC5476_IRQ_GPT 6 /* general purpose timer */
#define VRC5476_IRQ_LBRT 7 /* local bus read timeout */
#define VRC5476_IRQ_INTA 8 /* PCI INT #A */
#define VRC5476_IRQ_INTB 9 /* PCI INT #B */
#define VRC5476_IRQ_INTC 10 /* PCI INT #C */
#define VRC5476_IRQ_INTD 11 /* PCI INT #D */
#define VRC5476_IRQ_INTE 12 /* PCI INT #E */
#define VRC5476_IRQ_RESERVED_13 13 /* reserved */
#define VRC5476_IRQ_PCIS 14 /* PCI SERR # */
#define VRC5476_IRQ_PCI 15 /* PCI internal error */
/*
* i2859 irq assignment
*/
#define I8259_IRQ_RESERVED_0 0
#define I8259_IRQ_KEYBOARD 1 /* M1543 default */
#define I8259_IRQ_CASCADE 2
#define I8259_IRQ_UART_B 3 /* M1543 default, may conflict with RTC according to schematic diagram */
#define I8259_IRQ_UART_A 4 /* M1543 default */
#define I8259_IRQ_PARALLEL 5 /* M1543 default */
#define I8259_IRQ_RESERVED_6 6
#define I8259_IRQ_RESERVED_7 7
#define I8259_IRQ_RTC 8 /* who set this? */
#define I8259_IRQ_USB 9 /* ddb_setup */
#define I8259_IRQ_PMU 10 /* ddb_setup */
#define I8259_IRQ_RESERVED_11 11
#define I8259_IRQ_RESERVED_12 12 /* m1543_irq_setup */
#define I8259_IRQ_RESERVED_13 13
#define I8259_IRQ_HDC1 14 /* default and ddb_setup */
#define I8259_IRQ_HDC2 15 /* default */
/*
* misc
*/
#define VRC5476_I8259_CASCADE VRC5476_IRQ_INTC
#define CPU_VRC5476_CASCADE 2
#define is_i8259_irq(irq) ((irq) < NUM_I8259_IRQ)
#define nile4_to_irq(n) ((n)+NUM_I8259_IRQ)
#define irq_to_nile4(n) ((n)-NUM_I8259_IRQ)
/*
* low-level irq functions
*/
#ifndef __ASSEMBLY__
extern void nile4_map_irq(int nile4_irq, int cpu_irq);
extern void nile4_map_irq_all(int cpu_irq);
extern void nile4_enable_irq(int nile4_irq);
extern void nile4_disable_irq(int nile4_irq);
extern void nile4_disable_irq_all(void);
extern u16 nile4_get_irq_stat(int cpu_irq);
extern void nile4_enable_irq_output(int cpu_irq);
extern void nile4_disable_irq_output(int cpu_irq);
extern void nile4_set_pci_irq_polarity(int pci_irq, int high);
extern void nile4_set_pci_irq_level_or_edge(int pci_irq, int level);
extern void nile4_clear_irq(int nile4_irq);
extern void nile4_clear_irq_mask(u32 mask);
extern u8 nile4_i8259_iack(void);
extern void nile4_dump_irq_status(void); /* Debug */
#endif /* !__ASSEMBLY__ */
include/asm-mips/ddb5xxx/ddb5xxx.h
View file @ 470b1603
......@@ -255,9 +255,7 @@ extern void ddb_pci_reset_bus(void);
/*
* include the board dependent part
*/
#if defined(CONFIG_DDB5476)
#include <asm/ddb5xxx/ddb5476.h>
#elif defined(CONFIG_DDB5477)
#if defined(CONFIG_DDB5477)
#include <asm/ddb5xxx/ddb5477.h>
#else
#error "Unknown DDB board!"
......
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