Commit 4805b7ce authored by zain wang's avatar zain wang Committed by Andrzej Hajda

drm/bridge: analogix_dp: Fix incorrect operations with register ANALOGIX_DP_FUNC_EN_1

Register ANALOGIX_DP_FUNC_EN_1(offset 0x18), Rockchip is different to
Exynos:

on Exynos edp phy,
BIT 7		MASTER_VID_FUNC_EN_N
BIT 6		reserved
BIT 5		SLAVE_VID_FUNC_EN_N

on Rockchip edp phy,
BIT 7		reserved
BIT 6		RK_VID_CAP_FUNC_EN_N
BIT 5		RK_VID_FIFO_FUNC_EN_N

So, we should do some private operations to Rockchip.

Cc: Tomasz Figa <tfiga@chromium.org>
Signed-off-by: default avatarzain wang <wzz@rock-chips.com>
Signed-off-by: default avatarSean Paul <seanpaul@chromium.org>
Signed-off-by: default avatarThierry Escande <thierry.escande@collabora.com>
Reviewed-by: default avatarAndrzej Hajda <a.hajda@samsung.com>
Signed-off-by: default avatarEnric Balletbo i Serra <enric.balletbo@collabora.com>
Tested-by: default avatarMarek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: default avatarArchit Taneja <architt@codeaurora.org>
Signed-off-by: default avatarAndrzej Hajda <a.hajda@samsung.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180423105003.9004-17-enric.balletbo@collabora.com
parent c4d3b1a2
...@@ -126,9 +126,14 @@ void analogix_dp_reset(struct analogix_dp_device *dp) ...@@ -126,9 +126,14 @@ void analogix_dp_reset(struct analogix_dp_device *dp)
analogix_dp_stop_video(dp); analogix_dp_stop_video(dp);
analogix_dp_enable_video_mute(dp, 0); analogix_dp_enable_video_mute(dp, 0);
reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N | if (dp->plat_data && is_rockchip(dp->plat_data->dev_type))
AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N | reg = RK_VID_CAP_FUNC_EN_N | RK_VID_FIFO_FUNC_EN_N |
HDCP_FUNC_EN_N | SW_FUNC_EN_N; SW_FUNC_EN_N;
else
reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N |
AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N |
HDCP_FUNC_EN_N | SW_FUNC_EN_N;
writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1); writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
reg = SSC_FUNC_EN_N | AUX_FUNC_EN_N | reg = SSC_FUNC_EN_N | AUX_FUNC_EN_N |
...@@ -971,8 +976,12 @@ void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp) ...@@ -971,8 +976,12 @@ void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp)
u32 reg; u32 reg;
reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_1); reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
reg &= ~(MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N); if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) {
reg |= MASTER_VID_FUNC_EN_N; reg &= ~(RK_VID_CAP_FUNC_EN_N | RK_VID_FIFO_FUNC_EN_N);
} else {
reg &= ~(MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N);
reg |= MASTER_VID_FUNC_EN_N;
}
writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1); writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
......
...@@ -127,7 +127,9 @@ ...@@ -127,7 +127,9 @@
/* ANALOGIX_DP_FUNC_EN_1 */ /* ANALOGIX_DP_FUNC_EN_1 */
#define MASTER_VID_FUNC_EN_N (0x1 << 7) #define MASTER_VID_FUNC_EN_N (0x1 << 7)
#define RK_VID_CAP_FUNC_EN_N (0x1 << 6)
#define SLAVE_VID_FUNC_EN_N (0x1 << 5) #define SLAVE_VID_FUNC_EN_N (0x1 << 5)
#define RK_VID_FIFO_FUNC_EN_N (0x1 << 5)
#define AUD_FIFO_FUNC_EN_N (0x1 << 4) #define AUD_FIFO_FUNC_EN_N (0x1 << 4)
#define AUD_FUNC_EN_N (0x1 << 3) #define AUD_FUNC_EN_N (0x1 << 3)
#define HDCP_FUNC_EN_N (0x1 << 2) #define HDCP_FUNC_EN_N (0x1 << 2)
......
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