Commit 4869a147 authored by Sergei Shtylyov's avatar Sergei Shtylyov Committed by David S. Miller

sh_eth: TSU_QTAG0/1 registers the same as TSU_QTAGM0/1

The TSU_QTAG0/1 registers found in the Gigabit Ether controllers actually
have the same long name  as the TSU_QTAGM0/1 registers in the early Ether
controllers:  Qtag Addition/Deletion Set Register (Port 0/1 to 1/0); thus
there's no need to make a difference in sh_eth_tsu_init() between those
controllers. Unfortunately, we can't just remove TSU_QTAG0/1 from the
register *enum* because that would break the ethtool register dump...

Fixes: b0ca2a21 ("sh_eth: Add support of SH7763 to sh_eth")
Signed-off-by: default avatarSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 3adc1c63
...@@ -123,8 +123,8 @@ static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = { ...@@ -123,8 +123,8 @@ static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
[TSU_FWSL0] = 0x0030, [TSU_FWSL0] = 0x0030,
[TSU_FWSL1] = 0x0034, [TSU_FWSL1] = 0x0034,
[TSU_FWSLC] = 0x0038, [TSU_FWSLC] = 0x0038,
[TSU_QTAG0] = 0x0040, [TSU_QTAGM0] = 0x0040,
[TSU_QTAG1] = 0x0044, [TSU_QTAGM1] = 0x0044,
[TSU_FWSR] = 0x0050, [TSU_FWSR] = 0x0050,
[TSU_FWINMK] = 0x0054, [TSU_FWINMK] = 0x0054,
[TSU_ADQT0] = 0x0048, [TSU_ADQT0] = 0x0048,
...@@ -2097,8 +2097,6 @@ static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf) ...@@ -2097,8 +2097,6 @@ static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf)
add_tsu_reg(TSU_FWSL0); add_tsu_reg(TSU_FWSL0);
add_tsu_reg(TSU_FWSL1); add_tsu_reg(TSU_FWSL1);
add_tsu_reg(TSU_FWSLC); add_tsu_reg(TSU_FWSLC);
add_tsu_reg(TSU_QTAG0);
add_tsu_reg(TSU_QTAG1);
add_tsu_reg(TSU_QTAGM0); add_tsu_reg(TSU_QTAGM0);
add_tsu_reg(TSU_QTAGM1); add_tsu_reg(TSU_QTAGM1);
add_tsu_reg(TSU_FWSR); add_tsu_reg(TSU_FWSR);
...@@ -2934,13 +2932,8 @@ static void sh_eth_tsu_init(struct sh_eth_private *mdp) ...@@ -2934,13 +2932,8 @@ static void sh_eth_tsu_init(struct sh_eth_private *mdp)
sh_eth_tsu_write(mdp, 0, TSU_FWSL0); sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
sh_eth_tsu_write(mdp, 0, TSU_FWSL1); sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC); sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
if (sh_eth_is_gether(mdp)) { sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
sh_eth_tsu_write(mdp, 0, TSU_QTAG0); /* Disable QTAG(0->1) */ sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
sh_eth_tsu_write(mdp, 0, TSU_QTAG1); /* Disable QTAG(1->0) */
} else {
sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
}
sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */ sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */ sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */ sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
......
...@@ -118,8 +118,8 @@ enum { ...@@ -118,8 +118,8 @@ enum {
TSU_FWSL0, TSU_FWSL0,
TSU_FWSL1, TSU_FWSL1,
TSU_FWSLC, TSU_FWSLC,
TSU_QTAG0, TSU_QTAG0, /* Same as TSU_QTAGM0 */
TSU_QTAG1, TSU_QTAG1, /* Same as TSU_QTAGM1 */
TSU_QTAGM0, TSU_QTAGM0,
TSU_QTAGM1, TSU_QTAGM1,
TSU_FWSR, TSU_FWSR,
......
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