Commit 487234cc authored by Florian Fainelli's avatar Florian Fainelli Committed by David S. Miller

net: systemport: Correctly set TSB endian for host

Similarly to how we configure the RSB (Receive Status Block) we also
need to set the TSB (Transmit Status Block) based on the host endian.
This was missing from the commit indicated below.

Fixes: 389a06bc ("net: systemport: Set correct RSB endian bits based on host")
Signed-off-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent d49e3a9f
...@@ -1392,6 +1392,19 @@ static int bcm_sysport_init_tx_ring(struct bcm_sysport_priv *priv, ...@@ -1392,6 +1392,19 @@ static int bcm_sysport_init_tx_ring(struct bcm_sysport_priv *priv,
tdma_writel(priv, RING_IGNORE_STATUS, TDMA_DESC_RING_MAPPING(index)); tdma_writel(priv, RING_IGNORE_STATUS, TDMA_DESC_RING_MAPPING(index));
tdma_writel(priv, 0, TDMA_DESC_RING_PCP_DEI_VID(index)); tdma_writel(priv, 0, TDMA_DESC_RING_PCP_DEI_VID(index));
/* Do not use tdma_control_bit() here because TSB_SWAP1 collides
* with the original definition of ACB_ALGO
*/
reg = tdma_readl(priv, TDMA_CONTROL);
if (priv->is_lite)
reg &= ~BIT(TSB_SWAP1);
/* Set a correct TSB format based on host endian */
if (!IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
reg |= tdma_control_bit(priv, TSB_SWAP0);
else
reg &= ~tdma_control_bit(priv, TSB_SWAP0);
tdma_writel(priv, reg, TDMA_CONTROL);
/* Program the number of descriptors as MAX_THRESHOLD and half of /* Program the number of descriptors as MAX_THRESHOLD and half of
* its size for the hysteresis trigger * its size for the hysteresis trigger
*/ */
......
...@@ -449,7 +449,8 @@ struct bcm_rsb { ...@@ -449,7 +449,8 @@ struct bcm_rsb {
/* Uses 2 bits on SYSTEMPORT Lite and shifts everything by 1 bit, we /* Uses 2 bits on SYSTEMPORT Lite and shifts everything by 1 bit, we
* keep the SYSTEMPORT layout here and adjust with tdma_control_bit() * keep the SYSTEMPORT layout here and adjust with tdma_control_bit()
*/ */
#define TSB_SWAP 2 #define TSB_SWAP0 2
#define TSB_SWAP1 3
#define ACB_ALGO 3 #define ACB_ALGO 3
#define BUF_DATA_OFFSET_SHIFT 4 #define BUF_DATA_OFFSET_SHIFT 4
#define BUF_DATA_OFFSET_MASK 0x3ff #define BUF_DATA_OFFSET_MASK 0x3ff
......
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