Merge bk://bk.arm.linux.org.uk/linux-2.6-serial

into ppc970.osdl.org:/home/torvalds/v2.6/linux

arch/arm/kernel/debug.S

@@ -315,7 +315,7 @@
 
 #elif defined(CONFIG_ARCH_INTEGRATOR)
 
-#include <asm/hardware/serial_amba.h>
+#include <asm/hardware/amba_serial.h>
 
 		.macro	addruart,rx
 		mrc	p15, 0, \rx, c1, c0
@@ -326,7 +326,7 @@
 		.endm
 
 		.macro	senduart,rd,rx
-		strb	\rd, [\rx, #AMBA_UARTDR]
+		strb	\rd, [\rx, #UART01x_DR]
 		.endm
 
 		.macro	waituart,rd,rx

drivers/serial/8250.c

@@ -170,7 +170,8 @@ static const struct serial_uart_config uart_config[PORT_MAX_8250+1] = {
 	{ "ST16654",	64,	UART_CLEAR_FIFO | UART_USE_FIFO | UART_STARTECH },
 	{ "XR16850",	128,	UART_CLEAR_FIFO | UART_USE_FIFO | UART_STARTECH },
 	{ "RSA",	2048,	UART_CLEAR_FIFO | UART_USE_FIFO },
-	{ "NS16550A",	16,	UART_CLEAR_FIFO | UART_USE_FIFO | UART_NATSEMI }
+	{ "NS16550A",	16,	UART_CLEAR_FIFO | UART_USE_FIFO | UART_NATSEMI },
+	{ "XScale",	32,	UART_CLEAR_FIFO | UART_USE_FIFO  },
 };
 
 static _INLINE_ unsigned int serial_in(struct uart_8250_port *up, int offset)
@@ -1512,6 +1513,8 @@ serial8250_set_termios(struct uart_port *port, struct termios *termios,
 	up->ier &= ~UART_IER_MSI;
 	if (UART_ENABLE_MS(&up->port, termios->c_cflag))
 		up->ier |= UART_IER_MSI;
+	if (up->port.type == PORT_XSCALE)
+		up->ier |= UART_IER_UUE | UART_IER_RTOIE;
 
 	serial_out(up, UART_IER, up->ier);
 
@@ -1953,7 +1956,11 @@ serial8250_console_write(struct console *co, const char *s, unsigned int count)
 	 *	First save the UER then disable the interrupts
 	 */
 	ier = serial_in(up, UART_IER);
-	serial_out(up, UART_IER, 0);
+
+	if (up->port.type == PORT_XSCALE)
+		serial_out(up, UART_IER, UART_IER_UUE);
+	else
+		serial_out(up, UART_IER, 0);
 
 	/*
 	 *	Now, do each character

drivers/serial/Kconfig

@@ -174,19 +174,19 @@ config SERIAL_8250_ACORN
 	  system, say Y to this option.  The driver can handle 1, 2, or 3 port
 	  cards.  If unsure, say N.
 
-config SERIAL_AMBA
-	tristate "ARM AMBA serial port support"
+config SERIAL_AMBA_PL010
+	tristate "ARM AMBA PL010 serial port support"
 	depends on ARM_AMBA
 	select SERIAL_CORE
 	help
-	  This selects the ARM(R) AMBA(R) PrimeCell UART.  If you have an
-	  Integrator platform, say Y or M here.
+	  This selects the ARM(R) AMBA(R) PrimeCell PL010 UART.  If you have
+	  an Integrator/AP or Integrator/PP2 platform, say Y or M here.
 
 	  If unsure, say N.
 
-config SERIAL_AMBA_CONSOLE
+config SERIAL_AMBA_PL010_CONSOLE
 	bool "Support for console on AMBA serial port"
-	depends on SERIAL_AMBA=y
+	depends on SERIAL_AMBA_PL010=y
 	select SERIAL_CORE_CONSOLE
 	---help---
 	  Say Y here if you wish to use an AMBA PrimeCell UART as the system
@@ -200,10 +200,32 @@ config SERIAL_AMBA_CONSOLE
 	  your boot loader (lilo or loadlin) about how to pass options to the
 	  kernel at boot time.)
 
-config SERIAL_INTEGRATOR
-	bool
-	depends on SERIAL_AMBA && ARCH_INTEGRATOR
-	default y
+config SERIAL_AMBA_PL011
+	tristate "ARM AMBA PL011 serial port support"
+	depends on ARM_AMBA
+	select SERIAL_CORE
+	help
+	  This selects the ARM(R) AMBA(R) PrimeCell PL010 UART.  If you have
+	  an Integrator/PP2, Integrator/CP or Versatile platform, say Y or M
+	  here.
+
+	  If unsure, say N.
+
+config SERIAL_AMBA_PL011_CONSOLE
+	bool "Support for console on AMBA serial port"
+	depends on SERIAL_AMBA_PL011=y
+	select SERIAL_CORE_CONSOLE
+	---help---
+	  Say Y here if you wish to use an AMBA PrimeCell UART as the system
+	  console (the system console is the device which receives all kernel
+	  messages and warnings and which allows logins in single user mode).
+
+	  Even if you say Y here, the currently visible framebuffer console
+	  (/dev/tty0) will still be used as the system console by default, but
+	  you can alter that using a kernel command line option such as
+	  "console=ttyAM0". (Try "man bootparam" or see the documentation of
+	  your boot loader (lilo or loadlin) about how to pass options to the
+	  kernel at boot time.)
 
 config SERIAL_CLPS711X
 	tristate "CLPS711X serial port support"

drivers/serial/Makefile

@@ -16,7 +16,8 @@ obj-$(CONFIG_SERIAL_21285) += 21285.o
 obj-$(CONFIG_SERIAL_8250) += 8250.o $(serial-8250-y)
 obj-$(CONFIG_SERIAL_8250_CS) += serial_cs.o
 obj-$(CONFIG_SERIAL_8250_ACORN) += 8250_acorn.o
-obj-$(CONFIG_SERIAL_AMBA) += amba.o
+obj-$(CONFIG_SERIAL_AMBA_PL010) += amba-pl010.o
+obj-$(CONFIG_SERIAL_AMBA_PL011) += amba-pl011.o
 obj-$(CONFIG_SERIAL_CLPS711X) += clps711x.o
 obj-$(CONFIG_SERIAL_PXA) += pxa.o
 obj-$(CONFIG_SERIAL_SA1100) += sa1100.o

include/asm-arm/hardware/amba_serial.h

+/*
+ *  linux/include/asm-arm/hardware/serial_amba.h
+ *
+ *  Internal header file for AMBA serial ports
+ *
+ *  Copyright (C) ARM Limited
+ *  Copyright (C) 2000 Deep Blue Solutions Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef ASM_ARM_HARDWARE_SERIAL_AMBA_H
+#define ASM_ARM_HARDWARE_SERIAL_AMBA_H
+
+/* -------------------------------------------------------------------------------
+ *  From AMBA UART (PL010) Block Specification
+ * -------------------------------------------------------------------------------
+ *  UART Register Offsets.
+ */
+#define UART01x_DR		0x00	/* Data read or written from the interface. */
+#define UART01x_RSR		0x04	/* Receive status register (Read). */
+#define UART01x_ECR		0x04	/* Error clear register (Write). */
+#define UART010_LCRH		0x08	/* Line control register, high byte. */
+#define UART010_LCRM		0x0C	/* Line control register, middle byte. */
+#define UART010_LCRL		0x10	/* Line control register, low byte. */
+#define UART010_CR		0x14	/* Control register. */
+#define UART01x_FR		0x18	/* Flag register (Read only). */
+#define UART010_IIR		0x1C	/* Interrupt indentification register (Read). */
+#define UART010_ICR		0x1C	/* Interrupt clear register (Write). */
+#define UART01x_ILPR		0x20	/* IrDA low power counter register. */
+#define UART011_IBRD		0x24	/* Integer baud rate divisor register. */
+#define UART011_FBRD		0x28	/* Fractional baud rate divisor register. */
+#define UART011_LCRH		0x2c	/* Line control register. */
+#define UART011_CR		0x30	/* Control register. */
+#define UART011_IFLS		0x34	/* Interrupt fifo level select. */
+#define UART011_IMSC		0x38	/* Interrupt mask. */
+#define UART011_RIS		0x3c	/* Raw interrupt status. */
+#define UART011_MIS		0x40	/* Masked interrupt status. */
+#define UART011_ICR		0x44	/* Interrupt clear register. */
+#define UART011_DMACR		0x48	/* DMA control register. */
+
+#define UART01x_RSR_OE 		0x08
+#define UART01x_RSR_BE 		0x04
+#define UART01x_RSR_PE 		0x02
+#define UART01x_RSR_FE 		0x01
+
+#define UART011_FR_RI		0x100
+#define UART011_FR_TXFE		0x080
+#define UART011_FR_RXFF		0x040
+#define UART01x_FR_TXFF		0x020
+#define UART01x_FR_RXFE		0x010
+#define UART01x_FR_BUSY		0x008
+#define UART01x_FR_DCD 		0x004
+#define UART01x_FR_DSR 		0x002
+#define UART01x_FR_CTS 		0x001
+#define UART01x_FR_TMSK		(UART01x_FR_TXFF + UART01x_FR_BUSY)
+
+#define UART011_CR_CTSEN	0x8000	/* CTS hardware flow control */
+#define UART011_CR_RTSEN	0x4000	/* RTS hardware flow control */
+#define UART011_CR_OUT2		0x2000	/* OUT2 */
+#define UART011_CR_OUT1		0x1000	/* OUT1 */
+#define UART011_CR_RTS		0x0800	/* RTS */
+#define UART011_CR_DTR		0x0400	/* DTR */
+#define UART011_CR_RXE		0x0200	/* receive enable */
+#define UART011_CR_TXE		0x0100	/* transmit enable */
+#define UART011_CR_LBE		0x0080	/* loopback enable */
+#define UART010_CR_RTIE		0x0040
+#define UART010_CR_TIE 		0x0020
+#define UART010_CR_RIE 		0x0010
+#define UART010_CR_MSIE		0x0008
+#define UART01x_CR_IIRLP	0x0004	/* SIR low power mode */
+#define UART01x_CR_SIREN	0x0002	/* SIR enable */
+#define UART01x_CR_UARTEN	0x0001	/* UART enable */
+ 
+#define UART011_LCRH_SPS	0x80
+#define UART01x_LCRH_WLEN_8	0x60
+#define UART01x_LCRH_WLEN_7	0x40
+#define UART01x_LCRH_WLEN_6	0x20
+#define UART01x_LCRH_WLEN_5	0x00
+#define UART01x_LCRH_FEN	0x10
+#define UART01x_LCRH_STP2	0x08
+#define UART01x_LCRH_EPS	0x04
+#define UART01x_LCRH_PEN	0x02
+#define UART01x_LCRH_BRK	0x01
+
+#define UART010_IIR_RTIS	0x08
+#define UART010_IIR_TIS		0x04
+#define UART010_IIR_RIS		0x02
+#define UART010_IIR_MIS		0x01
+
+#define UART011_IFLS_RX1_8	(0 << 3)
+#define UART011_IFLS_RX2_8	(1 << 3)
+#define UART011_IFLS_RX4_8	(2 << 3)
+#define UART011_IFLS_RX6_8	(3 << 3)
+#define UART011_IFLS_RX7_8	(4 << 3)
+#define UART011_IFLS_TX1_8	(0 << 0)
+#define UART011_IFLS_TX2_8	(1 << 0)
+#define UART011_IFLS_TX4_8	(2 << 0)
+#define UART011_IFLS_TX6_8	(3 << 0)
+#define UART011_IFLS_TX7_8	(4 << 0)
+
+#define UART011_OEIM		(1 << 10)	/* overrun error interrupt mask */
+#define UART011_BEIM		(1 << 9)	/* break error interrupt mask */
+#define UART011_PEIM		(1 << 8)	/* parity error interrupt mask */
+#define UART011_FEIM		(1 << 7)	/* framing error interrupt mask */
+#define UART011_RTIM		(1 << 6)	/* receive timeout interrupt mask */
+#define UART011_TXIM		(1 << 5)	/* transmit interrupt mask */
+#define UART011_RXIM		(1 << 4)	/* receive interrupt mask */
+#define UART011_DSRMIM		(1 << 3)	/* DSR interrupt mask */
+#define UART011_DCDMIM		(1 << 2)	/* DCD interrupt mask */
+#define UART011_CTSMIM		(1 << 1)	/* CTS interrupt mask */
+#define UART011_RIMIM		(1 << 0)	/* RI interrupt mask */
+
+#define UART011_OEIS		(1 << 10)	/* overrun error interrupt status */
+#define UART011_BEIS		(1 << 9)	/* break error interrupt status */
+#define UART011_PEIS		(1 << 8)	/* parity error interrupt status */
+#define UART011_FEIS		(1 << 7)	/* framing error interrupt status */
+#define UART011_RTIS		(1 << 6)	/* receive timeout interrupt status */
+#define UART011_TXIS		(1 << 5)	/* transmit interrupt status */
+#define UART011_RXIS		(1 << 4)	/* receive interrupt status */
+#define UART011_DSRMIS		(1 << 3)	/* DSR interrupt status */
+#define UART011_DCDMIS		(1 << 2)	/* DCD interrupt status */
+#define UART011_CTSMIS		(1 << 1)	/* CTS interrupt status */
+#define UART011_RIMIS		(1 << 0)	/* RI interrupt status */
+
+#define UART011_OEIC		(1 << 10)	/* overrun error interrupt clear */
+#define UART011_BEIC		(1 << 9)	/* break error interrupt clear */
+#define UART011_PEIC		(1 << 8)	/* parity error interrupt clear */
+#define UART011_FEIC		(1 << 7)	/* framing error interrupt clear */
+#define UART011_RTIC		(1 << 6)	/* receive timeout interrupt clear */
+#define UART011_TXIC		(1 << 5)	/* transmit interrupt clear */
+#define UART011_RXIC		(1 << 4)	/* receive interrupt clear */
+#define UART011_DSRMIC		(1 << 3)	/* DSR interrupt clear */
+#define UART011_DCDMIC		(1 << 2)	/* DCD interrupt clear */
+#define UART011_CTSMIC		(1 << 1)	/* CTS interrupt clear */
+#define UART011_RIMIC		(1 << 0)	/* RI interrupt clear */
+
+#define UART011_DMAONERR	(1 << 2)	/* disable dma on error */
+#define UART011_TXDMAE		(1 << 1)	/* enable transmit dma */
+#define UART011_RXDMAE		(1 << 0)	/* enable receive dma */
+
+#define UART01x_RSR_ANY		(UART01x_RSR_OE|UART01x_RSR_BE|UART01x_RSR_PE|UART01x_RSR_FE)
+#define UART01x_FR_MODEM_ANY	(UART01x_FR_DCD|UART01x_FR_DSR|UART01x_FR_CTS)
+
+#endif

include/asm-arm/hardware/serial_amba.h

-/*
- *  linux/include/asm-arm/hardware/serial_amba.h
- *
- *  Internal header file for AMBA serial ports
- *
- *  Copyright (C) ARM Limited
- *  Copyright (C) 2000 Deep Blue Solutions Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef ASM_ARM_HARDWARE_SERIAL_AMBA_H
-#define ASM_ARM_HARDWARE_SERIAL_AMBA_H
-
-/* -------------------------------------------------------------------------------
- *  From AMBA UART (PL010) Block Specification (ARM-0001-CUST-DSPC-A03)
- * -------------------------------------------------------------------------------
- *  UART Register Offsets.
- */
-#define AMBA_UARTDR                     0x00	 /*  Data read or written from the interface. */
-#define AMBA_UARTRSR                    0x04	 /*  Receive status register (Read). */
-#define AMBA_UARTECR                    0x04	 /*  Error clear register (Write). */
-#define AMBA_UARTLCR_H                  0x08	 /*  Line control register, high byte. */
-#define AMBA_UARTLCR_M                  0x0C	 /*  Line control register, middle byte. */
-#define AMBA_UARTLCR_L                  0x10	 /*  Line control register, low byte. */
-#define AMBA_UARTCR                     0x14	 /*  Control register. */
-#define AMBA_UARTFR                     0x18	 /*  Flag register (Read only). */
-#define AMBA_UARTIIR                    0x1C	 /*  Interrupt indentification register (Read). */
-#define AMBA_UARTICR                    0x1C	 /*  Interrupt clear register (Write). */
-#define AMBA_UARTILPR                   0x20	 /*  IrDA low power counter register. */
-
-#define AMBA_UARTRSR_OE                 0x08
-#define AMBA_UARTRSR_BE                 0x04
-#define AMBA_UARTRSR_PE                 0x02
-#define AMBA_UARTRSR_FE                 0x01
-
-#define AMBA_UARTFR_TXFF                0x20
-#define AMBA_UARTFR_RXFE                0x10
-#define AMBA_UARTFR_BUSY                0x08
-#define AMBA_UARTFR_DCD			0x04
-#define AMBA_UARTFR_DSR			0x02
-#define AMBA_UARTFR_CTS			0x01
-#define AMBA_UARTFR_TMSK                (AMBA_UARTFR_TXFF + AMBA_UARTFR_BUSY)
- 
-#define AMBA_UARTCR_RTIE                0x40
-#define AMBA_UARTCR_TIE                 0x20
-#define AMBA_UARTCR_RIE                 0x10
-#define AMBA_UARTCR_MSIE                0x08
-#define AMBA_UARTCR_IIRLP               0x04
-#define AMBA_UARTCR_SIREN               0x02
-#define AMBA_UARTCR_UARTEN              0x01
- 
-#define AMBA_UARTLCR_H_WLEN_8           0x60
-#define AMBA_UARTLCR_H_WLEN_7           0x40
-#define AMBA_UARTLCR_H_WLEN_6           0x20
-#define AMBA_UARTLCR_H_WLEN_5           0x00
-#define AMBA_UARTLCR_H_FEN              0x10
-#define AMBA_UARTLCR_H_STP2             0x08
-#define AMBA_UARTLCR_H_EPS              0x04
-#define AMBA_UARTLCR_H_PEN              0x02
-#define AMBA_UARTLCR_H_BRK              0x01
-
-#define AMBA_UARTIIR_RTIS               0x08
-#define AMBA_UARTIIR_TIS                0x04
-#define AMBA_UARTIIR_RIS                0x02
-#define AMBA_UARTIIR_MIS                0x01
-
-#define ARM_BAUD_460800                 1
-#define ARM_BAUD_230400                 3
-#define ARM_BAUD_115200                 7
-#define ARM_BAUD_57600                  15
-#define ARM_BAUD_38400                  23
-#define ARM_BAUD_19200                  47
-#define ARM_BAUD_14400                  63
-#define ARM_BAUD_9600                   95
-#define ARM_BAUD_4800                   191
-#define ARM_BAUD_2400                   383
-#define ARM_BAUD_1200                   767
-
-#define AMBA_UARTRSR_ANY	(AMBA_UARTRSR_OE|AMBA_UARTRSR_BE|AMBA_UARTRSR_PE|AMBA_UARTRSR_FE)
-#define AMBA_UARTFR_MODEM_ANY	(AMBA_UARTFR_DCD|AMBA_UARTFR_DSR|AMBA_UARTFR_CTS)
-
-#endif

include/linux/serial_core.h

@@ -36,7 +36,8 @@
 #define PORT_16850	12
 #define PORT_RSA	13
 #define PORT_NS16550A	14
-#define PORT_MAX_8250	14	/* max port ID */
+#define PORT_XSCALE	15
+#define PORT_MAX_8250	15	/* max port ID */
 
 /*
  * ARM specific type numbers.  These are not currently guaranteed

include/linux/serial_reg.h

@@ -142,7 +142,7 @@
 #define UART_MSR_ANY_DELTA 0x0F	/* Any of the delta bits! */
 
 /*
- * The Intel PXA2xx chip defines those bits
+ * The Intel XScale on-chip UARTs define these bits
  */
 #define UART_IER_DMAE	0x80	/* DMA Requests Enable */
 #define UART_IER_UUE	0x40	/* UART Unit Enable */