Commit 4a066c6b authored by Dave Airlie's avatar Dave Airlie

drm: add R200_EMIT_TCL_POINT_SPRITE_CNTL

add support for new packet. won't be used until hyper-z version
number increase.
Signed-off-by: default avatarDave Airlie <airlied@linux.ie>
parent a174c062
......@@ -145,7 +145,8 @@
#define RADEON_EMIT_PP_TEX_SIZE_1 74
#define RADEON_EMIT_PP_TEX_SIZE_2 75
#define R200_EMIT_RB3D_BLENDCOLOR 76
#define RADEON_MAX_STATE_PACKETS 77
#define R200_EMIT_TCL_POINT_SPRITE_CNTL 77
#define RADEON_MAX_STATE_PACKETS 78
/* Commands understood by cmd_buffer ioctl. More can be added but
......
......@@ -799,6 +799,8 @@ extern int radeon_postcleanup( struct drm_device *dev );
#define R200_RB3D_BLENDCOLOR 0x3218
#define R200_SE_TCL_POINT_SPRITE_CNTL 0x22c4
/* Constants */
#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
......
......@@ -232,6 +232,7 @@ static __inline__ int radeon_check_and_fixup_packets( drm_radeon_private_t *dev_
case RADEON_EMIT_PP_TEX_SIZE_1:
case RADEON_EMIT_PP_TEX_SIZE_2:
case R200_EMIT_RB3D_BLENDCOLOR:
case R200_EMIT_TCL_POINT_SPRITE_CNTL:
/* These packets don't contain memory offsets */
break;
......@@ -596,6 +597,7 @@ static struct {
{ RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1" },
{ RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2" },
{ R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR" },
{ R200_SE_TCL_POINT_SPRITE_CNTL, 1, "R200_SE_TCL_POINT_SPRITE_CNTL" },
};
......
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