Commit 4a531488 authored by Chuanxiao Dong's avatar Chuanxiao Dong Committed by Zhenyu Wang

drm/i915/gvt: fix wrong offset when loading RCS mocs

Fix the wrong offset of the RCS specific mocs

Fixes: 17865713 ("drm/i915/gvt: vGPU context switch")
Signed-off-by: default avatarChuanxiao Dong <chuanxiao.dong@intel.com>
Signed-off-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
parent 975629c3
...@@ -207,7 +207,7 @@ static void load_mocs(struct intel_vgpu *vgpu, int ring_id) ...@@ -207,7 +207,7 @@ static void load_mocs(struct intel_vgpu *vgpu, int ring_id)
l3_offset.reg = 0xb020; l3_offset.reg = 0xb020;
for (i = 0; i < 32; i++) { for (i = 0; i < 32; i++) {
gen9_render_mocs_L3[i] = I915_READ(l3_offset); gen9_render_mocs_L3[i] = I915_READ(l3_offset);
I915_WRITE(l3_offset, vgpu_vreg(vgpu, offset)); I915_WRITE(l3_offset, vgpu_vreg(vgpu, l3_offset));
POSTING_READ(l3_offset); POSTING_READ(l3_offset);
l3_offset.reg += 4; l3_offset.reg += 4;
} }
......
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