Commit 4a878b9f authored by Sujith Manoharan's avatar Sujith Manoharan Committed by John W. Linville

ath9k: Initialize baseband for DFS channels

Certain baseband registers require different values
to be programmed when operating in a DFS channel to
ensure that radar detection works correctly. This
is required for AR9300, AR9340 and AR9580.
Signed-off-by: default avatarSujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 98b2e1fd
...@@ -152,6 +152,8 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah) ...@@ -152,6 +152,8 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
ar9340Modes_fast_clock_1p0); ar9340Modes_fast_clock_1p0);
INIT_INI_ARRAY(&ah->iniCckfirJapan2484, INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
ar9340_1p0_baseband_core_txfir_coeff_japan_2484); ar9340_1p0_baseband_core_txfir_coeff_japan_2484);
INIT_INI_ARRAY(&ah->ini_dfs,
ar9340_1p0_baseband_postamble_dfs_channel);
if (!ah->is_clk_25mhz) if (!ah->is_clk_25mhz)
INIT_INI_ARRAY(&ah->iniAdditional, INIT_INI_ARRAY(&ah->iniAdditional,
...@@ -340,6 +342,8 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah) ...@@ -340,6 +342,8 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
ar9580_1p0_modes_fast_clock); ar9580_1p0_modes_fast_clock);
INIT_INI_ARRAY(&ah->iniCckfirJapan2484, INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
ar9580_1p0_baseband_core_txfir_coeff_japan_2484); ar9580_1p0_baseband_core_txfir_coeff_japan_2484);
INIT_INI_ARRAY(&ah->ini_dfs,
ar9580_1p0_baseband_postamble_dfs_channel);
} else if (AR_SREV_9565_11_OR_LATER(ah)) { } else if (AR_SREV_9565_11_OR_LATER(ah)) {
INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
ar9565_1p1_mac_core); ar9565_1p1_mac_core);
...@@ -458,6 +462,8 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah) ...@@ -458,6 +462,8 @@ static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
ar9300Modes_fast_clock_2p2); ar9300Modes_fast_clock_2p2);
INIT_INI_ARRAY(&ah->iniCckfirJapan2484, INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
ar9300_2p2_baseband_core_txfir_coeff_japan_2484); ar9300_2p2_baseband_core_txfir_coeff_japan_2484);
INIT_INI_ARRAY(&ah->ini_dfs,
ar9300_2p2_baseband_postamble_dfs_channel);
} }
} }
......
...@@ -1332,6 +1332,7 @@ static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah) ...@@ -1332,6 +1332,7 @@ static void ar9003_hw_ani_cache_ini_regs(struct ath_hw *ah)
static void ar9003_hw_set_radar_params(struct ath_hw *ah, static void ar9003_hw_set_radar_params(struct ath_hw *ah,
struct ath_hw_radar_conf *conf) struct ath_hw_radar_conf *conf)
{ {
unsigned int regWrites = 0;
u32 radar_0 = 0, radar_1 = 0; u32 radar_0 = 0, radar_1 = 0;
if (!conf) { if (!conf) {
...@@ -1358,6 +1359,11 @@ static void ar9003_hw_set_radar_params(struct ath_hw *ah, ...@@ -1358,6 +1359,11 @@ static void ar9003_hw_set_radar_params(struct ath_hw *ah,
REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); REG_SET_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
else else
REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA); REG_CLR_BIT(ah, AR_PHY_RADAR_EXT, AR_PHY_RADAR_EXT_ENA);
if (AR_SREV_9300(ah) || AR_SREV_9340(ah) || AR_SREV_9580(ah)) {
REG_WRITE_ARRAY(&ah->ini_dfs,
IS_CHAN_HT40(ah->curchan) ? 2 : 1, regWrites);
}
} }
static void ar9003_hw_set_radar_conf(struct ath_hw *ah) static void ar9003_hw_set_radar_conf(struct ath_hw *ah)
......
...@@ -864,6 +864,7 @@ struct ath_hw { ...@@ -864,6 +864,7 @@ struct ath_hw {
u32 gpio_mask; u32 gpio_mask;
u32 gpio_val; u32 gpio_val;
struct ar5416IniArray ini_dfs;
struct ar5416IniArray iniModes; struct ar5416IniArray iniModes;
struct ar5416IniArray iniCommon; struct ar5416IniArray iniCommon;
struct ar5416IniArray iniBB_RfGain; struct ar5416IniArray iniBB_RfGain;
......
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