Commit 4b71a570 authored by Paulo Zanoni's avatar Paulo Zanoni Committed by Daniel Vetter

drm/i915: fix DSPADDR Gen check

The first version of commit "drm/i915: there's no DSPADDR register on
Haswell" added 2 "!IS_HASWELL" checks. When reviewing the patch, Ben
suggested to make these checks more future-proof, so when Daniel
applied the patch he fixed the first check but not the second. This
commit makes the second check also "future-proof".
Signed-off-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent ad1c0b19
...@@ -9420,7 +9420,7 @@ intel_display_print_error_state(struct seq_file *m, ...@@ -9420,7 +9420,7 @@ intel_display_print_error_state(struct seq_file *m,
if (INTEL_INFO(dev)->gen <= 3) if (INTEL_INFO(dev)->gen <= 3)
seq_printf(m, " SIZE: %08x\n", error->plane[i].size); seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
seq_printf(m, " POS: %08x\n", error->plane[i].pos); seq_printf(m, " POS: %08x\n", error->plane[i].pos);
if (!IS_HASWELL(dev)) if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
seq_printf(m, " ADDR: %08x\n", error->plane[i].addr); seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
if (INTEL_INFO(dev)->gen >= 4) { if (INTEL_INFO(dev)->gen >= 4) {
seq_printf(m, " SURF: %08x\n", error->plane[i].surface); seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
......
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