Commit 4b9ffb5a authored by Joao Pinto's avatar Joao Pinto Committed by Martin K. Petersen

ufs: add support for DesignWare Controller

This patch has the goal to add support for DesignWare UFS Controller
specific operations.
Signed-off-by: default avatarJoao Pinto <jpinto@synopsys.com>
Reviewed-by: default avatarHannes Reinicke <hare@suse.de>
Signed-off-by: default avatarMartin K. Petersen <martin.petersen@oracle.com>
parent 79fcc033
......@@ -11770,6 +11770,12 @@ S: Supported
F: Documentation/scsi/ufs.txt
F: drivers/scsi/ufs/
UNIVERSAL FLASH STORAGE HOST CONTROLLER DRIVER DWC HOOKS
M: Joao Pinto <Joao.Pinto@synopsys.com>
L: linux-scsi@vger.kernel.org
S: Supported
F: drivers/scsi/ufs/*dwc*
UNSORTED BLOCK IMAGES (UBI)
M: Artem Bityutskiy <dedekind1@gmail.com>
M: Richard Weinberger <richard@nod.at>
......
/*
* UFS Host driver for Synopsys Designware Core
*
* Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com)
*
* Authors: Joao Pinto <jpinto@synopsys.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "ufshcd.h"
#include "unipro.h"
#include "ufshcd-dwc.h"
#include "ufshci-dwc.h"
int ufshcd_dwc_dme_set_attrs(struct ufs_hba *hba,
const struct ufshcd_dme_attr_val *v, int n)
{
int ret = 0;
int attr_node = 0;
for (attr_node = 0; attr_node < n; attr_node++) {
ret = ufshcd_dme_set_attr(hba, v[attr_node].attr_sel,
ATTR_SET_NOR, v[attr_node].mib_val, v[attr_node].peer);
if (ret)
return ret;
}
return 0;
}
EXPORT_SYMBOL(ufshcd_dwc_dme_set_attrs);
/**
* ufshcd_dwc_program_clk_div()
* This function programs the clk divider value. This value is needed to
* provide 1 microsecond tick to unipro layer.
* @hba: Private Structure pointer
* @divider_val: clock divider value to be programmed
*
*/
static void ufshcd_dwc_program_clk_div(struct ufs_hba *hba, u32 divider_val)
{
ufshcd_writel(hba, divider_val, DWC_UFS_REG_HCLKDIV);
}
/**
* ufshcd_dwc_link_is_up()
* Check if link is up
* @hba: private structure poitner
*
* Returns 0 on success, non-zero value on failure
*/
static int ufshcd_dwc_link_is_up(struct ufs_hba *hba)
{
int dme_result = 0;
ufshcd_dme_get(hba, UIC_ARG_MIB(VS_POWERSTATE), &dme_result);
if (dme_result == UFSHCD_LINK_IS_UP) {
ufshcd_set_link_active(hba);
return 0;
}
return 1;
}
/**
* ufshcd_dwc_connection_setup()
* This function configures both the local side (host) and the peer side
* (device) unipro attributes to establish the connection to application/
* cport.
* This function is not required if the hardware is properly configured to
* have this connection setup on reset. But invoking this function does no
* harm and should be fine even working with any ufs device.
*
* @hba: pointer to drivers private data
*
* Returns 0 on success non-zero value on failure
*/
static int ufshcd_dwc_connection_setup(struct ufs_hba *hba)
{
const struct ufshcd_dme_attr_val setup_attrs[] = {
{ UIC_ARG_MIB(T_CONNECTIONSTATE), 0, DME_LOCAL },
{ UIC_ARG_MIB(N_DEVICEID), 0, DME_LOCAL },
{ UIC_ARG_MIB(N_DEVICEID_VALID), 0, DME_LOCAL },
{ UIC_ARG_MIB(T_PEERDEVICEID), 1, DME_LOCAL },
{ UIC_ARG_MIB(T_PEERCPORTID), 0, DME_LOCAL },
{ UIC_ARG_MIB(T_TRAFFICCLASS), 0, DME_LOCAL },
{ UIC_ARG_MIB(T_CPORTFLAGS), 0x6, DME_LOCAL },
{ UIC_ARG_MIB(T_CPORTMODE), 1, DME_LOCAL },
{ UIC_ARG_MIB(T_CONNECTIONSTATE), 1, DME_LOCAL },
{ UIC_ARG_MIB(T_CONNECTIONSTATE), 0, DME_PEER },
{ UIC_ARG_MIB(N_DEVICEID), 1, DME_PEER },
{ UIC_ARG_MIB(N_DEVICEID_VALID), 1, DME_PEER },
{ UIC_ARG_MIB(T_PEERDEVICEID), 1, DME_PEER },
{ UIC_ARG_MIB(T_PEERCPORTID), 0, DME_PEER },
{ UIC_ARG_MIB(T_TRAFFICCLASS), 0, DME_PEER },
{ UIC_ARG_MIB(T_CPORTFLAGS), 0x6, DME_PEER },
{ UIC_ARG_MIB(T_CPORTMODE), 1, DME_PEER },
{ UIC_ARG_MIB(T_CONNECTIONSTATE), 1, DME_PEER }
};
return ufshcd_dwc_dme_set_attrs(hba, setup_attrs, ARRAY_SIZE(setup_attrs));
}
/**
* ufshcd_dwc_link_startup_notify()
* UFS Host DWC specific link startup sequence
* @hba: private structure poitner
* @status: Callback notify status
*
* Returns 0 on success, non-zero value on failure
*/
int ufshcd_dwc_link_startup_notify(struct ufs_hba *hba,
enum ufs_notify_change_status status)
{
int err = 0;
if (status == PRE_CHANGE) {
ufshcd_dwc_program_clk_div(hba, DWC_UFS_REG_HCLKDIV_DIV_125);
if (hba->vops->phy_initialization) {
err = hba->vops->phy_initialization(hba);
if (err) {
dev_err(hba->dev, "Phy setup failed (%d)\n",
err);
goto out;
}
}
} else { /* POST_CHANGE */
err = ufshcd_dwc_link_is_up(hba);
if (err) {
dev_err(hba->dev, "Link is not up\n");
goto out;
}
err = ufshcd_dwc_connection_setup(hba);
if (err)
dev_err(hba->dev, "Connection setup failed (%d)\n",
err);
}
out:
return err;
}
EXPORT_SYMBOL(ufshcd_dwc_link_startup_notify);
/*
* UFS Host driver for Synopsys Designware Core
*
* Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com)
*
* Authors: Joao Pinto <jpinto@synopsys.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef _UFSHCD_DWC_H
#define _UFSHCD_DWC_H
struct ufshcd_dme_attr_val {
u32 attr_sel;
u32 mib_val;
u8 peer;
};
int ufshcd_dwc_link_startup_notify(struct ufs_hba *hba,
enum ufs_notify_change_status status);
int ufshcd_dwc_dme_set_attrs(struct ufs_hba *hba,
const struct ufshcd_dme_attr_val *v, int n);
#endif /* End of Header */
......@@ -264,6 +264,7 @@ struct ufs_pwr_mode_info {
* @suspend: called during host controller PM callback
* @resume: called during host controller PM callback
* @dbg_register_dump: used to dump controller debug information
* @phy_initialization: used to initialize phys
*/
struct ufs_hba_variant_ops {
const char *name;
......@@ -285,6 +286,7 @@ struct ufs_hba_variant_ops {
int (*suspend)(struct ufs_hba *, enum ufs_pm_op);
int (*resume)(struct ufs_hba *, enum ufs_pm_op);
void (*dbg_register_dump)(struct ufs_hba *hba);
int (*phy_initialization)(struct ufs_hba *);
};
/* clock gating state */
......@@ -567,11 +569,16 @@ static inline bool ufshcd_can_autobkops_during_suspend(struct ufs_hba *hba)
static inline bool ufshcd_is_intr_aggr_allowed(struct ufs_hba *hba)
{
/* DWC UFS Core has the Interrupt aggregation feature but is not detectable*/
#ifndef CONFIG_SCSI_UFS_DWC
if ((hba->caps & UFSHCD_CAP_INTR_AGGR) &&
!(hba->quirks & UFSHCD_QUIRK_BROKEN_INTR_AGGR))
return true;
else
return false;
#else
return true;
#endif
}
#define ufshcd_writel(hba, val, reg) \
......
/*
* UFS Host driver for Synopsys Designware Core
*
* Copyright (C) 2015-2016 Synopsys, Inc. (www.synopsys.com)
*
* Authors: Joao Pinto <jpinto@synopsys.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef _UFSHCI_DWC_H
#define _UFSHCI_DWC_H
/* DWC HC UFSHCI specific Registers */
enum dwc_specific_registers {
DWC_UFS_REG_HCLKDIV = 0xFC,
};
/* Clock Divider Values: Hex equivalent of frequency in MHz */
enum clk_div_values {
DWC_UFS_REG_HCLKDIV_DIV_62_5 = 0x3e,
DWC_UFS_REG_HCLKDIV_DIV_125 = 0x7d,
DWC_UFS_REG_HCLKDIV_DIV_200 = 0xc8,
};
/* Selector Index */
enum selector_index {
SELIND_LN0_TX = 0x00,
SELIND_LN1_TX = 0x01,
SELIND_LN0_RX = 0x04,
SELIND_LN1_RX = 0x05,
};
#endif /* End of Header */
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