Commit 4bb2d100 authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'soc2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull "ARM: More SoC support updates" from Olof Johansson:
 "This branch contains a handful of updates of SoC base code that had
  dependencies on other external trees that have now been merged:

   * Support for the new EXYNOS5250 SoC from Samsung
   * SMP and power domain support for Tegra3 from NVIDIA
   * ux500 updates for exporting SoC information through sysfs"

Fix up trivial merge conflicts as per Olof.

* tag 'soc2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (30 commits)
  ARM: mach-shmobile: ap4evb: Reserve DMA memory for the frame buffer
  ARM: EXYNOS: Fix compilation error with mach-exynos4-dt board
  ARM: dts: add initial dts file for EXYNOS5250, SMDK5250
  ARM: EXYNOS: add support device tree enabled board file for EXYNOS5
  ARM: EXYNOS: add support ARCH_EXYNOS5 for EXYNOS5 SoCs
  ARM: EXYNOS: add support get_core_count() for EXYNOS5250
  ARM: EXYNOS: support EINT for EXYNOS4 and EXYNOS5
  ARM: EXYNOS: add interrupt definitions for EXYNOS5250
  ARM: EXYNOS: add support for EXYNOS5250 SoC
  ARM: EXYNOS: add support uart for EXYNOS4 and EXYNOS5
  ARM: EXYNOS: add initial setup-i2c0 for EXYNOS5
  ARM: EXYNOS: add clock part for EXYNOS5250 SoC
  ARM: EXYNOS: use exynos_init_uarts() instead of exynos4_init_uarts()
  ARM: EXYNOS: to declare static for mach-exynos/common.c
  ARM: EXYNOS: Add clkdev lookup entry for lcd clock
  ARM: dt: Explicitly configure all serial ports on Tegra Cardhu
  ARM: tegra: support for secondary cores on Tegra30
  ARM: tegra: support for Tegra30 CPU powerdomains
  ARM: tegra: add support for Tegra30 powerdomains
  ARM: tegra: export tegra_powergate_is_powered()
  ...
parents ff877c49 83fe628e
...@@ -180,6 +180,7 @@ machine-$(CONFIG_ARCH_S5P64X0) := s5p64x0 ...@@ -180,6 +180,7 @@ machine-$(CONFIG_ARCH_S5P64X0) := s5p64x0
machine-$(CONFIG_ARCH_S5PC100) := s5pc100 machine-$(CONFIG_ARCH_S5PC100) := s5pc100
machine-$(CONFIG_ARCH_S5PV210) := s5pv210 machine-$(CONFIG_ARCH_S5PV210) := s5pv210
machine-$(CONFIG_ARCH_EXYNOS4) := exynos machine-$(CONFIG_ARCH_EXYNOS4) := exynos
machine-$(CONFIG_ARCH_EXYNOS5) := exynos
machine-$(CONFIG_ARCH_SA1100) := sa1100 machine-$(CONFIG_ARCH_SA1100) := sa1100
machine-$(CONFIG_ARCH_SHARK) := shark machine-$(CONFIG_ARCH_SHARK) := shark
machine-$(CONFIG_ARCH_SHMOBILE) := shmobile machine-$(CONFIG_ARCH_SHMOBILE) := shmobile
......
/*
* SAMSUNG SMDK5250 board device tree source
*
* Copyright (c) 2012 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
/include/ "exynos5250.dtsi"
/ {
model = "SAMSUNG SMDK5250 board based on EXYNOS5250";
compatible = "samsung,smdk5250", "samsung,exynos5250";
memory {
reg = <0x40000000 0x80000000>;
};
chosen {
bootargs = "root=/dev/ram0 rw ramdisk=8192 console=ttySAC1,115200";
};
};
/*
* SAMSUNG EXYNOS5250 SoC device tree source
*
* Copyright (c) 2012 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* SAMSUNG EXYNOS5250 SoC device nodes are listed in this file.
* EXYNOS5250 based board files can include this file and provide
* values for board specfic bindings.
*
* Note: This file does not include device nodes for all the controllers in
* EXYNOS5250 SoC. As device tree coverage for EXYNOS5250 increases,
* additional nodes can be added to this file.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/include/ "skeleton.dtsi"
/ {
compatible = "samsung,exynos5250";
interrupt-parent = <&gic>;
gic:interrupt-controller@10490000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0x10490000 0x1000>, <0x10480000 0x100>;
};
watchdog {
compatible = "samsung,s3c2410-wdt";
reg = <0x101D0000 0x100>;
interrupts = <0 42 0>;
};
rtc {
compatible = "samsung,s3c6410-rtc";
reg = <0x101E0000 0x100>;
interrupts = <0 43 0>, <0 44 0>;
};
sdhci@12200000 {
compatible = "samsung,exynos4210-sdhci";
reg = <0x12200000 0x100>;
interrupts = <0 75 0>;
};
sdhci@12210000 {
compatible = "samsung,exynos4210-sdhci";
reg = <0x12210000 0x100>;
interrupts = <0 76 0>;
};
sdhci@12220000 {
compatible = "samsung,exynos4210-sdhci";
reg = <0x12220000 0x100>;
interrupts = <0 77 0>;
};
sdhci@12230000 {
compatible = "samsung,exynos4210-sdhci";
reg = <0x12230000 0x100>;
interrupts = <0 78 0>;
};
serial@12C00000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C00000 0x100>;
interrupts = <0 51 0>;
};
serial@12C10000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C10000 0x100>;
interrupts = <0 52 0>;
};
serial@12C20000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C20000 0x100>;
interrupts = <0 53 0>;
};
serial@12C30000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C30000 0x100>;
interrupts = <0 54 0>;
};
i2c@12C60000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12C60000 0x100>;
interrupts = <0 56 0>;
};
i2c@12C70000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12C70000 0x100>;
interrupts = <0 57 0>;
};
i2c@12C80000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12C80000 0x100>;
interrupts = <0 58 0>;
};
i2c@12C90000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12C90000 0x100>;
interrupts = <0 59 0>;
};
i2c@12CA0000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12CA0000 0x100>;
interrupts = <0 60 0>;
};
i2c@12CB0000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12CB0000 0x100>;
interrupts = <0 61 0>;
};
i2c@12CC0000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12CC0000 0x100>;
interrupts = <0 62 0>;
};
i2c@12CD0000 {
compatible = "samsung,s3c2440-i2c";
reg = <0x12CD0000 0x100>;
interrupts = <0 63 0>;
};
amba {
#address-cells = <1>;
#size-cells = <1>;
compatible = "arm,amba-bus";
interrupt-parent = <&gic>;
ranges;
pdma0: pdma@121A0000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x121A0000 0x1000>;
interrupts = <0 34 0>;
};
pdma1: pdma@121B0000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x121B0000 0x1000>;
interrupts = <0 35 0>;
};
mdma0: pdma@10800000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x10800000 0x1000>;
interrupts = <0 33 0>;
};
mdma1: pdma@11C10000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x11C10000 0x1000>;
interrupts = <0 124 0>;
};
};
gpio-controllers {
#address-cells = <1>;
#size-cells = <1>;
gpio-controller;
ranges;
gpa0: gpio-controller@11400000 {
compatible = "samsung,exynos4-gpio";
reg = <0x11400000 0x20>;
#gpio-cells = <4>;
};
gpa1: gpio-controller@11400020 {
compatible = "samsung,exynos4-gpio";
reg = <0x11400020 0x20>;
#gpio-cells = <4>;
};
gpa2: gpio-controller@11400040 {
compatible = "samsung,exynos4-gpio";
reg = <0x11400040 0x20>;
#gpio-cells = <4>;
};
gpb0: gpio-controller@11400060 {
compatible = "samsung,exynos4-gpio";
reg = <0x11400060 0x20>;
#gpio-cells = <4>;
};
gpb1: gpio-controller@11400080 {
compatible = "samsung,exynos4-gpio";
reg = <0x11400080 0x20>;
#gpio-cells = <4>;
};
gpb2: gpio-controller@114000A0 {
compatible = "samsung,exynos4-gpio";
reg = <0x114000A0 0x20>;
#gpio-cells = <4>;
};
gpb3: gpio-controller@114000C0 {
compatible = "samsung,exynos4-gpio";
reg = <0x114000C0 0x20>;
#gpio-cells = <4>;
};
gpc0: gpio-controller@114000E0 {
compatible = "samsung,exynos4-gpio";
reg = <0x114000E0 0x20>;
#gpio-cells = <4>;
};
gpc1: gpio-controller@11400100 {
compatible = "samsung,exynos4-gpio";
reg = <0x11400100 0x20>;
#gpio-cells = <4>;
};
gpc2: gpio-controller@11400120 {
compatible = "samsung,exynos4-gpio";
reg = <0x11400120 0x20>;
#gpio-cells = <4>;
};
gpc3: gpio-controller@11400140 {
compatible = "samsung,exynos4-gpio";
reg = <0x11400140 0x20>;
#gpio-cells = <4>;
};
gpd0: gpio-controller@11400160 {
compatible = "samsung,exynos4-gpio";
reg = <0x11400160 0x20>;
#gpio-cells = <4>;
};
gpd1: gpio-controller@11400180 {
compatible = "samsung,exynos4-gpio";
reg = <0x11400180 0x20>;
#gpio-cells = <4>;
};
gpy0: gpio-controller@114001A0 {
compatible = "samsung,exynos4-gpio";
reg = <0x114001A0 0x20>;
#gpio-cells = <4>;
};
gpy1: gpio-controller@114001C0 {
compatible = "samsung,exynos4-gpio";
reg = <0x114001C0 0x20>;
#gpio-cells = <4>;
};
gpy2: gpio-controller@114001E0 {
compatible = "samsung,exynos4-gpio";
reg = <0x114001E0 0x20>;
#gpio-cells = <4>;
};
gpy3: gpio-controller@11400200 {
compatible = "samsung,exynos4-gpio";
reg = <0x11400200 0x20>;
#gpio-cells = <4>;
};
gpy4: gpio-controller@11400220 {
compatible = "samsung,exynos4-gpio";
reg = <0x11400220 0x20>;
#gpio-cells = <4>;
};
gpy5: gpio-controller@11400240 {
compatible = "samsung,exynos4-gpio";
reg = <0x11400240 0x20>;
#gpio-cells = <4>;
};
gpy6: gpio-controller@11400260 {
compatible = "samsung,exynos4-gpio";
reg = <0x11400260 0x20>;
#gpio-cells = <4>;
};
gpx0: gpio-controller@11400C00 {
compatible = "samsung,exynos4-gpio";
reg = <0x11400C00 0x20>;
#gpio-cells = <4>;
};
gpx1: gpio-controller@11400C20 {
compatible = "samsung,exynos4-gpio";
reg = <0x11400C20 0x20>;
#gpio-cells = <4>;
};
gpx2: gpio-controller@11400C40 {
compatible = "samsung,exynos4-gpio";
reg = <0x11400C40 0x20>;
#gpio-cells = <4>;
};
gpx3: gpio-controller@11400C60 {
compatible = "samsung,exynos4-gpio";
reg = <0x11400C60 0x20>;
#gpio-cells = <4>;
};
gpe0: gpio-controller@13400000 {
compatible = "samsung,exynos4-gpio";
reg = <0x13400000 0x20>;
#gpio-cells = <4>;
};
gpe1: gpio-controller@13400020 {
compatible = "samsung,exynos4-gpio";
reg = <0x13400020 0x20>;
#gpio-cells = <4>;
};
gpf0: gpio-controller@13400040 {
compatible = "samsung,exynos4-gpio";
reg = <0x13400040 0x20>;
#gpio-cells = <4>;
};
gpf1: gpio-controller@13400060 {
compatible = "samsung,exynos4-gpio";
reg = <0x13400060 0x20>;
#gpio-cells = <4>;
};
gpg0: gpio-controller@13400080 {
compatible = "samsung,exynos4-gpio";
reg = <0x13400080 0x20>;
#gpio-cells = <4>;
};
gpg1: gpio-controller@134000A0 {
compatible = "samsung,exynos4-gpio";
reg = <0x134000A0 0x20>;
#gpio-cells = <4>;
};
gpg2: gpio-controller@134000C0 {
compatible = "samsung,exynos4-gpio";
reg = <0x134000C0 0x20>;
#gpio-cells = <4>;
};
gph0: gpio-controller@134000E0 {
compatible = "samsung,exynos4-gpio";
reg = <0x134000E0 0x20>;
#gpio-cells = <4>;
};
gph1: gpio-controller@13400100 {
compatible = "samsung,exynos4-gpio";
reg = <0x13400100 0x20>;
#gpio-cells = <4>;
};
gpv0: gpio-controller@10D10000 {
compatible = "samsung,exynos4-gpio";
reg = <0x10D10000 0x20>;
#gpio-cells = <4>;
};
gpv1: gpio-controller@10D10020 {
compatible = "samsung,exynos4-gpio";
reg = <0x10D10020 0x20>;
#gpio-cells = <4>;
};
gpv2: gpio-controller@10D10040 {
compatible = "samsung,exynos4-gpio";
reg = <0x10D10040 0x20>;
#gpio-cells = <4>;
};
gpv3: gpio-controller@10D10060 {
compatible = "samsung,exynos4-gpio";
reg = <0x10D10060 0x20>;
#gpio-cells = <4>;
};
gpv4: gpio-controller@10D10080 {
compatible = "samsung,exynos4-gpio";
reg = <0x10D10080 0x20>;
#gpio-cells = <4>;
};
gpz: gpio-controller@03860000 {
compatible = "samsung,exynos4-gpio";
reg = <0x03860000 0x20>;
#gpio-cells = <4>;
};
};
};
...@@ -14,6 +14,22 @@ serial@70006000 { ...@@ -14,6 +14,22 @@ serial@70006000 {
clock-frequency = < 408000000 >; clock-frequency = < 408000000 >;
}; };
serial@70006040 {
status = "disable";
};
serial@70006200 {
status = "disable";
};
serial@70006300 {
status = "disable";
};
serial@70006400 {
status = "disable";
};
i2c@7000c000 { i2c@7000c000 {
clock-frequency = <100000>; clock-frequency = <100000>;
}; };
......
...@@ -11,18 +11,19 @@ if ARCH_EXYNOS ...@@ -11,18 +11,19 @@ if ARCH_EXYNOS
menu "SAMSUNG EXYNOS SoCs Support" menu "SAMSUNG EXYNOS SoCs Support"
choice
prompt "EXYNOS System Type"
default ARCH_EXYNOS4
config ARCH_EXYNOS4 config ARCH_EXYNOS4
bool "SAMSUNG EXYNOS4" bool "SAMSUNG EXYNOS4"
default y
select HAVE_SMP select HAVE_SMP
select MIGHT_HAVE_CACHE_L2X0 select MIGHT_HAVE_CACHE_L2X0
help help
Samsung EXYNOS4 SoCs based systems Samsung EXYNOS4 SoCs based systems
endchoice config ARCH_EXYNOS5
bool "SAMSUNG EXYNOS5"
select HAVE_SMP
help
Samsung EXYNOS5 (Cortex-A15) SoC based systems
comment "EXYNOS SoCs" comment "EXYNOS SoCs"
...@@ -56,6 +57,13 @@ config SOC_EXYNOS4412 ...@@ -56,6 +57,13 @@ config SOC_EXYNOS4412
help help
Enable EXYNOS4412 SoC support Enable EXYNOS4412 SoC support
config SOC_EXYNOS5250
bool "SAMSUNG EXYNOS5250"
default y
depends on ARCH_EXYNOS5
help
Enable EXYNOS5250 SoC support
config EXYNOS4_MCT config EXYNOS4_MCT
bool bool
default y default y
...@@ -356,7 +364,7 @@ config MACH_SMDK4412 ...@@ -356,7 +364,7 @@ config MACH_SMDK4412
Machine support for Samsung SMDK4412 Machine support for Samsung SMDK4412
endif endif
comment "Flattened Device Tree based board for Exynos4 based SoC" comment "Flattened Device Tree based board for EXYNOS SoCs"
config MACH_EXYNOS4_DT config MACH_EXYNOS4_DT
bool "Samsung Exynos4 Machine using device tree" bool "Samsung Exynos4 Machine using device tree"
...@@ -370,6 +378,15 @@ config MACH_EXYNOS4_DT ...@@ -370,6 +378,15 @@ config MACH_EXYNOS4_DT
Note: This is under development and not all peripherals can be supported Note: This is under development and not all peripherals can be supported
with this machine file. with this machine file.
config MACH_EXYNOS5_DT
bool "SAMSUNG EXYNOS5 Machine using device tree"
select SOC_EXYNOS5250
select USE_OF
select ARM_AMBA
help
Machine support for Samsung Exynos4 machine with device tree enabled.
Select this if a fdt blob is available for the EXYNOS4 SoC based board.
if ARCH_EXYNOS4 if ARCH_EXYNOS4
comment "Configuration for HSMMC 8-bit bus width" comment "Configuration for HSMMC 8-bit bus width"
......
...@@ -14,6 +14,7 @@ obj- := ...@@ -14,6 +14,7 @@ obj- :=
obj-$(CONFIG_ARCH_EXYNOS) += common.o obj-$(CONFIG_ARCH_EXYNOS) += common.o
obj-$(CONFIG_ARCH_EXYNOS4) += clock-exynos4.o obj-$(CONFIG_ARCH_EXYNOS4) += clock-exynos4.o
obj-$(CONFIG_ARCH_EXYNOS5) += clock-exynos5.o
obj-$(CONFIG_CPU_EXYNOS4210) += clock-exynos4210.o obj-$(CONFIG_CPU_EXYNOS4210) += clock-exynos4210.o
obj-$(CONFIG_SOC_EXYNOS4212) += clock-exynos4212.o obj-$(CONFIG_SOC_EXYNOS4212) += clock-exynos4212.o
...@@ -42,9 +43,11 @@ obj-$(CONFIG_MACH_SMDK4212) += mach-smdk4x12.o ...@@ -42,9 +43,11 @@ obj-$(CONFIG_MACH_SMDK4212) += mach-smdk4x12.o
obj-$(CONFIG_MACH_SMDK4412) += mach-smdk4x12.o obj-$(CONFIG_MACH_SMDK4412) += mach-smdk4x12.o
obj-$(CONFIG_MACH_EXYNOS4_DT) += mach-exynos4-dt.o obj-$(CONFIG_MACH_EXYNOS4_DT) += mach-exynos4-dt.o
obj-$(CONFIG_MACH_EXYNOS5_DT) += mach-exynos5-dt.o
# device support # device support
obj-y += dev-uart.o
obj-$(CONFIG_ARCH_EXYNOS4) += dev-audio.o obj-$(CONFIG_ARCH_EXYNOS4) += dev-audio.o
obj-$(CONFIG_EXYNOS4_DEV_AHCI) += dev-ahci.o obj-$(CONFIG_EXYNOS4_DEV_AHCI) += dev-ahci.o
obj-$(CONFIG_EXYNOS4_DEV_SYSMMU) += dev-sysmmu.o obj-$(CONFIG_EXYNOS4_DEV_SYSMMU) += dev-sysmmu.o
...@@ -52,7 +55,7 @@ obj-$(CONFIG_EXYNOS4_DEV_DWMCI) += dev-dwmci.o ...@@ -52,7 +55,7 @@ obj-$(CONFIG_EXYNOS4_DEV_DWMCI) += dev-dwmci.o
obj-$(CONFIG_EXYNOS4_DEV_DMA) += dma.o obj-$(CONFIG_EXYNOS4_DEV_DMA) += dma.o
obj-$(CONFIG_EXYNOS4_DEV_USB_OHCI) += dev-ohci.o obj-$(CONFIG_EXYNOS4_DEV_USB_OHCI) += dev-ohci.o
obj-$(CONFIG_ARCH_EXYNOS4) += setup-i2c0.o obj-$(CONFIG_ARCH_EXYNOS) += setup-i2c0.o
obj-$(CONFIG_EXYNOS4_SETUP_FIMC) += setup-fimc.o obj-$(CONFIG_EXYNOS4_SETUP_FIMC) += setup-fimc.o
obj-$(CONFIG_EXYNOS4_SETUP_FIMD0) += setup-fimd0.o obj-$(CONFIG_EXYNOS4_SETUP_FIMD0) += setup-fimd0.o
obj-$(CONFIG_EXYNOS4_SETUP_I2C1) += setup-i2c1.o obj-$(CONFIG_EXYNOS4_SETUP_I2C1) += setup-i2c1.o
......
...@@ -495,11 +495,6 @@ static struct clk exynos4_init_clocks_off[] = { ...@@ -495,11 +495,6 @@ static struct clk exynos4_init_clocks_off[] = {
.devname = "exynos4-fimc.3", .devname = "exynos4-fimc.3",
.enable = exynos4_clk_ip_cam_ctrl, .enable = exynos4_clk_ip_cam_ctrl,
.ctrlbit = (1 << 3), .ctrlbit = (1 << 3),
}, {
.name = "fimd",
.devname = "exynos4-fb.0",
.enable = exynos4_clk_ip_lcd0_ctrl,
.ctrlbit = (1 << 0),
}, { }, {
.name = "hsmmc", .name = "hsmmc",
.devname = "s3c-sdhci.0", .devname = "s3c-sdhci.0",
...@@ -796,6 +791,13 @@ static struct clk exynos4_clk_mdma1 = { ...@@ -796,6 +791,13 @@ static struct clk exynos4_clk_mdma1 = {
.ctrlbit = ((1 << 8) | (1 << 5) | (1 << 2)), .ctrlbit = ((1 << 8) | (1 << 5) | (1 << 2)),
}; };
static struct clk exynos4_clk_fimd0 = {
.name = "fimd",
.devname = "exynos4-fb.0",
.enable = exynos4_clk_ip_lcd0_ctrl,
.ctrlbit = (1 << 0),
};
struct clk *exynos4_clkset_group_list[] = { struct clk *exynos4_clkset_group_list[] = {
[0] = &clk_ext_xtal_mux, [0] = &clk_ext_xtal_mux,
[1] = &clk_xusbxti, [1] = &clk_xusbxti,
...@@ -1315,6 +1317,7 @@ static struct clk *exynos4_clk_cdev[] = { ...@@ -1315,6 +1317,7 @@ static struct clk *exynos4_clk_cdev[] = {
&exynos4_clk_pdma0, &exynos4_clk_pdma0,
&exynos4_clk_pdma1, &exynos4_clk_pdma1,
&exynos4_clk_mdma1, &exynos4_clk_mdma1,
&exynos4_clk_fimd0,
}; };
static struct clksrc_clk *exynos4_clksrc_cdev[] = { static struct clksrc_clk *exynos4_clksrc_cdev[] = {
...@@ -1341,6 +1344,7 @@ static struct clk_lookup exynos4_clk_lookup[] = { ...@@ -1341,6 +1344,7 @@ static struct clk_lookup exynos4_clk_lookup[] = {
CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk), CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk),
CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk), CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk),
CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk), CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk),
CLKDEV_INIT("exynos4-fb.0", "lcd", &exynos4_clk_fimd0),
CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0), CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0),
CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1), CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1),
CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos4_clk_mdma1), CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos4_clk_mdma1),
......
This diff is collapsed.
This diff is collapsed.
...@@ -12,39 +12,44 @@ ...@@ -12,39 +12,44 @@
#ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H #ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H
#define __ARCH_ARM_MACH_EXYNOS_COMMON_H #define __ARCH_ARM_MACH_EXYNOS_COMMON_H
extern struct sys_timer exynos4_timer;
void exynos_init_io(struct map_desc *mach_desc, int size); void exynos_init_io(struct map_desc *mach_desc, int size);
void exynos4_init_irq(void); void exynos4_init_irq(void);
void exynos5_init_irq(void);
void exynos4_restart(char mode, const char *cmd);
void exynos5_restart(char mode, const char *cmd);
#ifdef CONFIG_ARCH_EXYNOS4 #ifdef CONFIG_ARCH_EXYNOS4
void exynos4_register_clocks(void); void exynos4_register_clocks(void);
void exynos4_setup_clocks(void); void exynos4_setup_clocks(void);
void exynos4210_register_clocks(void);
void exynos4212_register_clocks(void);
#else #else
#define exynos4_register_clocks() #define exynos4_register_clocks()
#define exynos4_setup_clocks() #define exynos4_setup_clocks()
#endif
#define exynos4210_register_clocks() #ifdef CONFIG_ARCH_EXYNOS5
#define exynos4212_register_clocks() void exynos5_register_clocks(void);
void exynos5_setup_clocks(void);
#else
#define exynos5_register_clocks()
#define exynos5_setup_clocks()
#endif #endif
void exynos4_restart(char mode, const char *cmd); #ifdef CONFIG_CPU_EXYNOS4210
void exynos4210_register_clocks(void);
extern struct sys_timer exynos4_timer; #else
#define exynos4210_register_clocks()
#endif
#ifdef CONFIG_ARCH_EXYNOS #ifdef CONFIG_SOC_EXYNOS4212
extern int exynos_init(void); void exynos4212_register_clocks(void);
extern void exynos4_map_io(void);
extern void exynos4_init_clocks(int xtal);
extern void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no);
#else #else
#define exynos4_init_clocks NULL #define exynos4212_register_clocks()
#define exynos4_init_uarts NULL
#define exynos4_map_io NULL
#define exynos_init NULL
#endif #endif
#endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */ #endif /* __ARCH_ARM_MACH_EXYNOS_COMMON_H */
...@@ -242,8 +242,8 @@ static struct resource exynos4_ahci_resource[] = { ...@@ -242,8 +242,8 @@ static struct resource exynos4_ahci_resource[] = {
.flags = IORESOURCE_MEM, .flags = IORESOURCE_MEM,
}, },
[1] = { [1] = {
.start = IRQ_SATA, .start = EXYNOS4_IRQ_SATA,
.end = IRQ_SATA, .end = EXYNOS4_IRQ_SATA,
.flags = IORESOURCE_IRQ, .flags = IORESOURCE_IRQ,
}, },
}; };
......
...@@ -304,8 +304,8 @@ static struct resource exynos4_ac97_resource[] = { ...@@ -304,8 +304,8 @@ static struct resource exynos4_ac97_resource[] = {
.flags = IORESOURCE_DMA, .flags = IORESOURCE_DMA,
}, },
[4] = { [4] = {
.start = IRQ_AC97, .start = EXYNOS4_IRQ_AC97,
.end = IRQ_AC97, .end = EXYNOS4_IRQ_AC97,
.flags = IORESOURCE_IRQ, .flags = IORESOURCE_IRQ,
}, },
}; };
......
/*
* Copyright (c) 2012 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Base EXYNOS UART resource and device definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/interrupt.h>
#include <linux/list.h>
#include <linux/ioport.h>
#include <linux/platform_device.h>
#include <asm/mach/arch.h>
#include <asm/mach/irq.h>
#include <mach/hardware.h>
#include <mach/map.h>
#include <plat/devs.h>
#define EXYNOS_UART_RESOURCE(_series, _nr) \
static struct resource exynos##_series##_uart##_nr##_resource[] = { \
[0] = DEFINE_RES_MEM(EXYNOS##_series##_PA_UART##_nr, EXYNOS##_series##_SZ_UART), \
[1] = DEFINE_RES_IRQ(EXYNOS##_series##_IRQ_UART##_nr), \
};
EXYNOS_UART_RESOURCE(4, 0)
EXYNOS_UART_RESOURCE(4, 1)
EXYNOS_UART_RESOURCE(4, 2)
EXYNOS_UART_RESOURCE(4, 3)
struct s3c24xx_uart_resources exynos4_uart_resources[] __initdata = {
[0] = {
.resources = exynos4_uart0_resource,
.nr_resources = ARRAY_SIZE(exynos4_uart0_resource),
},
[1] = {
.resources = exynos4_uart1_resource,
.nr_resources = ARRAY_SIZE(exynos4_uart1_resource),
},
[2] = {
.resources = exynos4_uart2_resource,
.nr_resources = ARRAY_SIZE(exynos4_uart2_resource),
},
[3] = {
.resources = exynos4_uart3_resource,
.nr_resources = ARRAY_SIZE(exynos4_uart3_resource),
},
};
EXYNOS_UART_RESOURCE(5, 0)
EXYNOS_UART_RESOURCE(5, 1)
EXYNOS_UART_RESOURCE(5, 2)
EXYNOS_UART_RESOURCE(5, 3)
struct s3c24xx_uart_resources exynos5_uart_resources[] __initdata = {
[0] = {
.resources = exynos5_uart0_resource,
.nr_resources = ARRAY_SIZE(exynos5_uart0_resource),
},
[1] = {
.resources = exynos5_uart1_resource,
.nr_resources = ARRAY_SIZE(exynos5_uart0_resource),
},
[2] = {
.resources = exynos5_uart2_resource,
.nr_resources = ARRAY_SIZE(exynos5_uart2_resource),
},
[3] = {
.resources = exynos5_uart3_resource,
.nr_resources = ARRAY_SIZE(exynos5_uart3_resource),
},
};
...@@ -108,7 +108,7 @@ static u8 exynos4212_pdma0_peri[] = { ...@@ -108,7 +108,7 @@ static u8 exynos4212_pdma0_peri[] = {
struct dma_pl330_platdata exynos4_pdma0_pdata; struct dma_pl330_platdata exynos4_pdma0_pdata;
static AMBA_AHB_DEVICE(exynos4_pdma0, "dma-pl330.0", 0x00041330, static AMBA_AHB_DEVICE(exynos4_pdma0, "dma-pl330.0", 0x00041330,
EXYNOS4_PA_PDMA0, {IRQ_PDMA0}, &exynos4_pdma0_pdata); EXYNOS4_PA_PDMA0, {EXYNOS4_IRQ_PDMA0}, &exynos4_pdma0_pdata);
static u8 exynos4210_pdma1_peri[] = { static u8 exynos4210_pdma1_peri[] = {
DMACH_PCM0_RX, DMACH_PCM0_RX,
...@@ -174,7 +174,7 @@ static u8 exynos4212_pdma1_peri[] = { ...@@ -174,7 +174,7 @@ static u8 exynos4212_pdma1_peri[] = {
static struct dma_pl330_platdata exynos4_pdma1_pdata; static struct dma_pl330_platdata exynos4_pdma1_pdata;
static AMBA_AHB_DEVICE(exynos4_pdma1, "dma-pl330.1", 0x00041330, static AMBA_AHB_DEVICE(exynos4_pdma1, "dma-pl330.1", 0x00041330,
EXYNOS4_PA_PDMA1, {IRQ_PDMA1}, &exynos4_pdma1_pdata); EXYNOS4_PA_PDMA1, {EXYNOS4_IRQ_PDMA1}, &exynos4_pdma1_pdata);
static u8 mdma_peri[] = { static u8 mdma_peri[] = {
DMACH_MTOM_0, DMACH_MTOM_0,
...@@ -193,7 +193,7 @@ static struct dma_pl330_platdata exynos4_mdma1_pdata = { ...@@ -193,7 +193,7 @@ static struct dma_pl330_platdata exynos4_mdma1_pdata = {
}; };
static AMBA_AHB_DEVICE(exynos4_mdma1, "dma-pl330.2", 0x00041330, static AMBA_AHB_DEVICE(exynos4_mdma1, "dma-pl330.2", 0x00041330,
EXYNOS4_PA_MDMA1, {IRQ_MDMA1}, &exynos4_mdma1_pdata); EXYNOS4_PA_MDMA1, {EXYNOS4_IRQ_MDMA1}, &exynos4_mdma1_pdata);
static int __init exynos4_dma_init(void) static int __init exynos4_dma_init(void)
{ {
......
...@@ -21,8 +21,13 @@ ...@@ -21,8 +21,13 @@
*/ */
.macro addruart, rp, rv, tmp .macro addruart, rp, rv, tmp
ldr \rp, = S3C_PA_UART mov \rp, #0x10000000
ldr \rv, = S3C_VA_UART ldr \rp, [\rp, #0x0]
and \rp, \rp, #0xf00000
teq \rp, #0x500000 @@ EXYNOS5
ldreq \rp, =EXYNOS5_PA_UART
movne \rp, #EXYNOS4_PA_UART @@ EXYNOS4
ldr \rv, =S3C_VA_UART
#if CONFIG_DEBUG_S3C_UART != 0 #if CONFIG_DEBUG_S3C_UART != 0
add \rp, \rp, #(0x10000 * CONFIG_DEBUG_S3C_UART) add \rp, \rp, #(0x10000 * CONFIG_DEBUG_S3C_UART)
add \rv, \rv, #(0x10000 * CONFIG_DEBUG_S3C_UART) add \rv, \rv, #(0x10000 * CONFIG_DEBUG_S3C_UART)
......
This diff is collapsed.
...@@ -25,6 +25,7 @@ ...@@ -25,6 +25,7 @@
#define EXYNOS4_PA_SYSRAM0 0x02025000 #define EXYNOS4_PA_SYSRAM0 0x02025000
#define EXYNOS4_PA_SYSRAM1 0x02020000 #define EXYNOS4_PA_SYSRAM1 0x02020000
#define EXYNOS5_PA_SYSRAM 0x02020000
#define EXYNOS4_PA_FIMC0 0x11800000 #define EXYNOS4_PA_FIMC0 0x11800000
#define EXYNOS4_PA_FIMC1 0x11810000 #define EXYNOS4_PA_FIMC1 0x11810000
...@@ -48,14 +49,23 @@ ...@@ -48,14 +49,23 @@
#define EXYNOS4_PA_ONENAND 0x0C000000 #define EXYNOS4_PA_ONENAND 0x0C000000
#define EXYNOS4_PA_ONENAND_DMA 0x0C600000 #define EXYNOS4_PA_ONENAND_DMA 0x0C600000
#define EXYNOS4_PA_CHIPID 0x10000000 #define EXYNOS_PA_CHIPID 0x10000000
#define EXYNOS4_PA_SYSCON 0x10010000 #define EXYNOS4_PA_SYSCON 0x10010000
#define EXYNOS5_PA_SYSCON 0x10050100
#define EXYNOS4_PA_PMU 0x10020000 #define EXYNOS4_PA_PMU 0x10020000
#define EXYNOS5_PA_PMU 0x10040000
#define EXYNOS4_PA_CMU 0x10030000 #define EXYNOS4_PA_CMU 0x10030000
#define EXYNOS5_PA_CMU 0x10010000
#define EXYNOS4_PA_SYSTIMER 0x10050000 #define EXYNOS4_PA_SYSTIMER 0x10050000
#define EXYNOS5_PA_SYSTIMER 0x101C0000
#define EXYNOS4_PA_WATCHDOG 0x10060000 #define EXYNOS4_PA_WATCHDOG 0x10060000
#define EXYNOS5_PA_WATCHDOG 0x101D0000
#define EXYNOS4_PA_RTC 0x10070000 #define EXYNOS4_PA_RTC 0x10070000
#define EXYNOS4_PA_KEYPAD 0x100A0000 #define EXYNOS4_PA_KEYPAD 0x100A0000
...@@ -64,9 +74,12 @@ ...@@ -64,9 +74,12 @@
#define EXYNOS4_PA_DMC1 0x10410000 #define EXYNOS4_PA_DMC1 0x10410000
#define EXYNOS4_PA_COMBINER 0x10440000 #define EXYNOS4_PA_COMBINER 0x10440000
#define EXYNOS5_PA_COMBINER 0x10440000
#define EXYNOS4_PA_GIC_CPU 0x10480000 #define EXYNOS4_PA_GIC_CPU 0x10480000
#define EXYNOS4_PA_GIC_DIST 0x10490000 #define EXYNOS4_PA_GIC_DIST 0x10490000
#define EXYNOS5_PA_GIC_CPU 0x10480000
#define EXYNOS5_PA_GIC_DIST 0x10490000
#define EXYNOS4_PA_COREPERI 0x10500000 #define EXYNOS4_PA_COREPERI 0x10500000
#define EXYNOS4_PA_TWD 0x10500600 #define EXYNOS4_PA_TWD 0x10500600
...@@ -97,7 +110,6 @@ ...@@ -97,7 +110,6 @@
#define EXYNOS4_PA_SPI1 0x13930000 #define EXYNOS4_PA_SPI1 0x13930000
#define EXYNOS4_PA_SPI2 0x13940000 #define EXYNOS4_PA_SPI2 0x13940000
#define EXYNOS4_PA_GPIO1 0x11400000 #define EXYNOS4_PA_GPIO1 0x11400000
#define EXYNOS4_PA_GPIO2 0x11000000 #define EXYNOS4_PA_GPIO2 0x11000000
#define EXYNOS4_PA_GPIO3 0x03860000 #define EXYNOS4_PA_GPIO3 0x03860000
...@@ -119,6 +131,7 @@ ...@@ -119,6 +131,7 @@
#define EXYNOS4_PA_SATAPHY_CTRL 0x126B0000 #define EXYNOS4_PA_SATAPHY_CTRL 0x126B0000
#define EXYNOS4_PA_SROMC 0x12570000 #define EXYNOS4_PA_SROMC 0x12570000
#define EXYNOS5_PA_SROMC 0x12250000
#define EXYNOS4_PA_EHCI 0x12580000 #define EXYNOS4_PA_EHCI 0x12580000
#define EXYNOS4_PA_OHCI 0x12590000 #define EXYNOS4_PA_OHCI 0x12590000
...@@ -126,6 +139,7 @@ ...@@ -126,6 +139,7 @@
#define EXYNOS4_PA_MFC 0x13400000 #define EXYNOS4_PA_MFC 0x13400000
#define EXYNOS4_PA_UART 0x13800000 #define EXYNOS4_PA_UART 0x13800000
#define EXYNOS5_PA_UART 0x12C00000
#define EXYNOS4_PA_VP 0x12C00000 #define EXYNOS4_PA_VP 0x12C00000
#define EXYNOS4_PA_MIXER 0x12C10000 #define EXYNOS4_PA_MIXER 0x12C10000
...@@ -134,6 +148,7 @@ ...@@ -134,6 +148,7 @@
#define EXYNOS4_PA_IIC_HDMIPHY 0x138E0000 #define EXYNOS4_PA_IIC_HDMIPHY 0x138E0000
#define EXYNOS4_PA_IIC(x) (0x13860000 + ((x) * 0x10000)) #define EXYNOS4_PA_IIC(x) (0x13860000 + ((x) * 0x10000))
#define EXYNOS5_PA_IIC(x) (0x12C60000 + ((x) * 0x10000))
#define EXYNOS4_PA_ADC 0x13910000 #define EXYNOS4_PA_ADC 0x13910000
#define EXYNOS4_PA_ADC1 0x13911000 #define EXYNOS4_PA_ADC1 0x13911000
...@@ -143,8 +158,10 @@ ...@@ -143,8 +158,10 @@
#define EXYNOS4_PA_SPDIF 0x139B0000 #define EXYNOS4_PA_SPDIF 0x139B0000
#define EXYNOS4_PA_TIMER 0x139D0000 #define EXYNOS4_PA_TIMER 0x139D0000
#define EXYNOS5_PA_TIMER 0x12DD0000
#define EXYNOS4_PA_SDRAM 0x40000000 #define EXYNOS4_PA_SDRAM 0x40000000
#define EXYNOS5_PA_SDRAM 0x40000000
/* Compatibiltiy Defines */ /* Compatibiltiy Defines */
...@@ -162,7 +179,6 @@ ...@@ -162,7 +179,6 @@
#define S3C_PA_IIC7 EXYNOS4_PA_IIC(7) #define S3C_PA_IIC7 EXYNOS4_PA_IIC(7)
#define S3C_PA_RTC EXYNOS4_PA_RTC #define S3C_PA_RTC EXYNOS4_PA_RTC
#define S3C_PA_WDT EXYNOS4_PA_WATCHDOG #define S3C_PA_WDT EXYNOS4_PA_WATCHDOG
#define S3C_PA_UART EXYNOS4_PA_UART
#define S3C_PA_SPI0 EXYNOS4_PA_SPI0 #define S3C_PA_SPI0 EXYNOS4_PA_SPI0
#define S3C_PA_SPI1 EXYNOS4_PA_SPI1 #define S3C_PA_SPI1 EXYNOS4_PA_SPI1
#define S3C_PA_SPI2 EXYNOS4_PA_SPI2 #define S3C_PA_SPI2 EXYNOS4_PA_SPI2
...@@ -193,15 +209,18 @@ ...@@ -193,15 +209,18 @@
/* Compatibility UART */ /* Compatibility UART */
#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET)) #define EXYNOS4_PA_UART0 0x13800000
#define EXYNOS4_PA_UART1 0x13810000
#define EXYNOS4_PA_UART2 0x13820000
#define EXYNOS4_PA_UART3 0x13830000
#define EXYNOS4_SZ_UART SZ_256
#define S5P_PA_UART(x) (EXYNOS4_PA_UART + ((x) * S3C_UART_OFFSET)) #define EXYNOS5_PA_UART0 0x12C00000
#define S5P_PA_UART0 S5P_PA_UART(0) #define EXYNOS5_PA_UART1 0x12C10000
#define S5P_PA_UART1 S5P_PA_UART(1) #define EXYNOS5_PA_UART2 0x12C20000
#define S5P_PA_UART2 S5P_PA_UART(2) #define EXYNOS5_PA_UART3 0x12C30000
#define S5P_PA_UART3 S5P_PA_UART(3) #define EXYNOS5_SZ_UART SZ_256
#define S5P_PA_UART4 S5P_PA_UART(4)
#define S5P_SZ_UART SZ_256 #define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
#endif /* __ASM_ARCH_MAP_H */ #endif /* __ASM_ARCH_MAP_H */
...@@ -253,6 +253,68 @@ ...@@ -253,6 +253,68 @@
#define EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT (0) #define EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT (0)
#define EXYNOS4_CLKDIV_CAM1_JPEG_MASK (0xf << EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT) #define EXYNOS4_CLKDIV_CAM1_JPEG_MASK (0xf << EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT)
/* For EXYNOS5250 */
#define EXYNOS5_APLL_CON0 EXYNOS_CLKREG(0x00100)
#define EXYNOS5_CLKSRC_CPU EXYNOS_CLKREG(0x00200)
#define EXYNOS5_CLKDIV_CPU0 EXYNOS_CLKREG(0x00500)
#define EXYNOS5_MPLL_CON0 EXYNOS_CLKREG(0x04100)
#define EXYNOS5_CLKSRC_CORE1 EXYNOS_CLKREG(0x04204)
#define EXYNOS5_CLKGATE_IP_CORE EXYNOS_CLKREG(0x04900)
#define EXYNOS5_CLKDIV_ACP EXYNOS_CLKREG(0x08500)
#define EXYNOS5_CLKSRC_TOP2 EXYNOS_CLKREG(0x10218)
#define EXYNOS5_EPLL_CON0 EXYNOS_CLKREG(0x10130)
#define EXYNOS5_EPLL_CON1 EXYNOS_CLKREG(0x10134)
#define EXYNOS5_VPLL_CON0 EXYNOS_CLKREG(0x10140)
#define EXYNOS5_VPLL_CON1 EXYNOS_CLKREG(0x10144)
#define EXYNOS5_CPLL_CON0 EXYNOS_CLKREG(0x10120)
#define EXYNOS5_CLKSRC_TOP0 EXYNOS_CLKREG(0x10210)
#define EXYNOS5_CLKSRC_TOP3 EXYNOS_CLKREG(0x1021C)
#define EXYNOS5_CLKSRC_GSCL EXYNOS_CLKREG(0x10220)
#define EXYNOS5_CLKSRC_DISP1_0 EXYNOS_CLKREG(0x1022C)
#define EXYNOS5_CLKSRC_FSYS EXYNOS_CLKREG(0x10244)
#define EXYNOS5_CLKSRC_PERIC0 EXYNOS_CLKREG(0x10250)
#define EXYNOS5_CLKSRC_MASK_TOP EXYNOS_CLKREG(0x10310)
#define EXYNOS5_CLKSRC_MASK_GSCL EXYNOS_CLKREG(0x10320)
#define EXYNOS5_CLKSRC_MASK_DISP1_0 EXYNOS_CLKREG(0x1032C)
#define EXYNOS5_CLKSRC_MASK_FSYS EXYNOS_CLKREG(0x10340)
#define EXYNOS5_CLKSRC_MASK_PERIC0 EXYNOS_CLKREG(0x10350)
#define EXYNOS5_CLKDIV_TOP0 EXYNOS_CLKREG(0x10510)
#define EXYNOS5_CLKDIV_TOP1 EXYNOS_CLKREG(0x10514)
#define EXYNOS5_CLKDIV_GSCL EXYNOS_CLKREG(0x10520)
#define EXYNOS5_CLKDIV_DISP1_0 EXYNOS_CLKREG(0x1052C)
#define EXYNOS5_CLKDIV_GEN EXYNOS_CLKREG(0x1053C)
#define EXYNOS5_CLKDIV_FSYS0 EXYNOS_CLKREG(0x10548)
#define EXYNOS5_CLKDIV_FSYS1 EXYNOS_CLKREG(0x1054C)
#define EXYNOS5_CLKDIV_FSYS2 EXYNOS_CLKREG(0x10550)
#define EXYNOS5_CLKDIV_FSYS3 EXYNOS_CLKREG(0x10554)
#define EXYNOS5_CLKDIV_PERIC0 EXYNOS_CLKREG(0x10558)
#define EXYNOS5_CLKGATE_IP_ACP EXYNOS_CLKREG(0x08800)
#define EXYNOS5_CLKGATE_IP_GSCL EXYNOS_CLKREG(0x10920)
#define EXYNOS5_CLKGATE_IP_DISP1 EXYNOS_CLKREG(0x10928)
#define EXYNOS5_CLKGATE_IP_MFC EXYNOS_CLKREG(0x1092C)
#define EXYNOS5_CLKGATE_IP_GEN EXYNOS_CLKREG(0x10934)
#define EXYNOS5_CLKGATE_IP_FSYS EXYNOS_CLKREG(0x10944)
#define EXYNOS5_CLKGATE_IP_GPS EXYNOS_CLKREG(0x1094C)
#define EXYNOS5_CLKGATE_IP_PERIC EXYNOS_CLKREG(0x10950)
#define EXYNOS5_CLKGATE_IP_PERIS EXYNOS_CLKREG(0x10960)
#define EXYNOS5_CLKGATE_BLOCK EXYNOS_CLKREG(0x10980)
#define EXYNOS5_BPLL_CON0 EXYNOS_CLKREG(0x20110)
#define EXYNOS5_CLKSRC_CDREX EXYNOS_CLKREG(0x20200)
#define EXYNOS5_CLKDIV_CDREX EXYNOS_CLKREG(0x20500)
#define EXYNOS5_EPLL_LOCK EXYNOS_CLKREG(0x10030)
#define EXYNOS5_EPLLCON0_LOCKED_SHIFT (29)
/* Compatibility defines and inclusion */ /* Compatibility defines and inclusion */
#include <mach/regs-pmu.h> #include <mach/regs-pmu.h>
......
...@@ -16,6 +16,15 @@ ...@@ -16,6 +16,15 @@
#include <mach/map.h> #include <mach/map.h>
#include <mach/irqs.h> #include <mach/irqs.h>
#define EINT_REG_NR(x) (EINT_OFFSET(x) >> 3)
#define EINT_CON(b, x) (b + 0xE00 + (EINT_REG_NR(x) * 4))
#define EINT_FLTCON(b, x) (b + 0xE80 + (EINT_REG_NR(x) * 4))
#define EINT_MASK(b, x) (b + 0xF00 + (EINT_REG_NR(x) * 4))
#define EINT_PEND(b, x) (b + 0xF40 + (EINT_REG_NR(x) * 4))
#define EINT_OFFSET_BIT(x) (1 << (EINT_OFFSET(x) & 0x7))
/* compatibility for plat-s5p/irq-pm.c */
#define EXYNOS4_EINT40CON (S5P_VA_GPIO2 + 0xE00) #define EXYNOS4_EINT40CON (S5P_VA_GPIO2 + 0xE00)
#define S5P_EINT_CON(x) (EXYNOS4_EINT40CON + ((x) * 0x4)) #define S5P_EINT_CON(x) (EXYNOS4_EINT40CON + ((x) * 0x4))
...@@ -28,15 +37,4 @@ ...@@ -28,15 +37,4 @@
#define EXYNOS4_EINT40PEND (S5P_VA_GPIO2 + 0xF40) #define EXYNOS4_EINT40PEND (S5P_VA_GPIO2 + 0xF40)
#define S5P_EINT_PEND(x) (EXYNOS4_EINT40PEND + ((x) * 0x4)) #define S5P_EINT_PEND(x) (EXYNOS4_EINT40PEND + ((x) * 0x4))
#define EINT_REG_NR(x) (EINT_OFFSET(x) >> 3)
#define eint_irq_to_bit(irq) (1 << (EINT_OFFSET(irq) & 0x7))
#define EINT_MODE S3C_GPIO_SFN(0xf)
#define EINT_GPIO_0(x) EXYNOS4_GPX0(x)
#define EINT_GPIO_1(x) EXYNOS4_GPX1(x)
#define EINT_GPIO_2(x) EXYNOS4_GPX2(x)
#define EINT_GPIO_3(x) EXYNOS4_GPX3(x)
#endif /* __ASM_ARCH_REGS_GPIO_H */ #endif /* __ASM_ARCH_REGS_GPIO_H */
...@@ -31,6 +31,7 @@ ...@@ -31,6 +31,7 @@
#define S5P_USE_STANDBYWFE_ISP_ARM (1 << 26) #define S5P_USE_STANDBYWFE_ISP_ARM (1 << 26)
#define S5P_SWRESET S5P_PMUREG(0x0400) #define S5P_SWRESET S5P_PMUREG(0x0400)
#define EXYNOS_SWRESET S5P_PMUREG(0x0400)
#define S5P_WAKEUP_STAT S5P_PMUREG(0x0600) #define S5P_WAKEUP_STAT S5P_PMUREG(0x0600)
#define S5P_EINT_WAKEUP_MASK S5P_PMUREG(0x0604) #define S5P_EINT_WAKEUP_MASK S5P_PMUREG(0x0604)
......
/* linux/arch/arm/mach-exynos4/include/mach/uncompress.h /*
* * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com * http://www.samsung.com
* *
* EXYNOS4 - uncompress code * EXYNOS - uncompress code
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as * it under the terms of the GNU General Public License version 2 as
...@@ -13,12 +12,20 @@ ...@@ -13,12 +12,20 @@
#ifndef __ASM_ARCH_UNCOMPRESS_H #ifndef __ASM_ARCH_UNCOMPRESS_H
#define __ASM_ARCH_UNCOMPRESS_H __FILE__ #define __ASM_ARCH_UNCOMPRESS_H __FILE__
#include <asm/mach-types.h>
#include <mach/map.h> #include <mach/map.h>
volatile u8 *uart_base;
#include <plat/uncompress.h> #include <plat/uncompress.h>
static void arch_detect_cpu(void) static void arch_detect_cpu(void)
{ {
/* we do not need to do any cpu detection here at the moment. */ if (machine_is_smdk5250())
uart_base = (volatile u8 *)EXYNOS5_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT);
else
uart_base = (volatile u8 *)EXYNOS4_PA_UART + (S3C_UART_OFFSET * CONFIG_S3C_LOWLEVEL_UART_PORT);
/* /*
* For preventing FIFO overrun or infinite loop of UART console, * For preventing FIFO overrun or infinite loop of UART console,
......
...@@ -37,13 +37,13 @@ ...@@ -37,13 +37,13 @@
* data from the device tree. * data from the device tree.
*/ */
static const struct of_dev_auxdata exynos4210_auxdata_lookup[] __initconst = { static const struct of_dev_auxdata exynos4210_auxdata_lookup[] __initconst = {
OF_DEV_AUXDATA("samsung,exynos4210-uart", S5P_PA_UART0, OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART0,
"exynos4210-uart.0", NULL), "exynos4210-uart.0", NULL),
OF_DEV_AUXDATA("samsung,exynos4210-uart", S5P_PA_UART1, OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART1,
"exynos4210-uart.1", NULL), "exynos4210-uart.1", NULL),
OF_DEV_AUXDATA("samsung,exynos4210-uart", S5P_PA_UART2, OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART2,
"exynos4210-uart.2", NULL), "exynos4210-uart.2", NULL),
OF_DEV_AUXDATA("samsung,exynos4210-uart", S5P_PA_UART3, OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART3,
"exynos4210-uart.3", NULL), "exynos4210-uart.3", NULL),
OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(0), OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(0),
"exynos4-sdhci.0", NULL), "exynos4-sdhci.0", NULL),
......
/*
* SAMSUNG EXYNOS5250 Flattened Device Tree enabled machine
*
* Copyright (c) 2012 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/of_platform.h>
#include <linux/serial_core.h>
#include <asm/mach/arch.h>
#include <asm/hardware/gic.h>
#include <mach/map.h>
#include <plat/cpu.h>
#include <plat/regs-serial.h>
#include "common.h"
/*
* The following lookup table is used to override device names when devices
* are registered from device tree. This is temporarily added to enable
* device tree support addition for the EXYNOS5 architecture.
*
* For drivers that require platform data to be provided from the machine
* file, a platform data pointer can also be supplied along with the
* devices names. Usually, the platform data elements that cannot be parsed
* from the device tree by the drivers (example: function pointers) are
* supplied. But it should be noted that this is a temporary mechanism and
* at some point, the drivers should be capable of parsing all the platform
* data from the device tree.
*/
static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART0,
"exynos4210-uart.0", NULL),
OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART1,
"exynos4210-uart.1", NULL),
OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART2,
"exynos4210-uart.2", NULL),
OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART3,
"exynos4210-uart.3", NULL),
OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.2", NULL),
{},
};
static void __init exynos5250_dt_map_io(void)
{
exynos_init_io(NULL, 0);
s3c24xx_init_clocks(24000000);
}
static void __init exynos5250_dt_machine_init(void)
{
of_platform_populate(NULL, of_default_bus_match_table,
exynos5250_auxdata_lookup, NULL);
}
static char const *exynos5250_dt_compat[] __initdata = {
"samsung,exynos5250",
NULL
};
DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)")
/* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
.init_irq = exynos5_init_irq,
.map_io = exynos5250_dt_map_io,
.handle_irq = gic_handle_irq,
.init_machine = exynos5250_dt_machine_init,
.timer = &exynos4_timer,
.dt_compat = exynos5250_dt_compat,
.restart = exynos5_restart,
MACHINE_END
...@@ -261,7 +261,10 @@ static void exynos4_clockevent_init(void) ...@@ -261,7 +261,10 @@ static void exynos4_clockevent_init(void)
mct_comp_device.cpumask = cpumask_of(0); mct_comp_device.cpumask = cpumask_of(0);
clockevents_register_device(&mct_comp_device); clockevents_register_device(&mct_comp_device);
setup_irq(IRQ_MCT_G0, &mct_comp_event_irq); if (soc_is_exynos5250())
setup_irq(EXYNOS5_IRQ_MCT_G0, &mct_comp_event_irq);
else
setup_irq(EXYNOS4_IRQ_MCT_G0, &mct_comp_event_irq);
} }
#ifdef CONFIG_LOCAL_TIMERS #ifdef CONFIG_LOCAL_TIMERS
...@@ -412,16 +415,16 @@ static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt) ...@@ -412,16 +415,16 @@ static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)
if (mct_int_type == MCT_INT_SPI) { if (mct_int_type == MCT_INT_SPI) {
if (cpu == 0) { if (cpu == 0) {
mct_tick0_event_irq.dev_id = mevt; mct_tick0_event_irq.dev_id = mevt;
evt->irq = IRQ_MCT_L0; evt->irq = EXYNOS4_IRQ_MCT_L0;
setup_irq(IRQ_MCT_L0, &mct_tick0_event_irq); setup_irq(EXYNOS4_IRQ_MCT_L0, &mct_tick0_event_irq);
} else { } else {
mct_tick1_event_irq.dev_id = mevt; mct_tick1_event_irq.dev_id = mevt;
evt->irq = IRQ_MCT_L1; evt->irq = EXYNOS4_IRQ_MCT_L1;
setup_irq(IRQ_MCT_L1, &mct_tick1_event_irq); setup_irq(EXYNOS4_IRQ_MCT_L1, &mct_tick1_event_irq);
irq_set_affinity(IRQ_MCT_L1, cpumask_of(1)); irq_set_affinity(EXYNOS4_IRQ_MCT_L1, cpumask_of(1));
} }
} else { } else {
enable_percpu_irq(IRQ_MCT_LOCALTIMER, 0); enable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER, 0);
} }
return 0; return 0;
...@@ -437,7 +440,7 @@ static void exynos4_local_timer_stop(struct clock_event_device *evt) ...@@ -437,7 +440,7 @@ static void exynos4_local_timer_stop(struct clock_event_device *evt)
else else
remove_irq(evt->irq, &mct_tick1_event_irq); remove_irq(evt->irq, &mct_tick1_event_irq);
else else
disable_percpu_irq(IRQ_MCT_LOCALTIMER); disable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER);
} }
static struct local_timer_ops exynos4_mct_tick_ops __cpuinitdata = { static struct local_timer_ops exynos4_mct_tick_ops __cpuinitdata = {
...@@ -457,11 +460,11 @@ static void __init exynos4_timer_resources(void) ...@@ -457,11 +460,11 @@ static void __init exynos4_timer_resources(void)
if (mct_int_type == MCT_INT_PPI) { if (mct_int_type == MCT_INT_PPI) {
int err; int err;
err = request_percpu_irq(IRQ_MCT_LOCALTIMER, err = request_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER,
exynos4_mct_tick_isr, "MCT", exynos4_mct_tick_isr, "MCT",
&percpu_mct_tick); &percpu_mct_tick);
WARN(err, "MCT: can't request IRQ %d (%d)\n", WARN(err, "MCT: can't request IRQ %d (%d)\n",
IRQ_MCT_LOCALTIMER, err); EXYNOS_IRQ_MCT_LOCALTIMER, err);
} }
local_timer_register(&exynos4_mct_tick_ops); local_timer_register(&exynos4_mct_tick_ops);
......
...@@ -166,7 +166,10 @@ void __init smp_init_cpus(void) ...@@ -166,7 +166,10 @@ void __init smp_init_cpus(void)
void __iomem *scu_base = scu_base_addr(); void __iomem *scu_base = scu_base_addr();
unsigned int i, ncores; unsigned int i, ncores;
ncores = scu_base ? scu_get_core_count(scu_base) : 1; if (soc_is_exynos5250())
ncores = 2;
else
ncores = scu_base ? scu_get_core_count(scu_base) : 1;
/* sanity check */ /* sanity check */
if (ncores > nr_cpu_ids) { if (ncores > nr_cpu_ids) {
...@@ -183,8 +186,8 @@ void __init smp_init_cpus(void) ...@@ -183,8 +186,8 @@ void __init smp_init_cpus(void)
void __init platform_smp_prepare_cpus(unsigned int max_cpus) void __init platform_smp_prepare_cpus(unsigned int max_cpus)
{ {
if (!soc_is_exynos5250())
scu_enable(scu_base_addr()); scu_enable(scu_base_addr());
/* /*
* Write the address of secondary startup into the * Write the address of secondary startup into the
......
/* /*
* linux/arch/arm/mach-exynos4/setup-i2c0.c * Copyright (c) 2009-2012 Samsung Electronics Co., Ltd.
*
* Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/ * http://www.samsung.com/
* *
* I2C0 GPIO configuration. * I2C0 GPIO configuration.
...@@ -18,9 +16,14 @@ struct platform_device; /* don't need the contents */ ...@@ -18,9 +16,14 @@ struct platform_device; /* don't need the contents */
#include <linux/gpio.h> #include <linux/gpio.h>
#include <plat/iic.h> #include <plat/iic.h>
#include <plat/gpio-cfg.h> #include <plat/gpio-cfg.h>
#include <plat/cpu.h>
void s3c_i2c0_cfg_gpio(struct platform_device *dev) void s3c_i2c0_cfg_gpio(struct platform_device *dev)
{ {
if (soc_is_exynos5250())
/* will be implemented with gpio function */
return;
s3c_gpio_cfgall_range(EXYNOS4_GPD1(0), 2, s3c_gpio_cfgall_range(EXYNOS4_GPD1(0), 2,
S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
} }
...@@ -1186,6 +1186,7 @@ static struct i2c_board_info i2c1_devices[] = { ...@@ -1186,6 +1186,7 @@ static struct i2c_board_info i2c1_devices[] = {
}, },
}; };
#define GPIO_PORT9CR 0xE6051009 #define GPIO_PORT9CR 0xE6051009
#define GPIO_PORT10CR 0xE605100A #define GPIO_PORT10CR 0xE605100A
#define USCCR1 0xE6058144 #define USCCR1 0xE6058144
......
...@@ -1327,15 +1327,6 @@ static struct i2c_board_info i2c1_devices[] = { ...@@ -1327,15 +1327,6 @@ static struct i2c_board_info i2c1_devices[] = {
}, },
}; };
static void __init mackerel_map_io(void)
{
sh7372_map_io();
/* DMA memory at 0xff200000 - 0xffdfffff. The default 2MB size isn't
* enough to allocate the frame buffer memory.
*/
init_consistent_dma_size(12 << 20);
}
#define GPIO_PORT9CR 0xE6051009 #define GPIO_PORT9CR 0xE6051009
#define GPIO_PORT10CR 0xE605100A #define GPIO_PORT10CR 0xE605100A
#define GPIO_PORT167CR 0xE60520A7 #define GPIO_PORT167CR 0xE60520A7
...@@ -1555,7 +1546,7 @@ static void __init mackerel_init(void) ...@@ -1555,7 +1546,7 @@ static void __init mackerel_init(void)
} }
MACHINE_START(MACKEREL, "mackerel") MACHINE_START(MACKEREL, "mackerel")
.map_io = mackerel_map_io, .map_io = sh7372_map_io,
.init_early = sh7372_add_early_devices, .init_early = sh7372_add_early_devices,
.init_irq = sh7372_init_irq, .init_irq = sh7372_init_irq,
.handle_irq = shmobile_handle_irq_intc, .handle_irq = shmobile_handle_irq_intc,
......
...@@ -31,6 +31,7 @@ ...@@ -31,6 +31,7 @@
#include <linux/sh_intc.h> #include <linux/sh_intc.h>
#include <linux/sh_timer.h> #include <linux/sh_timer.h>
#include <linux/pm_domain.h> #include <linux/pm_domain.h>
#include <linux/dma-mapping.h>
#include <mach/hardware.h> #include <mach/hardware.h>
#include <mach/sh7372.h> #include <mach/sh7372.h>
#include <mach/common.h> #include <mach/common.h>
...@@ -54,6 +55,12 @@ static struct map_desc sh7372_io_desc[] __initdata = { ...@@ -54,6 +55,12 @@ static struct map_desc sh7372_io_desc[] __initdata = {
void __init sh7372_map_io(void) void __init sh7372_map_io(void)
{ {
iotable_init(sh7372_io_desc, ARRAY_SIZE(sh7372_io_desc)); iotable_init(sh7372_io_desc, ARRAY_SIZE(sh7372_io_desc));
/*
* DMA memory at 0xff200000 - 0xffdfffff. The default 2MB size isn't
* enough to allocate the frame buffer memory.
*/
init_consistent_dma_size(12 << 20);
} }
/* SCIFA0 */ /* SCIFA0 */
......
...@@ -8,6 +8,7 @@ obj-y += timer.o ...@@ -8,6 +8,7 @@ obj-y += timer.o
obj-y += pinmux.o obj-y += pinmux.o
obj-y += fuse.o obj-y += fuse.o
obj-y += pmc.o obj-y += pmc.o
obj-y += flowctrl.o
obj-$(CONFIG_CPU_IDLE) += cpuidle.o obj-$(CONFIG_CPU_IDLE) += cpuidle.o
obj-$(CONFIG_CPU_IDLE) += sleep.o obj-$(CONFIG_CPU_IDLE) += sleep.o
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += powergate.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += powergate.o
...@@ -18,6 +19,7 @@ obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += pinmux-tegra30-tables.o ...@@ -18,6 +19,7 @@ obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += pinmux-tegra30-tables.o
obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += board-dt-tegra30.o obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += board-dt-tegra30.o
obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_clocks.o obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_clocks.o
obj-$(CONFIG_SMP) += platsmp.o headsmp.o obj-$(CONFIG_SMP) += platsmp.o headsmp.o
obj-$(CONFIG_SMP) += reset.o
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
obj-$(CONFIG_TEGRA_SYSTEM_DMA) += dma.o apbio.o obj-$(CONFIG_TEGRA_SYSTEM_DMA) += dma.o apbio.o
obj-$(CONFIG_CPU_FREQ) += cpu-tegra.o obj-$(CONFIG_CPU_FREQ) += cpu-tegra.o
......
...@@ -56,7 +56,7 @@ struct of_dev_auxdata tegra30_auxdata_lookup[] __initdata = { ...@@ -56,7 +56,7 @@ struct of_dev_auxdata tegra30_auxdata_lookup[] __initdata = {
static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = { static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
/* name parent rate enabled */ /* name parent rate enabled */
{ "uartd", "pll_p", 408000000, true }, { "uarta", "pll_p", 408000000, true },
{ NULL, NULL, 0, 0}, { NULL, NULL, 0, 0},
}; };
......
...@@ -27,6 +27,7 @@ ...@@ -27,6 +27,7 @@
#include <asm/hardware/gic.h> #include <asm/hardware/gic.h>
#include <mach/iomap.h> #include <mach/iomap.h>
#include <mach/powergate.h>
#include "board.h" #include "board.h"
#include "clock.h" #include "clock.h"
...@@ -118,13 +119,16 @@ void __init tegra20_init_early(void) ...@@ -118,13 +119,16 @@ void __init tegra20_init_early(void)
tegra_clk_init_from_table(tegra20_clk_init_table); tegra_clk_init_from_table(tegra20_clk_init_table);
tegra_init_cache(0x331, 0x441); tegra_init_cache(0x331, 0x441);
tegra_pmc_init(); tegra_pmc_init();
tegra_powergate_init();
} }
#endif #endif
#ifdef CONFIG_ARCH_TEGRA_3x_SOC #ifdef CONFIG_ARCH_TEGRA_3x_SOC
void __init tegra30_init_early(void) void __init tegra30_init_early(void)
{ {
tegra_init_fuse();
tegra30_init_clocks(); tegra30_init_clocks();
tegra_init_cache(0x441, 0x551); tegra_init_cache(0x441, 0x551);
tegra_pmc_init(); tegra_pmc_init();
tegra_powergate_init();
} }
#endif #endif
/*
* arch/arm/mach-tegra/flowctrl.c
*
* functions and macros to control the flowcontroller
*
* Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/io.h>
#include <mach/iomap.h>
#include "flowctrl.h"
u8 flowctrl_offset_halt_cpu[] = {
FLOW_CTRL_HALT_CPU0_EVENTS,
FLOW_CTRL_HALT_CPU1_EVENTS,
FLOW_CTRL_HALT_CPU1_EVENTS + 8,
FLOW_CTRL_HALT_CPU1_EVENTS + 16,
};
u8 flowctrl_offset_cpu_csr[] = {
FLOW_CTRL_CPU0_CSR,
FLOW_CTRL_CPU1_CSR,
FLOW_CTRL_CPU1_CSR + 8,
FLOW_CTRL_CPU1_CSR + 16,
};
static void flowctrl_update(u8 offset, u32 value)
{
void __iomem *addr = IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + offset;
writel(value, addr);
/* ensure the update has reached the flow controller */
wmb();
readl_relaxed(addr);
}
void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value)
{
return flowctrl_update(flowctrl_offset_halt_cpu[cpuid], value);
}
void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value)
{
return flowctrl_update(flowctrl_offset_cpu_csr[cpuid], value);
}
...@@ -34,4 +34,9 @@ ...@@ -34,4 +34,9 @@
#define FLOW_CTRL_HALT_CPU1_EVENTS 0x14 #define FLOW_CTRL_HALT_CPU1_EVENTS 0x14
#define FLOW_CTRL_CPU1_CSR 0x18 #define FLOW_CTRL_CPU1_CSR 0x18
#ifndef __ASSEMBLY__
void flowctrl_write_cpu_csr(unsigned int cpuid, u32 value);
void flowctrl_write_cpu_halt(unsigned int cpuid, u32 value);
#endif
#endif #endif
...@@ -34,6 +34,7 @@ ...@@ -34,6 +34,7 @@
int tegra_sku_id; int tegra_sku_id;
int tegra_cpu_process_id; int tegra_cpu_process_id;
int tegra_core_process_id; int tegra_core_process_id;
int tegra_chip_id;
enum tegra_revision tegra_revision; enum tegra_revision tegra_revision;
/* The BCT to use at boot is specified by board straps that can be read /* The BCT to use at boot is specified by board straps that can be read
...@@ -66,12 +67,9 @@ static inline bool get_spare_fuse(int bit) ...@@ -66,12 +67,9 @@ static inline bool get_spare_fuse(int bit)
return tegra_fuse_readl(FUSE_SPARE_BIT + bit * 4); return tegra_fuse_readl(FUSE_SPARE_BIT + bit * 4);
} }
static enum tegra_revision tegra_get_revision(void) static enum tegra_revision tegra_get_revision(u32 id)
{ {
void __iomem *chip_id = IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804;
u32 id = readl(chip_id);
u32 minor_rev = (id >> 16) & 0xf; u32 minor_rev = (id >> 16) & 0xf;
u32 chipid = (id >> 8) & 0xff;
switch (minor_rev) { switch (minor_rev) {
case 1: case 1:
...@@ -79,7 +77,8 @@ static enum tegra_revision tegra_get_revision(void) ...@@ -79,7 +77,8 @@ static enum tegra_revision tegra_get_revision(void)
case 2: case 2:
return TEGRA_REVISION_A02; return TEGRA_REVISION_A02;
case 3: case 3:
if (chipid == 0x20 && (get_spare_fuse(18) || get_spare_fuse(19))) if (tegra_chip_id == TEGRA20 &&
(get_spare_fuse(18) || get_spare_fuse(19)))
return TEGRA_REVISION_A03p; return TEGRA_REVISION_A03p;
else else
return TEGRA_REVISION_A03; return TEGRA_REVISION_A03;
...@@ -92,6 +91,8 @@ static enum tegra_revision tegra_get_revision(void) ...@@ -92,6 +91,8 @@ static enum tegra_revision tegra_get_revision(void)
void tegra_init_fuse(void) void tegra_init_fuse(void)
{ {
u32 id;
u32 reg = readl(IO_TO_VIRT(TEGRA_CLK_RESET_BASE + 0x48)); u32 reg = readl(IO_TO_VIRT(TEGRA_CLK_RESET_BASE + 0x48));
reg |= 1 << 28; reg |= 1 << 28;
writel(reg, IO_TO_VIRT(TEGRA_CLK_RESET_BASE + 0x48)); writel(reg, IO_TO_VIRT(TEGRA_CLK_RESET_BASE + 0x48));
...@@ -108,10 +109,13 @@ void tegra_init_fuse(void) ...@@ -108,10 +109,13 @@ void tegra_init_fuse(void)
reg = tegra_apb_readl(TEGRA_APB_MISC_BASE + STRAP_OPT); reg = tegra_apb_readl(TEGRA_APB_MISC_BASE + STRAP_OPT);
tegra_bct_strapping = (reg & RAM_ID_MASK) >> RAM_CODE_SHIFT; tegra_bct_strapping = (reg & RAM_ID_MASK) >> RAM_CODE_SHIFT;
tegra_revision = tegra_get_revision(); id = readl_relaxed(IO_ADDRESS(TEGRA_APB_MISC_BASE) + 0x804);
tegra_chip_id = (id >> 8) & 0xff;
tegra_revision = tegra_get_revision(id);
pr_info("Tegra Revision: %s SKU: %d CPU Process: %d Core Process: %d\n", pr_info("Tegra Revision: %s SKU: %d CPU Process: %d Core Process: %d\n",
tegra_revision_name[tegra_get_revision()], tegra_revision_name[tegra_revision],
tegra_sku_id, tegra_cpu_process_id, tegra_sku_id, tegra_cpu_process_id,
tegra_core_process_id); tegra_core_process_id);
} }
......
...@@ -35,9 +35,13 @@ enum tegra_revision { ...@@ -35,9 +35,13 @@ enum tegra_revision {
#define SKU_ID_AP25E 27 #define SKU_ID_AP25E 27
#define SKU_ID_T25E 28 #define SKU_ID_T25E 28
#define TEGRA20 0x20
#define TEGRA30 0x30
extern int tegra_sku_id; extern int tegra_sku_id;
extern int tegra_cpu_process_id; extern int tegra_cpu_process_id;
extern int tegra_core_process_id; extern int tegra_core_process_id;
extern int tegra_chip_id;
extern enum tegra_revision tegra_revision; extern enum tegra_revision tegra_revision;
extern int tegra_bct_strapping; extern int tegra_bct_strapping;
......
#include <linux/linkage.h> #include <linux/linkage.h>
#include <linux/init.h> #include <linux/init.h>
#include <asm/cache.h>
#include <mach/iomap.h>
#include "flowctrl.h"
#include "reset.h"
#define APB_MISC_GP_HIDREV 0x804
#define PMC_SCRATCH41 0x140
#define RESET_DATA(x) ((TEGRA_RESET_##x)*4)
.macro mov32, reg, val
movw \reg, #:lower16:\val
movt \reg, #:upper16:\val
.endm
.section ".text.head", "ax" .section ".text.head", "ax"
__CPUINIT __CPUINIT
...@@ -47,15 +64,149 @@ ENTRY(v7_invalidate_l1) ...@@ -47,15 +64,149 @@ ENTRY(v7_invalidate_l1)
mov pc, lr mov pc, lr
ENDPROC(v7_invalidate_l1) ENDPROC(v7_invalidate_l1)
ENTRY(tegra_secondary_startup) ENTRY(tegra_secondary_startup)
msr cpsr_fsxc, #0xd3
bl v7_invalidate_l1 bl v7_invalidate_l1
mrc p15, 0, r0, c0, c0, 5 /* Enable coresight */
and r0, r0, #15 mov32 r0, 0xC5ACCE55
ldr r1, =0x6000f100 mcr p14, 0, r0, c7, c12, 6
str r0, [r1]
1: ldr r2, [r1]
cmp r0, r2
beq 1b
b secondary_startup b secondary_startup
ENDPROC(tegra_secondary_startup) ENDPROC(tegra_secondary_startup)
.align L1_CACHE_SHIFT
ENTRY(__tegra_cpu_reset_handler_start)
/*
* __tegra_cpu_reset_handler:
*
* Common handler for all CPU reset events.
*
* Register usage within the reset handler:
*
* R7 = CPU present (to the OS) mask
* R8 = CPU in LP1 state mask
* R9 = CPU in LP2 state mask
* R10 = CPU number
* R11 = CPU mask
* R12 = pointer to reset handler data
*
* NOTE: This code is copied to IRAM. All code and data accesses
* must be position-independent.
*/
.align L1_CACHE_SHIFT
ENTRY(__tegra_cpu_reset_handler)
cpsid aif, 0x13 @ SVC mode, interrupts disabled
mrc p15, 0, r10, c0, c0, 5 @ MPIDR
and r10, r10, #0x3 @ R10 = CPU number
mov r11, #1
mov r11, r11, lsl r10 @ R11 = CPU mask
adr r12, __tegra_cpu_reset_handler_data
#ifdef CONFIG_SMP
/* Does the OS know about this CPU? */
ldr r7, [r12, #RESET_DATA(MASK_PRESENT)]
tst r7, r11 @ if !present
bleq __die @ CPU not present (to OS)
#endif
#ifdef CONFIG_ARCH_TEGRA_2x_SOC
/* Are we on Tegra20? */
mov32 r6, TEGRA_APB_MISC_BASE
ldr r0, [r6, #APB_MISC_GP_HIDREV]
and r0, r0, #0xff00
cmp r0, #(0x20 << 8)
bne 1f
/* If not CPU0, don't let CPU0 reset CPU1 now that CPU1 is coming up. */
mov32 r6, TEGRA_PMC_BASE
mov r0, #0
cmp r10, #0
strne r0, [r6, #PMC_SCRATCH41]
1:
#endif
#ifdef CONFIG_SMP
/*
* Can only be secondary boot (initial or hotplug) but CPU 0
* cannot be here.
*/
cmp r10, #0
bleq __die @ CPU0 cannot be here
ldr lr, [r12, #RESET_DATA(STARTUP_SECONDARY)]
cmp lr, #0
bleq __die @ no secondary startup handler
bx lr
#endif
/*
* We don't know why the CPU reset. Just kill it.
* The LR register will contain the address we died at + 4.
*/
__die:
sub lr, lr, #4
mov32 r7, TEGRA_PMC_BASE
str lr, [r7, #PMC_SCRATCH41]
mov32 r7, TEGRA_CLK_RESET_BASE
/* Are we on Tegra20? */
mov32 r6, TEGRA_APB_MISC_BASE
ldr r0, [r6, #APB_MISC_GP_HIDREV]
and r0, r0, #0xff00
cmp r0, #(0x20 << 8)
bne 1f
#ifdef CONFIG_ARCH_TEGRA_2x_SOC
mov32 r0, 0x1111
mov r1, r0, lsl r10
str r1, [r7, #0x340] @ CLK_RST_CPU_CMPLX_SET
#endif
1:
#ifdef CONFIG_ARCH_TEGRA_3x_SOC
mov32 r6, TEGRA_FLOW_CTRL_BASE
cmp r10, #0
moveq r1, #FLOW_CTRL_HALT_CPU0_EVENTS
moveq r2, #FLOW_CTRL_CPU0_CSR
movne r1, r10, lsl #3
addne r2, r1, #(FLOW_CTRL_CPU1_CSR-8)
addne r1, r1, #(FLOW_CTRL_HALT_CPU1_EVENTS-8)
/* Clear CPU "event" and "interrupt" flags and power gate
it when halting but not before it is in the "WFI" state. */
ldr r0, [r6, +r2]
orr r0, r0, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
orr r0, r0, #FLOW_CTRL_CSR_ENABLE
str r0, [r6, +r2]
/* Unconditionally halt this CPU */
mov r0, #FLOW_CTRL_WAITEVENT
str r0, [r6, +r1]
ldr r0, [r6, +r1] @ memory barrier
dsb
isb
wfi @ CPU should be power gated here
/* If the CPU didn't power gate above just kill it's clock. */
mov r0, r11, lsl #8
str r0, [r7, #348] @ CLK_CPU_CMPLX_SET
#endif
/* If the CPU still isn't dead, just spin here. */
b .
ENDPROC(__tegra_cpu_reset_handler)
.align L1_CACHE_SHIFT
.type __tegra_cpu_reset_handler_data, %object
.globl __tegra_cpu_reset_handler_data
__tegra_cpu_reset_handler_data:
.rept TEGRA_RESET_DATA_SIZE
.long 0
.endr
.align L1_CACHE_SHIFT
ENTRY(__tegra_cpu_reset_handler_end)
...@@ -113,6 +113,9 @@ ...@@ -113,6 +113,9 @@
#define TEGRA_AHB_GIZMO_BASE 0x6000C004 #define TEGRA_AHB_GIZMO_BASE 0x6000C004
#define TEGRA_AHB_GIZMO_SIZE 0x10C #define TEGRA_AHB_GIZMO_SIZE 0x10C
#define TEGRA_SB_BASE 0x6000C200
#define TEGRA_SB_SIZE 256
#define TEGRA_STATMON_BASE 0x6000C400 #define TEGRA_STATMON_BASE 0x6000C400
#define TEGRA_STATMON_SIZE SZ_1K #define TEGRA_STATMON_SIZE SZ_1K
......
...@@ -27,8 +27,21 @@ ...@@ -27,8 +27,21 @@
#define TEGRA_POWERGATE_VDEC 4 #define TEGRA_POWERGATE_VDEC 4
#define TEGRA_POWERGATE_L2 5 #define TEGRA_POWERGATE_L2 5
#define TEGRA_POWERGATE_MPE 6 #define TEGRA_POWERGATE_MPE 6
#define TEGRA_NUM_POWERGATE 7 #define TEGRA_POWERGATE_HEG 7
#define TEGRA_POWERGATE_SATA 8
#define TEGRA_POWERGATE_CPU1 9
#define TEGRA_POWERGATE_CPU2 10
#define TEGRA_POWERGATE_CPU3 11
#define TEGRA_POWERGATE_CELP 12
#define TEGRA_POWERGATE_3D1 13
#define TEGRA_POWERGATE_CPU0 TEGRA_POWERGATE_CPU
#define TEGRA_POWERGATE_3D0 TEGRA_POWERGATE_3D
int __init tegra_powergate_init(void);
int tegra_cpu_powergate_id(int cpuid);
int tegra_powergate_is_powered(int id);
int tegra_powergate_power_on(int id); int tegra_powergate_power_on(int id);
int tegra_powergate_power_off(int id); int tegra_powergate_power_off(int id);
int tegra_powergate_remove_clamping(int id); int tegra_powergate_remove_clamping(int id);
......
...@@ -24,19 +24,31 @@ ...@@ -24,19 +24,31 @@
#include <asm/mach-types.h> #include <asm/mach-types.h>
#include <asm/smp_scu.h> #include <asm/smp_scu.h>
#include <mach/clk.h>
#include <mach/iomap.h> #include <mach/iomap.h>
#include <mach/powergate.h>
#include "fuse.h"
#include "flowctrl.h"
#include "reset.h"
extern void tegra_secondary_startup(void); extern void tegra_secondary_startup(void);
static DEFINE_SPINLOCK(boot_lock);
static void __iomem *scu_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE); static void __iomem *scu_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE);
#define EVP_CPU_RESET_VECTOR \ #define EVP_CPU_RESET_VECTOR \
(IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE) + 0x100) (IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE) + 0x100)
#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX \ #define CLK_RST_CONTROLLER_CLK_CPU_CMPLX \
(IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x4c) (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x4c)
#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET \
(IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x340)
#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR \ #define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR \
(IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x344) (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x344)
#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR \
(IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x34c)
#define CPU_CLOCK(cpu) (0x1<<(8+cpu))
#define CPU_RESET(cpu) (0x1111ul<<(cpu))
void __cpuinit platform_secondary_init(unsigned int cpu) void __cpuinit platform_secondary_init(unsigned int cpu)
{ {
...@@ -47,63 +59,106 @@ void __cpuinit platform_secondary_init(unsigned int cpu) ...@@ -47,63 +59,106 @@ void __cpuinit platform_secondary_init(unsigned int cpu)
*/ */
gic_secondary_init(0); gic_secondary_init(0);
/*
* Synchronise with the boot thread.
*/
spin_lock(&boot_lock);
spin_unlock(&boot_lock);
} }
int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle) static int tegra20_power_up_cpu(unsigned int cpu)
{ {
unsigned long old_boot_vector;
unsigned long boot_vector;
unsigned long timeout;
u32 reg; u32 reg;
/* /* Enable the CPU clock. */
* set synchronisation state between this boot processor reg = readl(CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
* and the secondary one writel(reg & ~CPU_CLOCK(cpu), CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
*/ barrier();
spin_lock(&boot_lock); reg = readl(CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
/* Clear flow controller CSR. */
flowctrl_write_cpu_csr(cpu, 0);
/* set the reset vector to point to the secondary_startup routine */ return 0;
}
boot_vector = virt_to_phys(tegra_secondary_startup); static int tegra30_power_up_cpu(unsigned int cpu)
old_boot_vector = readl(EVP_CPU_RESET_VECTOR); {
writel(boot_vector, EVP_CPU_RESET_VECTOR); u32 reg;
int ret, pwrgateid;
unsigned long timeout;
/* enable cpu clock on cpu1 */ pwrgateid = tegra_cpu_powergate_id(cpu);
reg = readl(CLK_RST_CONTROLLER_CLK_CPU_CMPLX); if (pwrgateid < 0)
writel(reg & ~(1<<9), CLK_RST_CONTROLLER_CLK_CPU_CMPLX); return pwrgateid;
/* If this is the first boot, toggle powergates directly. */
if (!tegra_powergate_is_powered(pwrgateid)) {
ret = tegra_powergate_power_on(pwrgateid);
if (ret)
return ret;
/* Wait for the power to come up. */
timeout = jiffies + 10*HZ;
while (tegra_powergate_is_powered(pwrgateid)) {
if (time_after(jiffies, timeout))
return -ETIMEDOUT;
udelay(10);
}
}
reg = (1<<13) | (1<<9) | (1<<5) | (1<<1); /* CPU partition is powered. Enable the CPU clock. */
writel(reg, CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR); writel(CPU_CLOCK(cpu), CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
reg = readl(CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
udelay(10);
smp_wmb(); /* Remove I/O clamps. */
flush_cache_all(); ret = tegra_powergate_remove_clamping(pwrgateid);
udelay(10);
/* unhalt the cpu */ /* Clear flow controller CSR. */
writel(0, IO_ADDRESS(TEGRA_FLOW_CTRL_BASE) + 0x14); flowctrl_write_cpu_csr(cpu, 0);
timeout = jiffies + (1 * HZ); return 0;
while (time_before(jiffies, timeout)) { }
if (readl(EVP_CPU_RESET_VECTOR) != boot_vector)
break; int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
udelay(10); {
} int status;
/* put the old boot vector back */ /*
writel(old_boot_vector, EVP_CPU_RESET_VECTOR); * Force the CPU into reset. The CPU must remain in reset when the
* flow controller state is cleared (which will cause the flow
* controller to stop driving reset if the CPU has been power-gated
* via the flow controller). This will have no effect on first boot
* of the CPU since it should already be in reset.
*/
writel(CPU_RESET(cpu), CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
dmb();
/* /*
* now the secondary core is starting up let it run its * Unhalt the CPU. If the flow controller was used to power-gate the
* calibrations, then wait for it to finish * CPU this will cause the flow controller to stop driving reset.
* The CPU will remain in reset because the clock and reset block
* is now driving reset.
*/ */
spin_unlock(&boot_lock); flowctrl_write_cpu_halt(cpu, 0);
switch (tegra_chip_id) {
case TEGRA20:
status = tegra20_power_up_cpu(cpu);
break;
case TEGRA30:
status = tegra30_power_up_cpu(cpu);
break;
default:
status = -EINVAL;
break;
}
return 0; if (status)
goto done;
/* Take the CPU out of reset. */
writel(CPU_RESET(cpu), CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
wmb();
done:
return status;
} }
/* /*
...@@ -128,6 +183,6 @@ void __init smp_init_cpus(void) ...@@ -128,6 +183,6 @@ void __init smp_init_cpus(void)
void __init platform_smp_prepare_cpus(unsigned int max_cpus) void __init platform_smp_prepare_cpus(unsigned int max_cpus)
{ {
tegra_cpu_reset_handler_init();
scu_enable(scu_base); scu_enable(scu_base);
} }
...@@ -31,6 +31,8 @@ ...@@ -31,6 +31,8 @@
#include <mach/iomap.h> #include <mach/iomap.h>
#include <mach/powergate.h> #include <mach/powergate.h>
#include "fuse.h"
#define PWRGATE_TOGGLE 0x30 #define PWRGATE_TOGGLE 0x30
#define PWRGATE_TOGGLE_START (1 << 8) #define PWRGATE_TOGGLE_START (1 << 8)
...@@ -38,6 +40,16 @@ ...@@ -38,6 +40,16 @@
#define PWRGATE_STATUS 0x38 #define PWRGATE_STATUS 0x38
static int tegra_num_powerdomains;
static int tegra_num_cpu_domains;
static u8 *tegra_cpu_domains;
static u8 tegra30_cpu_domains[] = {
TEGRA_POWERGATE_CPU0,
TEGRA_POWERGATE_CPU1,
TEGRA_POWERGATE_CPU2,
TEGRA_POWERGATE_CPU3,
};
static DEFINE_SPINLOCK(tegra_powergate_lock); static DEFINE_SPINLOCK(tegra_powergate_lock);
static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE); static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
...@@ -75,7 +87,7 @@ static int tegra_powergate_set(int id, bool new_state) ...@@ -75,7 +87,7 @@ static int tegra_powergate_set(int id, bool new_state)
int tegra_powergate_power_on(int id) int tegra_powergate_power_on(int id)
{ {
if (id < 0 || id >= TEGRA_NUM_POWERGATE) if (id < 0 || id >= tegra_num_powerdomains)
return -EINVAL; return -EINVAL;
return tegra_powergate_set(id, true); return tegra_powergate_set(id, true);
...@@ -83,17 +95,18 @@ int tegra_powergate_power_on(int id) ...@@ -83,17 +95,18 @@ int tegra_powergate_power_on(int id)
int tegra_powergate_power_off(int id) int tegra_powergate_power_off(int id)
{ {
if (id < 0 || id >= TEGRA_NUM_POWERGATE) if (id < 0 || id >= tegra_num_powerdomains)
return -EINVAL; return -EINVAL;
return tegra_powergate_set(id, false); return tegra_powergate_set(id, false);
} }
static bool tegra_powergate_is_powered(int id) int tegra_powergate_is_powered(int id)
{ {
u32 status; u32 status;
WARN_ON(id < 0 || id >= TEGRA_NUM_POWERGATE); if (id < 0 || id >= tegra_num_powerdomains)
return -EINVAL;
status = pmc_read(PWRGATE_STATUS) & (1 << id); status = pmc_read(PWRGATE_STATUS) & (1 << id);
return !!status; return !!status;
...@@ -103,7 +116,7 @@ int tegra_powergate_remove_clamping(int id) ...@@ -103,7 +116,7 @@ int tegra_powergate_remove_clamping(int id)
{ {
u32 mask; u32 mask;
if (id < 0 || id >= TEGRA_NUM_POWERGATE) if (id < 0 || id >= tegra_num_powerdomains)
return -EINVAL; return -EINVAL;
/* /*
...@@ -156,6 +169,34 @@ int tegra_powergate_sequence_power_up(int id, struct clk *clk) ...@@ -156,6 +169,34 @@ int tegra_powergate_sequence_power_up(int id, struct clk *clk)
return ret; return ret;
} }
int tegra_cpu_powergate_id(int cpuid)
{
if (cpuid > 0 && cpuid < tegra_num_cpu_domains)
return tegra_cpu_domains[cpuid];
return -EINVAL;
}
int __init tegra_powergate_init(void)
{
switch (tegra_chip_id) {
case TEGRA20:
tegra_num_powerdomains = 7;
break;
case TEGRA30:
tegra_num_powerdomains = 14;
tegra_num_cpu_domains = 4;
tegra_cpu_domains = tegra30_cpu_domains;
break;
default:
/* Unknown Tegra variant. Disable powergating */
tegra_num_powerdomains = 0;
break;
}
return 0;
}
#ifdef CONFIG_DEBUG_FS #ifdef CONFIG_DEBUG_FS
static const char * const powergate_name[] = { static const char * const powergate_name[] = {
...@@ -175,7 +216,7 @@ static int powergate_show(struct seq_file *s, void *data) ...@@ -175,7 +216,7 @@ static int powergate_show(struct seq_file *s, void *data)
seq_printf(s, " powergate powered\n"); seq_printf(s, " powergate powered\n");
seq_printf(s, "------------------\n"); seq_printf(s, "------------------\n");
for (i = 0; i < TEGRA_NUM_POWERGATE; i++) for (i = 0; i < tegra_num_powerdomains; i++)
seq_printf(s, " %9s %7s\n", powergate_name[i], seq_printf(s, " %9s %7s\n", powergate_name[i],
tegra_powergate_is_powered(i) ? "yes" : "no"); tegra_powergate_is_powered(i) ? "yes" : "no");
return 0; return 0;
......
/*
* arch/arm/mach-tegra/reset.c
*
* Copyright (C) 2011,2012 NVIDIA Corporation.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <linux/init.h>
#include <linux/io.h>
#include <linux/cpumask.h>
#include <linux/bitops.h>
#include <asm/cacheflush.h>
#include <asm/hardware/cache-l2x0.h>
#include <mach/iomap.h>
#include <mach/irammap.h>
#include "reset.h"
#include "fuse.h"
#define TEGRA_IRAM_RESET_BASE (TEGRA_IRAM_BASE + \
TEGRA_IRAM_RESET_HANDLER_OFFSET)
static bool is_enabled;
static void tegra_cpu_reset_handler_enable(void)
{
void __iomem *iram_base = IO_ADDRESS(TEGRA_IRAM_RESET_BASE);
void __iomem *evp_cpu_reset =
IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE + 0x100);
void __iomem *sb_ctrl = IO_ADDRESS(TEGRA_SB_BASE);
u32 reg;
BUG_ON(is_enabled);
BUG_ON(tegra_cpu_reset_handler_size > TEGRA_IRAM_RESET_HANDLER_SIZE);
memcpy(iram_base, (void *)__tegra_cpu_reset_handler_start,
tegra_cpu_reset_handler_size);
/*
* NOTE: This must be the one and only write to the EVP CPU reset
* vector in the entire system.
*/
writel(TEGRA_IRAM_RESET_BASE + tegra_cpu_reset_handler_offset,
evp_cpu_reset);
wmb();
reg = readl(evp_cpu_reset);
/*
* Prevent further modifications to the physical reset vector.
* NOTE: Has no effect on chips prior to Tegra30.
*/
if (tegra_chip_id != TEGRA20) {
reg = readl(sb_ctrl);
reg |= 2;
writel(reg, sb_ctrl);
wmb();
}
is_enabled = true;
}
void __init tegra_cpu_reset_handler_init(void)
{
#ifdef CONFIG_SMP
__tegra_cpu_reset_handler_data[TEGRA_RESET_MASK_PRESENT] =
*((u32 *)cpu_present_mask);
__tegra_cpu_reset_handler_data[TEGRA_RESET_STARTUP_SECONDARY] =
virt_to_phys((void *)tegra_secondary_startup);
#endif
tegra_cpu_reset_handler_enable();
}
/*
* arch/arm/mach-tegra/reset.h
*
* CPU reset dispatcher.
*
* Copyright (c) 2011, NVIDIA Corporation.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __MACH_TEGRA_RESET_H
#define __MACH_TEGRA_RESET_H
#define TEGRA_RESET_MASK_PRESENT 0
#define TEGRA_RESET_MASK_LP1 1
#define TEGRA_RESET_MASK_LP2 2
#define TEGRA_RESET_STARTUP_SECONDARY 3
#define TEGRA_RESET_STARTUP_LP2 4
#define TEGRA_RESET_STARTUP_LP1 5
#define TEGRA_RESET_DATA_SIZE 6
#ifndef __ASSEMBLY__
extern unsigned long __tegra_cpu_reset_handler_data[TEGRA_RESET_DATA_SIZE];
void __tegra_cpu_reset_handler_start(void);
void __tegra_cpu_reset_handler(void);
void __tegra_cpu_reset_handler_end(void);
void tegra_secondary_startup(void);
#define tegra_cpu_reset_handler_offset \
((u32)__tegra_cpu_reset_handler - \
(u32)__tegra_cpu_reset_handler_start)
#define tegra_cpu_reset_handler_size \
(__tegra_cpu_reset_handler_end - \
__tegra_cpu_reset_handler_start)
void __init tegra_cpu_reset_handler_init(void);
#endif
#endif
...@@ -27,6 +27,7 @@ config MACH_MOP500 ...@@ -27,6 +27,7 @@ config MACH_MOP500
select UX500_SOC_DB8500 select UX500_SOC_DB8500
select I2C select I2C
select I2C_NOMADIK select I2C_NOMADIK
select SOC_BUS
help help
Include support for the MOP500 development platform. Include support for the MOP500 development platform.
......
...@@ -99,7 +99,7 @@ static struct mmci_platform_data mop500_sdi0_data = { ...@@ -99,7 +99,7 @@ static struct mmci_platform_data mop500_sdi0_data = {
#endif #endif
}; };
static void sdi0_configure(void) static void sdi0_configure(struct device *parent)
{ {
int ret; int ret;
...@@ -118,15 +118,15 @@ static void sdi0_configure(void) ...@@ -118,15 +118,15 @@ static void sdi0_configure(void)
gpio_direction_output(sdi0_en, 1); gpio_direction_output(sdi0_en, 1);
/* Add the device, force v2 to subrevision 1 */ /* Add the device, force v2 to subrevision 1 */
db8500_add_sdi0(&mop500_sdi0_data, U8500_SDI_V2_PERIPHID); db8500_add_sdi0(parent, &mop500_sdi0_data, U8500_SDI_V2_PERIPHID);
} }
void mop500_sdi_tc35892_init(void) void mop500_sdi_tc35892_init(struct device *parent)
{ {
mop500_sdi0_data.gpio_cd = GPIO_SDMMC_CD; mop500_sdi0_data.gpio_cd = GPIO_SDMMC_CD;
sdi0_en = GPIO_SDMMC_EN; sdi0_en = GPIO_SDMMC_EN;
sdi0_vsel = GPIO_SDMMC_1V8_3V_SEL; sdi0_vsel = GPIO_SDMMC_1V8_3V_SEL;
sdi0_configure(); sdi0_configure(parent);
} }
/* /*
...@@ -241,12 +241,13 @@ static struct mmci_platform_data mop500_sdi4_data = { ...@@ -241,12 +241,13 @@ static struct mmci_platform_data mop500_sdi4_data = {
#endif #endif
}; };
void __init mop500_sdi_init(void) void __init mop500_sdi_init(struct device *parent)
{ {
/* PoP:ed eMMC */ /* PoP:ed eMMC */
db8500_add_sdi2(&mop500_sdi2_data, U8500_SDI_V2_PERIPHID); db8500_add_sdi2(parent, &mop500_sdi2_data, U8500_SDI_V2_PERIPHID);
/* On-board eMMC */ /* On-board eMMC */
db8500_add_sdi4(&mop500_sdi4_data, U8500_SDI_V2_PERIPHID); db8500_add_sdi4(parent, &mop500_sdi4_data, U8500_SDI_V2_PERIPHID);
/* /*
* On boards with the TC35892 GPIO expander, sdi0 will finally * On boards with the TC35892 GPIO expander, sdi0 will finally
* be added when the TC35892 initializes and calls * be added when the TC35892 initializes and calls
...@@ -254,31 +255,31 @@ void __init mop500_sdi_init(void) ...@@ -254,31 +255,31 @@ void __init mop500_sdi_init(void)
*/ */
} }
void __init snowball_sdi_init(void) void __init snowball_sdi_init(struct device *parent)
{ {
/* On Snowball MMC_CAP_SD_HIGHSPEED isn't supported (Hardware issue?) */ /* On Snowball MMC_CAP_SD_HIGHSPEED isn't supported (Hardware issue?) */
mop500_sdi0_data.capabilities &= ~MMC_CAP_SD_HIGHSPEED; mop500_sdi0_data.capabilities &= ~MMC_CAP_SD_HIGHSPEED;
/* On-board eMMC */ /* On-board eMMC */
db8500_add_sdi4(&mop500_sdi4_data, U8500_SDI_V2_PERIPHID); db8500_add_sdi4(parent, &mop500_sdi4_data, U8500_SDI_V2_PERIPHID);
/* External Micro SD slot */ /* External Micro SD slot */
mop500_sdi0_data.gpio_cd = SNOWBALL_SDMMC_CD_GPIO; mop500_sdi0_data.gpio_cd = SNOWBALL_SDMMC_CD_GPIO;
mop500_sdi0_data.cd_invert = true; mop500_sdi0_data.cd_invert = true;
sdi0_en = SNOWBALL_SDMMC_EN_GPIO; sdi0_en = SNOWBALL_SDMMC_EN_GPIO;
sdi0_vsel = SNOWBALL_SDMMC_1V8_3V_GPIO; sdi0_vsel = SNOWBALL_SDMMC_1V8_3V_GPIO;
sdi0_configure(); sdi0_configure(parent);
} }
void __init hrefv60_sdi_init(void) void __init hrefv60_sdi_init(struct device *parent)
{ {
/* PoP:ed eMMC */ /* PoP:ed eMMC */
db8500_add_sdi2(&mop500_sdi2_data, U8500_SDI_V2_PERIPHID); db8500_add_sdi2(parent, &mop500_sdi2_data, U8500_SDI_V2_PERIPHID);
/* On-board eMMC */ /* On-board eMMC */
db8500_add_sdi4(&mop500_sdi4_data, U8500_SDI_V2_PERIPHID); db8500_add_sdi4(parent, &mop500_sdi4_data, U8500_SDI_V2_PERIPHID);
/* External Micro SD slot */ /* External Micro SD slot */
mop500_sdi0_data.gpio_cd = HREFV60_SDMMC_CD_GPIO; mop500_sdi0_data.gpio_cd = HREFV60_SDMMC_CD_GPIO;
sdi0_en = HREFV60_SDMMC_EN_GPIO; sdi0_en = HREFV60_SDMMC_EN_GPIO;
sdi0_vsel = HREFV60_SDMMC_1V8_3V_GPIO; sdi0_vsel = HREFV60_SDMMC_1V8_3V_GPIO;
sdi0_configure(); sdi0_configure(parent);
/* WLAN SDIO channel */ /* WLAN SDIO channel */
db8500_add_sdi1(&mop500_sdi1_data, U8500_SDI_V2_PERIPHID); db8500_add_sdi1(parent, &mop500_sdi1_data, U8500_SDI_V2_PERIPHID);
} }
...@@ -226,7 +226,12 @@ static struct tps6105x_platform_data mop500_tps61052_data = { ...@@ -226,7 +226,12 @@ static struct tps6105x_platform_data mop500_tps61052_data = {
static void mop500_tc35892_init(struct tc3589x *tc3589x, unsigned int base) static void mop500_tc35892_init(struct tc3589x *tc3589x, unsigned int base)
{ {
mop500_sdi_tc35892_init(); struct device *parent = NULL;
#if 0
/* FIXME: Is the sdi actually part of tc3589x? */
parent = tc3589x->dev;
#endif
mop500_sdi_tc35892_init(parent);
} }
static struct tc3589x_gpio_platform_data mop500_tc35892_gpio_data = { static struct tc3589x_gpio_platform_data mop500_tc35892_gpio_data = {
...@@ -353,12 +358,12 @@ U8500_I2C_CONTROLLER(1, 0xe, 1, 8, 100000, 200, I2C_FREQ_MODE_FAST); ...@@ -353,12 +358,12 @@ U8500_I2C_CONTROLLER(1, 0xe, 1, 8, 100000, 200, I2C_FREQ_MODE_FAST);
U8500_I2C_CONTROLLER(2, 0xe, 1, 8, 100000, 200, I2C_FREQ_MODE_FAST); U8500_I2C_CONTROLLER(2, 0xe, 1, 8, 100000, 200, I2C_FREQ_MODE_FAST);
U8500_I2C_CONTROLLER(3, 0xe, 1, 8, 100000, 200, I2C_FREQ_MODE_FAST); U8500_I2C_CONTROLLER(3, 0xe, 1, 8, 100000, 200, I2C_FREQ_MODE_FAST);
static void __init mop500_i2c_init(void) static void __init mop500_i2c_init(struct device *parent)
{ {
db8500_add_i2c0(&u8500_i2c0_data); db8500_add_i2c0(parent, &u8500_i2c0_data);
db8500_add_i2c1(&u8500_i2c1_data); db8500_add_i2c1(parent, &u8500_i2c1_data);
db8500_add_i2c2(&u8500_i2c2_data); db8500_add_i2c2(parent, &u8500_i2c2_data);
db8500_add_i2c3(&u8500_i2c3_data); db8500_add_i2c3(parent, &u8500_i2c3_data);
} }
static struct gpio_keys_button mop500_gpio_keys[] = { static struct gpio_keys_button mop500_gpio_keys[] = {
...@@ -451,9 +456,9 @@ static struct pl022_ssp_controller ssp0_platform_data = { ...@@ -451,9 +456,9 @@ static struct pl022_ssp_controller ssp0_platform_data = {
.num_chipselect = 5, .num_chipselect = 5,
}; };
static void __init mop500_spi_init(void) static void __init mop500_spi_init(struct device *parent)
{ {
db8500_add_ssp0(&ssp0_platform_data); db8500_add_ssp0(parent, &ssp0_platform_data);
} }
#ifdef CONFIG_STE_DMA40 #ifdef CONFIG_STE_DMA40
...@@ -587,11 +592,11 @@ static struct amba_pl011_data uart2_plat = { ...@@ -587,11 +592,11 @@ static struct amba_pl011_data uart2_plat = {
#endif #endif
}; };
static void __init mop500_uart_init(void) static void __init mop500_uart_init(struct device *parent)
{ {
db8500_add_uart0(&uart0_plat); db8500_add_uart0(parent, &uart0_plat);
db8500_add_uart1(&uart1_plat); db8500_add_uart1(parent, &uart1_plat);
db8500_add_uart2(&uart2_plat); db8500_add_uart2(parent, &uart2_plat);
} }
static struct platform_device *snowball_platform_devs[] __initdata = { static struct platform_device *snowball_platform_devs[] __initdata = {
...@@ -603,21 +608,26 @@ static struct platform_device *snowball_platform_devs[] __initdata = { ...@@ -603,21 +608,26 @@ static struct platform_device *snowball_platform_devs[] __initdata = {
static void __init mop500_init_machine(void) static void __init mop500_init_machine(void)
{ {
struct device *parent = NULL;
int i2c0_devs; int i2c0_devs;
int i;
mop500_gpio_keys[0].gpio = GPIO_PROX_SENSOR; mop500_gpio_keys[0].gpio = GPIO_PROX_SENSOR;
u8500_init_devices(); parent = u8500_init_devices();
mop500_pins_init(); mop500_pins_init();
for (i = 0; i < ARRAY_SIZE(mop500_platform_devs); i++)
mop500_platform_devs[i]->dev.parent = parent;
platform_add_devices(mop500_platform_devs, platform_add_devices(mop500_platform_devs,
ARRAY_SIZE(mop500_platform_devs)); ARRAY_SIZE(mop500_platform_devs));
mop500_i2c_init(); mop500_i2c_init(parent);
mop500_sdi_init(); mop500_sdi_init(parent);
mop500_spi_init(); mop500_spi_init(parent);
mop500_uart_init(); mop500_uart_init(parent);
i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices); i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
...@@ -631,19 +641,24 @@ static void __init mop500_init_machine(void) ...@@ -631,19 +641,24 @@ static void __init mop500_init_machine(void)
static void __init snowball_init_machine(void) static void __init snowball_init_machine(void)
{ {
struct device *parent = NULL;
int i2c0_devs; int i2c0_devs;
int i;
u8500_init_devices(); parent = u8500_init_devices();
snowball_pins_init(); snowball_pins_init();
for (i = 0; i < ARRAY_SIZE(snowball_platform_devs); i++)
snowball_platform_devs[i]->dev.parent = parent;
platform_add_devices(snowball_platform_devs, platform_add_devices(snowball_platform_devs,
ARRAY_SIZE(snowball_platform_devs)); ARRAY_SIZE(snowball_platform_devs));
mop500_i2c_init(); mop500_i2c_init(parent);
snowball_sdi_init(); snowball_sdi_init(parent);
mop500_spi_init(); mop500_spi_init(parent);
mop500_uart_init(); mop500_uart_init(parent);
i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices); i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs); i2c_register_board_info(0, mop500_i2c0_devices, i2c0_devs);
...@@ -656,7 +671,9 @@ static void __init snowball_init_machine(void) ...@@ -656,7 +671,9 @@ static void __init snowball_init_machine(void)
static void __init hrefv60_init_machine(void) static void __init hrefv60_init_machine(void)
{ {
struct device *parent = NULL;
int i2c0_devs; int i2c0_devs;
int i;
/* /*
* The HREFv60 board removed a GPIO expander and routed * The HREFv60 board removed a GPIO expander and routed
...@@ -665,17 +682,20 @@ static void __init hrefv60_init_machine(void) ...@@ -665,17 +682,20 @@ static void __init hrefv60_init_machine(void)
*/ */
mop500_gpio_keys[0].gpio = HREFV60_PROX_SENSE_GPIO; mop500_gpio_keys[0].gpio = HREFV60_PROX_SENSE_GPIO;
u8500_init_devices(); parent = u8500_init_devices();
hrefv60_pins_init(); hrefv60_pins_init();
for (i = 0; i < ARRAY_SIZE(mop500_platform_devs); i++)
mop500_platform_devs[i]->dev.parent = parent;
platform_add_devices(mop500_platform_devs, platform_add_devices(mop500_platform_devs,
ARRAY_SIZE(mop500_platform_devs)); ARRAY_SIZE(mop500_platform_devs));
mop500_i2c_init(); mop500_i2c_init(parent);
hrefv60_sdi_init(); hrefv60_sdi_init(parent);
mop500_spi_init(); mop500_spi_init(parent);
mop500_uart_init(); mop500_uart_init(parent);
i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices); i2c0_devs = ARRAY_SIZE(mop500_i2c0_devices);
......
...@@ -75,10 +75,10 @@ ...@@ -75,10 +75,10 @@
struct i2c_board_info; struct i2c_board_info;
extern void mop500_sdi_init(void); extern void mop500_sdi_init(struct device *parent);
extern void snowball_sdi_init(void); extern void snowball_sdi_init(struct device *parent);
extern void hrefv60_sdi_init(void); extern void hrefv60_sdi_init(struct device *parent);
extern void mop500_sdi_tc35892_init(void); extern void mop500_sdi_tc35892_init(struct device *parent);
void __init mop500_u8500uib_init(void); void __init mop500_u8500uib_init(void);
void __init mop500_stuib_init(void); void __init mop500_stuib_init(void);
void __init mop500_pins_init(void); void __init mop500_pins_init(void);
......
...@@ -66,9 +66,9 @@ static struct mmci_platform_data u5500_sdi0_data = { ...@@ -66,9 +66,9 @@ static struct mmci_platform_data u5500_sdi0_data = {
#endif #endif
}; };
void __init u5500_sdi_init(void) void __init u5500_sdi_init(struct device *parent)
{ {
nmk_config_pins(u5500_sdi_pins, ARRAY_SIZE(u5500_sdi_pins)); nmk_config_pins(u5500_sdi_pins, ARRAY_SIZE(u5500_sdi_pins));
db5500_add_sdi0(&u5500_sdi0_data); db5500_add_sdi0(parent, &u5500_sdi0_data);
} }
...@@ -97,9 +97,9 @@ static struct i2c_board_info __initdata u5500_i2c2_devices[] = { ...@@ -97,9 +97,9 @@ static struct i2c_board_info __initdata u5500_i2c2_devices[] = {
}, },
}; };
static void __init u5500_i2c_init(void) static void __init u5500_i2c_init(struct device *parent)
{ {
db5500_add_i2c2(&u5500_i2c2_data); db5500_add_i2c2(parent, &u5500_i2c2_data);
i2c_register_board_info(2, ARRAY_AND_SIZE(u5500_i2c2_devices)); i2c_register_board_info(2, ARRAY_AND_SIZE(u5500_i2c2_devices));
} }
...@@ -126,20 +126,27 @@ static struct platform_device *u5500_platform_devices[] __initdata = { ...@@ -126,20 +126,27 @@ static struct platform_device *u5500_platform_devices[] __initdata = {
&ab5500_device, &ab5500_device,
}; };
static void __init u5500_uart_init(void) static void __init u5500_uart_init(struct device *parent)
{ {
db5500_add_uart0(NULL); db5500_add_uart0(parent, NULL);
db5500_add_uart1(NULL); db5500_add_uart1(parent, NULL);
db5500_add_uart2(NULL); db5500_add_uart2(parent, NULL);
} }
static void __init u5500_init_machine(void) static void __init u5500_init_machine(void)
{ {
u5500_init_devices(); struct device *parent = NULL;
int i;
parent = u5500_init_devices();
nmk_config_pins(u5500_pins, ARRAY_SIZE(u5500_pins)); nmk_config_pins(u5500_pins, ARRAY_SIZE(u5500_pins));
u5500_i2c_init();
u5500_sdi_init(); u5500_i2c_init(parent);
u5500_uart_init(); u5500_sdi_init(parent);
u5500_uart_init(parent);
for (i = 0; i < ARRAY_SIZE(u5500_platform_devices); i++)
u5500_platform_devices[i]->dev.parent = parent;
platform_add_devices(u5500_platform_devices, platform_add_devices(u5500_platform_devices,
ARRAY_SIZE(u5500_platform_devices)); ARRAY_SIZE(u5500_platform_devices));
......
...@@ -147,13 +147,13 @@ static resource_size_t __initdata db5500_gpio_base[] = { ...@@ -147,13 +147,13 @@ static resource_size_t __initdata db5500_gpio_base[] = {
U5500_GPIOBANK7_BASE, U5500_GPIOBANK7_BASE,
}; };
static void __init db5500_add_gpios(void) static void __init db5500_add_gpios(struct device *parent)
{ {
struct nmk_gpio_platform_data pdata = { struct nmk_gpio_platform_data pdata = {
/* No custom data yet */ /* No custom data yet */
}; };
dbx500_add_gpios(ARRAY_AND_SIZE(db5500_gpio_base), dbx500_add_gpios(parent, ARRAY_AND_SIZE(db5500_gpio_base),
IRQ_DB5500_GPIO0, &pdata); IRQ_DB5500_GPIO0, &pdata);
} }
...@@ -212,14 +212,36 @@ static int usb_db5500_tx_dma_cfg[] = { ...@@ -212,14 +212,36 @@ static int usb_db5500_tx_dma_cfg[] = {
DB5500_DMA_DEV38_USB_OTG_OEP_8 DB5500_DMA_DEV38_USB_OTG_OEP_8
}; };
void __init u5500_init_devices(void) static const char *db5500_read_soc_id(void)
{ {
db5500_add_gpios(); return kasprintf(GFP_KERNEL, "u5500 currently unsupported\n");
}
static struct device * __init db5500_soc_device_init(void)
{
const char *soc_id = db5500_read_soc_id();
return ux500_soc_device_init(soc_id);
}
struct device * __init u5500_init_devices(void)
{
struct device *parent;
int i;
parent = db5500_soc_device_init();
db5500_add_gpios(parent);
db5500_pmu_init(); db5500_pmu_init();
db5500_dma_init(); db5500_dma_init(parent);
db5500_add_rtc(); db5500_add_rtc(parent);
db5500_add_usb(usb_db5500_rx_dma_cfg, usb_db5500_tx_dma_cfg); db5500_add_usb(parent, usb_db5500_rx_dma_cfg, usb_db5500_tx_dma_cfg);
for (i = 0; i < ARRAY_SIZE(db5500_platform_devs); i++)
db5500_platform_devs[i]->dev.parent = parent;
platform_add_devices(db5500_platform_devs, platform_add_devices(db5500_platform_devs,
ARRAY_SIZE(db5500_platform_devs)); ARRAY_SIZE(db5500_platform_devs));
return parent;
} }
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
...@@ -125,10 +125,11 @@ static struct platform_device dma40_device = { ...@@ -125,10 +125,11 @@ static struct platform_device dma40_device = {
.resource = dma40_resources .resource = dma40_resources
}; };
void __init db5500_dma_init(void) void __init db5500_dma_init(struct device *parent)
{ {
int ret; int ret;
dma40_device.dev.parent = parent;
ret = platform_device_register(&dma40_device); ret = platform_device_register(&dma40_device);
if (ret) if (ret)
dev_err(&dma40_device.dev, "unable to register device: %d\n", ret); dev_err(&dma40_device.dev, "unable to register device: %d\n", ret);
......
...@@ -161,4 +161,7 @@ ...@@ -161,4 +161,7 @@
#define U8500_MODEM_BASE 0xe000000 #define U8500_MODEM_BASE 0xe000000
#define U8500_APE_BASE 0x6000000 #define U8500_APE_BASE 0x6000000
/* SoC identification number information */
#define U8500_BB_UID_BASE (U8500_BACKUPRAM1_BASE + 0xFC0)
#endif #endif
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment