Commit 4cf44d52 authored by Kalle Valo's avatar Kalle Valo

Merge ath-next from git://git.kernel.org/pub/scm/linux/kernel/git/kvalo/ath.git

ath.git patches for 4.19. Major changes:

ath10k

* support channel 173

* fix spectral scan for QCA9984 and QCA9888 chipsets

ath6kl

* add support for Dell Wireless 1537
parents ce397d21 d5e5f685
config ATH10K config ATH10K
tristate "Atheros 802.11ac wireless cards support" tristate "Atheros 802.11ac wireless cards support"
depends on MAC80211 && HAS_DMA depends on MAC80211 && HAS_DMA
select ATH_COMMON select ATH_COMMON
select CRC32 select CRC32
select WANT_DEV_COREDUMP select WANT_DEV_COREDUMP
select ATH10K_CE select ATH10K_CE
---help--- ---help---
This module adds support for wireless adapters based on This module adds support for wireless adapters based on
Atheros IEEE 802.11ac family of chipsets. Atheros IEEE 802.11ac family of chipsets.
If you choose to build a module, it'll be called ath10k. If you choose to build a module, it'll be called ath10k.
config ATH10K_CE config ATH10K_CE
bool bool
...@@ -41,12 +41,12 @@ config ATH10K_USB ...@@ -41,12 +41,12 @@ config ATH10K_USB
work in progress and will not fully work. work in progress and will not fully work.
config ATH10K_SNOC config ATH10K_SNOC
tristate "Qualcomm ath10k SNOC support (EXPERIMENTAL)" tristate "Qualcomm ath10k SNOC support (EXPERIMENTAL)"
depends on ATH10K && ARCH_QCOM depends on ATH10K && ARCH_QCOM
---help--- ---help---
This module adds support for integrated WCN3990 chip connected This module adds support for integrated WCN3990 chip connected
to system NOC(SNOC). Currently work in progress and will not to system NOC(SNOC). Currently work in progress and will not
fully work. fully work.
config ATH10K_DEBUG config ATH10K_DEBUG
bool "Atheros ath10k debugging" bool "Atheros ath10k debugging"
......
...@@ -1512,7 +1512,7 @@ ath10k_ce_alloc_src_ring_64(struct ath10k *ar, unsigned int ce_id, ...@@ -1512,7 +1512,7 @@ ath10k_ce_alloc_src_ring_64(struct ath10k *ar, unsigned int ce_id,
ret = ath10k_ce_alloc_shadow_base(ar, src_ring, nentries); ret = ath10k_ce_alloc_shadow_base(ar, src_ring, nentries);
if (ret) { if (ret) {
dma_free_coherent(ar->dev, dma_free_coherent(ar->dev,
(nentries * sizeof(struct ce_desc) + (nentries * sizeof(struct ce_desc_64) +
CE_DESC_RING_ALIGN), CE_DESC_RING_ALIGN),
src_ring->base_addr_owner_space_unaligned, src_ring->base_addr_owner_space_unaligned,
base_addr); base_addr);
......
...@@ -383,4 +383,46 @@ static inline u32 ath10k_ce_interrupt_summary(struct ath10k *ar) ...@@ -383,4 +383,46 @@ static inline u32 ath10k_ce_interrupt_summary(struct ath10k *ar)
return CE_INTERRUPT_SUMMARY; return CE_INTERRUPT_SUMMARY;
} }
/* Host software's Copy Engine configuration. */
#define CE_ATTR_FLAGS 0
/*
* Configuration information for a Copy Engine pipe.
* Passed from Host to Target during startup (one per CE).
*
* NOTE: Structure is shared between Host software and Target firmware!
*/
struct ce_pipe_config {
__le32 pipenum;
__le32 pipedir;
__le32 nentries;
__le32 nbytes_max;
__le32 flags;
__le32 reserved;
};
/*
* Directions for interconnect pipe configuration.
* These definitions may be used during configuration and are shared
* between Host and Target.
*
* Pipe Directions are relative to the Host, so PIPEDIR_IN means
* "coming IN over air through Target to Host" as with a WiFi Rx operation.
* Conversely, PIPEDIR_OUT means "going OUT from Host through Target over air"
* as with a WiFi Tx operation. This is somewhat awkward for the "middle-man"
* Target since things that are "PIPEDIR_OUT" are coming IN to the Target
* over the interconnect.
*/
#define PIPEDIR_NONE 0
#define PIPEDIR_IN 1 /* Target-->Host, WiFi Rx direction */
#define PIPEDIR_OUT 2 /* Host->Target, WiFi Tx direction */
#define PIPEDIR_INOUT 3 /* bidirectional */
/* Establish a mapping between a service/direction and a pipe. */
struct service_to_pipe {
__le32 service_id;
__le32 pipedir;
__le32 pipenum;
};
#endif /* _CE_H_ */ #endif /* _CE_H_ */
...@@ -41,10 +41,8 @@ static bool uart_print; ...@@ -41,10 +41,8 @@ static bool uart_print;
static bool skip_otp; static bool skip_otp;
static bool rawmode; static bool rawmode;
/* Enable ATH10K_FW_CRASH_DUMP_REGISTERS and ATH10K_FW_CRASH_DUMP_CE_DATA unsigned long ath10k_coredump_mask = BIT(ATH10K_FW_CRASH_DUMP_REGISTERS) |
* by default. BIT(ATH10K_FW_CRASH_DUMP_CE_DATA);
*/
unsigned long ath10k_coredump_mask = 0x3;
/* FIXME: most of these should be readonly */ /* FIXME: most of these should be readonly */
module_param_named(debug_mask, ath10k_debug_mask, uint, 0644); module_param_named(debug_mask, ath10k_debug_mask, uint, 0644);
...@@ -82,6 +80,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -82,6 +80,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.hw_ops = &qca988x_ops, .hw_ops = &qca988x_ops,
.decap_align_bytes = 4, .decap_align_bytes = 4,
.spectral_bin_discard = 0, .spectral_bin_discard = 0,
.spectral_bin_offset = 0,
.vht160_mcs_rx_highest = 0, .vht160_mcs_rx_highest = 0,
.vht160_mcs_tx_highest = 0, .vht160_mcs_tx_highest = 0,
.n_cipher_suites = 8, .n_cipher_suites = 8,
...@@ -113,6 +112,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -113,6 +112,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.hw_ops = &qca988x_ops, .hw_ops = &qca988x_ops,
.decap_align_bytes = 4, .decap_align_bytes = 4,
.spectral_bin_discard = 0, .spectral_bin_discard = 0,
.spectral_bin_offset = 0,
.vht160_mcs_rx_highest = 0, .vht160_mcs_rx_highest = 0,
.vht160_mcs_tx_highest = 0, .vht160_mcs_tx_highest = 0,
.n_cipher_suites = 8, .n_cipher_suites = 8,
...@@ -145,6 +145,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -145,6 +145,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.hw_ops = &qca988x_ops, .hw_ops = &qca988x_ops,
.decap_align_bytes = 4, .decap_align_bytes = 4,
.spectral_bin_discard = 0, .spectral_bin_discard = 0,
.spectral_bin_offset = 0,
.vht160_mcs_rx_highest = 0, .vht160_mcs_rx_highest = 0,
.vht160_mcs_tx_highest = 0, .vht160_mcs_tx_highest = 0,
.n_cipher_suites = 8, .n_cipher_suites = 8,
...@@ -176,6 +177,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -176,6 +177,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.hw_ops = &qca988x_ops, .hw_ops = &qca988x_ops,
.decap_align_bytes = 4, .decap_align_bytes = 4,
.spectral_bin_discard = 0, .spectral_bin_discard = 0,
.spectral_bin_offset = 0,
.vht160_mcs_rx_highest = 0, .vht160_mcs_rx_highest = 0,
.vht160_mcs_tx_highest = 0, .vht160_mcs_tx_highest = 0,
.n_cipher_suites = 8, .n_cipher_suites = 8,
...@@ -207,6 +209,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -207,6 +209,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.hw_ops = &qca988x_ops, .hw_ops = &qca988x_ops,
.decap_align_bytes = 4, .decap_align_bytes = 4,
.spectral_bin_discard = 0, .spectral_bin_discard = 0,
.spectral_bin_offset = 0,
.vht160_mcs_rx_highest = 0, .vht160_mcs_rx_highest = 0,
.vht160_mcs_tx_highest = 0, .vht160_mcs_tx_highest = 0,
.n_cipher_suites = 8, .n_cipher_suites = 8,
...@@ -238,6 +241,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -238,6 +241,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.hw_ops = &qca988x_ops, .hw_ops = &qca988x_ops,
.decap_align_bytes = 4, .decap_align_bytes = 4,
.spectral_bin_discard = 0, .spectral_bin_discard = 0,
.spectral_bin_offset = 0,
.vht160_mcs_rx_highest = 0, .vht160_mcs_rx_highest = 0,
.vht160_mcs_tx_highest = 0, .vht160_mcs_tx_highest = 0,
.n_cipher_suites = 8, .n_cipher_suites = 8,
...@@ -272,6 +276,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -272,6 +276,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.target_cpu_freq = 176000000, .target_cpu_freq = 176000000,
.decap_align_bytes = 4, .decap_align_bytes = 4,
.spectral_bin_discard = 0, .spectral_bin_discard = 0,
.spectral_bin_offset = 0,
.vht160_mcs_rx_highest = 0, .vht160_mcs_rx_highest = 0,
.vht160_mcs_tx_highest = 0, .vht160_mcs_tx_highest = 0,
.n_cipher_suites = 8, .n_cipher_suites = 8,
...@@ -309,6 +314,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -309,6 +314,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.hw_ops = &qca99x0_ops, .hw_ops = &qca99x0_ops,
.decap_align_bytes = 1, .decap_align_bytes = 1,
.spectral_bin_discard = 4, .spectral_bin_discard = 4,
.spectral_bin_offset = 0,
.vht160_mcs_rx_highest = 0, .vht160_mcs_rx_highest = 0,
.vht160_mcs_tx_highest = 0, .vht160_mcs_tx_highest = 0,
.n_cipher_suites = 11, .n_cipher_suites = 11,
...@@ -347,6 +353,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -347,6 +353,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.hw_ops = &qca99x0_ops, .hw_ops = &qca99x0_ops,
.decap_align_bytes = 1, .decap_align_bytes = 1,
.spectral_bin_discard = 12, .spectral_bin_discard = 12,
.spectral_bin_offset = 8,
/* Can do only 2x2 VHT160 or 80+80. 1560Mbps is 4x4 80Mhz /* Can do only 2x2 VHT160 or 80+80. 1560Mbps is 4x4 80Mhz
* or 2x2 160Mhz, long-guard-interval. * or 2x2 160Mhz, long-guard-interval.
...@@ -388,6 +395,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -388,6 +395,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.hw_ops = &qca99x0_ops, .hw_ops = &qca99x0_ops,
.decap_align_bytes = 1, .decap_align_bytes = 1,
.spectral_bin_discard = 12, .spectral_bin_discard = 12,
.spectral_bin_offset = 8,
/* Can do only 1x1 VHT160 or 80+80. 780Mbps is 2x2 80Mhz or /* Can do only 1x1 VHT160 or 80+80. 780Mbps is 2x2 80Mhz or
* 1x1 160Mhz, long-guard-interval. * 1x1 160Mhz, long-guard-interval.
...@@ -423,6 +431,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -423,6 +431,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.hw_ops = &qca988x_ops, .hw_ops = &qca988x_ops,
.decap_align_bytes = 4, .decap_align_bytes = 4,
.spectral_bin_discard = 0, .spectral_bin_discard = 0,
.spectral_bin_offset = 0,
.vht160_mcs_rx_highest = 0, .vht160_mcs_rx_highest = 0,
.vht160_mcs_tx_highest = 0, .vht160_mcs_tx_highest = 0,
.n_cipher_suites = 8, .n_cipher_suites = 8,
...@@ -456,6 +465,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -456,6 +465,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.target_cpu_freq = 176000000, .target_cpu_freq = 176000000,
.decap_align_bytes = 4, .decap_align_bytes = 4,
.spectral_bin_discard = 0, .spectral_bin_discard = 0,
.spectral_bin_offset = 0,
.vht160_mcs_rx_highest = 0, .vht160_mcs_rx_highest = 0,
.vht160_mcs_tx_highest = 0, .vht160_mcs_tx_highest = 0,
.n_cipher_suites = 8, .n_cipher_suites = 8,
...@@ -494,6 +504,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = { ...@@ -494,6 +504,7 @@ static const struct ath10k_hw_params ath10k_hw_params_list[] = {
.hw_ops = &qca99x0_ops, .hw_ops = &qca99x0_ops,
.decap_align_bytes = 1, .decap_align_bytes = 1,
.spectral_bin_discard = 4, .spectral_bin_discard = 4,
.spectral_bin_offset = 0,
.vht160_mcs_rx_highest = 0, .vht160_mcs_rx_highest = 0,
.vht160_mcs_tx_highest = 0, .vht160_mcs_tx_highest = 0,
.n_cipher_suites = 11, .n_cipher_suites = 11,
......
...@@ -48,7 +48,8 @@ ...@@ -48,7 +48,8 @@
#define WMI_READY_TIMEOUT (5 * HZ) #define WMI_READY_TIMEOUT (5 * HZ)
#define ATH10K_FLUSH_TIMEOUT_HZ (5 * HZ) #define ATH10K_FLUSH_TIMEOUT_HZ (5 * HZ)
#define ATH10K_CONNECTION_LOSS_HZ (3 * HZ) #define ATH10K_CONNECTION_LOSS_HZ (3 * HZ)
#define ATH10K_NUM_CHANS 40 #define ATH10K_NUM_CHANS 41
#define ATH10K_MAX_5G_CHAN 173
/* Antenna noise floor */ /* Antenna noise floor */
#define ATH10K_DEFAULT_NOISE_FLOOR -95 #define ATH10K_DEFAULT_NOISE_FLOOR -95
......
...@@ -1727,7 +1727,9 @@ int ath10k_debug_start(struct ath10k *ar) ...@@ -1727,7 +1727,9 @@ int ath10k_debug_start(struct ath10k *ar)
ath10k_warn(ar, "failed to disable pktlog: %d\n", ret); ath10k_warn(ar, "failed to disable pktlog: %d\n", ret);
} }
if (ar->debug.nf_cal_period) { if (ar->debug.nf_cal_period &&
!test_bit(ATH10K_FW_FEATURE_NON_BMI,
ar->normal_mode_fw.fw_file.fw_features)) {
ret = ath10k_wmi_pdev_set_param(ar, ret = ath10k_wmi_pdev_set_param(ar,
ar->wmi.pdev_param->cal_period, ar->wmi.pdev_param->cal_period,
ar->debug.nf_cal_period); ar->debug.nf_cal_period);
...@@ -1744,7 +1746,9 @@ void ath10k_debug_stop(struct ath10k *ar) ...@@ -1744,7 +1746,9 @@ void ath10k_debug_stop(struct ath10k *ar)
{ {
lockdep_assert_held(&ar->conf_mutex); lockdep_assert_held(&ar->conf_mutex);
ath10k_debug_cal_data_fetch(ar); if (!test_bit(ATH10K_FW_FEATURE_NON_BMI,
ar->normal_mode_fw.fw_file.fw_features))
ath10k_debug_cal_data_fetch(ar);
/* Must not use _sync to avoid deadlock, we do that in /* Must not use _sync to avoid deadlock, we do that in
* ath10k_debug_destroy(). The check for htt_stats_mask is to avoid * ath10k_debug_destroy(). The check for htt_stats_mask is to avoid
...@@ -2367,15 +2371,18 @@ int ath10k_debug_register(struct ath10k *ar) ...@@ -2367,15 +2371,18 @@ int ath10k_debug_register(struct ath10k *ar)
debugfs_create_file("fw_dbglog", 0600, ar->debug.debugfs_phy, ar, debugfs_create_file("fw_dbglog", 0600, ar->debug.debugfs_phy, ar,
&fops_fw_dbglog); &fops_fw_dbglog);
debugfs_create_file("cal_data", 0400, ar->debug.debugfs_phy, ar, if (!test_bit(ATH10K_FW_FEATURE_NON_BMI,
&fops_cal_data); ar->normal_mode_fw.fw_file.fw_features)) {
debugfs_create_file("cal_data", 0400, ar->debug.debugfs_phy, ar,
&fops_cal_data);
debugfs_create_file("nf_cal_period", 0600, ar->debug.debugfs_phy, ar,
&fops_nf_cal_period);
}
debugfs_create_file("ani_enable", 0600, ar->debug.debugfs_phy, ar, debugfs_create_file("ani_enable", 0600, ar->debug.debugfs_phy, ar,
&fops_ani_enable); &fops_ani_enable);
debugfs_create_file("nf_cal_period", 0600, ar->debug.debugfs_phy, ar,
&fops_nf_cal_period);
if (IS_ENABLED(CONFIG_ATH10K_DFS_CERTIFIED)) { if (IS_ENABLED(CONFIG_ATH10K_DFS_CERTIFIED)) {
debugfs_create_file("dfs_simulate_radar", 0200, ar->debug.debugfs_phy, debugfs_create_file("dfs_simulate_radar", 0200, ar->debug.debugfs_phy,
ar, &fops_simulate_radar); ar, &fops_simulate_radar);
......
...@@ -1202,7 +1202,7 @@ static int ath10k_htt_tx_32(struct ath10k_htt *htt, ...@@ -1202,7 +1202,7 @@ static int ath10k_htt_tx_32(struct ath10k_htt *htt,
case ATH10K_HW_TXRX_RAW: case ATH10K_HW_TXRX_RAW:
case ATH10K_HW_TXRX_NATIVE_WIFI: case ATH10K_HW_TXRX_NATIVE_WIFI:
flags0 |= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT; flags0 |= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT;
/* pass through */ /* fall through */
case ATH10K_HW_TXRX_ETHERNET: case ATH10K_HW_TXRX_ETHERNET:
if (ar->hw_params.continuous_frag_desc) { if (ar->hw_params.continuous_frag_desc) {
ext_desc_t = htt->frag_desc.vaddr_desc_32; ext_desc_t = htt->frag_desc.vaddr_desc_32;
...@@ -1404,7 +1404,7 @@ static int ath10k_htt_tx_64(struct ath10k_htt *htt, ...@@ -1404,7 +1404,7 @@ static int ath10k_htt_tx_64(struct ath10k_htt *htt,
case ATH10K_HW_TXRX_RAW: case ATH10K_HW_TXRX_RAW:
case ATH10K_HW_TXRX_NATIVE_WIFI: case ATH10K_HW_TXRX_NATIVE_WIFI:
flags0 |= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT; flags0 |= HTT_DATA_TX_DESC_FLAGS0_MAC_HDR_PRESENT;
/* pass through */ /* fall through */
case ATH10K_HW_TXRX_ETHERNET: case ATH10K_HW_TXRX_ETHERNET:
if (ar->hw_params.continuous_frag_desc) { if (ar->hw_params.continuous_frag_desc) {
ext_desc_t = htt->frag_desc.vaddr_desc_64; ext_desc_t = htt->frag_desc.vaddr_desc_64;
......
...@@ -586,6 +586,9 @@ struct ath10k_hw_params { ...@@ -586,6 +586,9 @@ struct ath10k_hw_params {
/* target supporting retention restore on ddr */ /* target supporting retention restore on ddr */
bool rri_on_ddr; bool rri_on_ddr;
/* Number of bytes to be the offset for each FFT sample */
int spectral_bin_offset;
}; };
struct htt_rx_desc; struct htt_rx_desc;
......
...@@ -7858,6 +7858,9 @@ static const struct ieee80211_channel ath10k_5ghz_channels[] = { ...@@ -7858,6 +7858,9 @@ static const struct ieee80211_channel ath10k_5ghz_channels[] = {
CHAN5G(161, 5805, 0), CHAN5G(161, 5805, 0),
CHAN5G(165, 5825, 0), CHAN5G(165, 5825, 0),
CHAN5G(169, 5845, 0), CHAN5G(169, 5845, 0),
CHAN5G(173, 5865, 0),
/* If you add more, you may need to change ATH10K_MAX_5G_CHAN */
/* And you will definitely need to change ATH10K_NUM_CHANS in core.h */
}; };
struct ath10k *ath10k_mac_create(size_t priv_size) struct ath10k *ath10k_mac_create(size_t priv_size)
......
...@@ -86,48 +86,6 @@ struct pcie_state { ...@@ -86,48 +86,6 @@ struct pcie_state {
/* PCIE_CONFIG_FLAG definitions */ /* PCIE_CONFIG_FLAG definitions */
#define PCIE_CONFIG_FLAG_ENABLE_L1 0x0000001 #define PCIE_CONFIG_FLAG_ENABLE_L1 0x0000001
/* Host software's Copy Engine configuration. */
#define CE_ATTR_FLAGS 0
/*
* Configuration information for a Copy Engine pipe.
* Passed from Host to Target during startup (one per CE).
*
* NOTE: Structure is shared between Host software and Target firmware!
*/
struct ce_pipe_config {
__le32 pipenum;
__le32 pipedir;
__le32 nentries;
__le32 nbytes_max;
__le32 flags;
__le32 reserved;
};
/*
* Directions for interconnect pipe configuration.
* These definitions may be used during configuration and are shared
* between Host and Target.
*
* Pipe Directions are relative to the Host, so PIPEDIR_IN means
* "coming IN over air through Target to Host" as with a WiFi Rx operation.
* Conversely, PIPEDIR_OUT means "going OUT from Host through Target over air"
* as with a WiFi Tx operation. This is somewhat awkward for the "middle-man"
* Target since things that are "PIPEDIR_OUT" are coming IN to the Target
* over the interconnect.
*/
#define PIPEDIR_NONE 0
#define PIPEDIR_IN 1 /* Target-->Host, WiFi Rx direction */
#define PIPEDIR_OUT 2 /* Host->Target, WiFi Tx direction */
#define PIPEDIR_INOUT 3 /* bidirectional */
/* Establish a mapping between a service/direction and a pipe. */
struct service_to_pipe {
__le32 service_id;
__le32 pipedir;
__le32 pipenum;
};
/* Per-pipe state. */ /* Per-pipe state. */
struct ath10k_pci_pipe { struct ath10k_pci_pipe {
/* Handle of underlying Copy Engine */ /* Handle of underlying Copy Engine */
......
...@@ -14,19 +14,20 @@ ...@@ -14,19 +14,20 @@
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/ */
#include <linux/module.h> #include <linux/clk.h>
#include <linux/kernel.h> #include <linux/kernel.h>
#include "debug.h" #include <linux/module.h>
#include "hif.h"
#include "htc.h"
#include "ce.h"
#include "snoc.h"
#include <linux/of.h> #include <linux/of.h>
#include <linux/of_device.h> #include <linux/of_device.h>
#include <linux/platform_device.h> #include <linux/platform_device.h>
#include <linux/regulator/consumer.h> #include <linux/regulator/consumer.h>
#include <linux/clk.h>
#define WCN3990_CE_ATTR_FLAGS 0 #include "ce.h"
#include "debug.h"
#include "hif.h"
#include "htc.h"
#include "snoc.h"
#define ATH10K_SNOC_RX_POST_RETRY_MS 50 #define ATH10K_SNOC_RX_POST_RETRY_MS 50
#define CE_POLL_PIPE 4 #define CE_POLL_PIPE 4
...@@ -449,7 +450,7 @@ static void ath10k_snoc_htt_rx_cb(struct ath10k_ce_pipe *ce_state) ...@@ -449,7 +450,7 @@ static void ath10k_snoc_htt_rx_cb(struct ath10k_ce_pipe *ce_state)
static void ath10k_snoc_rx_replenish_retry(struct timer_list *t) static void ath10k_snoc_rx_replenish_retry(struct timer_list *t)
{ {
struct ath10k_pci *ar_snoc = from_timer(ar_snoc, t, rx_post_retry); struct ath10k_snoc *ar_snoc = from_timer(ar_snoc, t, rx_post_retry);
struct ath10k *ar = ar_snoc->ar; struct ath10k *ar = ar_snoc->ar;
ath10k_snoc_rx_post(ar); ath10k_snoc_rx_post(ar);
...@@ -820,7 +821,7 @@ static const struct ath10k_bus_ops ath10k_snoc_bus_ops = { ...@@ -820,7 +821,7 @@ static const struct ath10k_bus_ops ath10k_snoc_bus_ops = {
.write32 = ath10k_snoc_write32, .write32 = ath10k_snoc_write32,
}; };
int ath10k_snoc_get_ce_id_from_irq(struct ath10k *ar, int irq) static int ath10k_snoc_get_ce_id_from_irq(struct ath10k *ar, int irq)
{ {
struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar); struct ath10k_snoc *ar_snoc = ath10k_snoc_priv(ar);
int i; int i;
...@@ -868,7 +869,7 @@ static int ath10k_snoc_napi_poll(struct napi_struct *ctx, int budget) ...@@ -868,7 +869,7 @@ static int ath10k_snoc_napi_poll(struct napi_struct *ctx, int budget)
return done; return done;
} }
void ath10k_snoc_init_napi(struct ath10k *ar) static void ath10k_snoc_init_napi(struct ath10k *ar)
{ {
netif_napi_add(&ar->napi_dev, &ar->napi, ath10k_snoc_napi_poll, netif_napi_add(&ar->napi_dev, &ar->napi, ath10k_snoc_napi_poll,
ATH10K_NAPI_BUDGET); ATH10K_NAPI_BUDGET);
...@@ -1303,13 +1304,13 @@ static int ath10k_snoc_probe(struct platform_device *pdev) ...@@ -1303,13 +1304,13 @@ static int ath10k_snoc_probe(struct platform_device *pdev)
ar_snoc->ce.bus_ops = &ath10k_snoc_bus_ops; ar_snoc->ce.bus_ops = &ath10k_snoc_bus_ops;
ar->ce_priv = &ar_snoc->ce; ar->ce_priv = &ar_snoc->ce;
ath10k_snoc_resource_init(ar); ret = ath10k_snoc_resource_init(ar);
if (ret) { if (ret) {
ath10k_warn(ar, "failed to initialize resource: %d\n", ret); ath10k_warn(ar, "failed to initialize resource: %d\n", ret);
goto err_core_destroy; goto err_core_destroy;
} }
ath10k_snoc_setup_resource(ar); ret = ath10k_snoc_setup_resource(ar);
if (ret) { if (ret) {
ath10k_warn(ar, "failed to setup resource: %d\n", ret); ath10k_warn(ar, "failed to setup resource: %d\n", ret);
goto err_core_destroy; goto err_core_destroy;
...@@ -1388,25 +1389,7 @@ static struct platform_driver ath10k_snoc_driver = { ...@@ -1388,25 +1389,7 @@ static struct platform_driver ath10k_snoc_driver = {
.of_match_table = ath10k_snoc_dt_match, .of_match_table = ath10k_snoc_dt_match,
}, },
}; };
module_platform_driver(ath10k_snoc_driver);
static int __init ath10k_snoc_init(void)
{
int ret;
ret = platform_driver_register(&ath10k_snoc_driver);
if (ret)
pr_err("failed to register ath10k snoc driver: %d\n",
ret);
return ret;
}
module_init(ath10k_snoc_init);
static void __exit ath10k_snoc_exit(void)
{
platform_driver_unregister(&ath10k_snoc_driver);
}
module_exit(ath10k_snoc_exit);
MODULE_AUTHOR("Qualcomm"); MODULE_AUTHOR("Qualcomm");
MODULE_LICENSE("Dual BSD/GPL"); MODULE_LICENSE("Dual BSD/GPL");
......
...@@ -19,7 +19,6 @@ ...@@ -19,7 +19,6 @@
#include "hw.h" #include "hw.h"
#include "ce.h" #include "ce.h"
#include "pci.h"
struct ath10k_snoc_drv_priv { struct ath10k_snoc_drv_priv {
enum ath10k_hw_rev hw_rev; enum ath10k_hw_rev hw_rev;
......
...@@ -145,7 +145,7 @@ int ath10k_spectral_process_fft(struct ath10k *ar, ...@@ -145,7 +145,7 @@ int ath10k_spectral_process_fft(struct ath10k *ar,
fft_sample->noise = __cpu_to_be16(phyerr->nf_chains[chain_idx]); fft_sample->noise = __cpu_to_be16(phyerr->nf_chains[chain_idx]);
bins = (u8 *)fftr; bins = (u8 *)fftr;
bins += sizeof(*fftr); bins += sizeof(*fftr) + ar->hw_params.spectral_bin_offset;
fft_sample->tsf = __cpu_to_be64(tsf); fft_sample->tsf = __cpu_to_be64(tsf);
......
...@@ -2366,7 +2366,7 @@ int ath10k_wmi_event_mgmt_rx(struct ath10k *ar, struct sk_buff *skb) ...@@ -2366,7 +2366,7 @@ int ath10k_wmi_event_mgmt_rx(struct ath10k *ar, struct sk_buff *skb)
*/ */
if (channel >= 1 && channel <= 14) { if (channel >= 1 && channel <= 14) {
status->band = NL80211_BAND_2GHZ; status->band = NL80211_BAND_2GHZ;
} else if (channel >= 36 && channel <= 169) { } else if (channel >= 36 && channel <= ATH10K_MAX_5G_CHAN) {
status->band = NL80211_BAND_5GHZ; status->band = NL80211_BAND_5GHZ;
} else { } else {
/* Shouldn't happen unless list of advertised channels to /* Shouldn't happen unless list of advertised channels to
...@@ -4602,10 +4602,6 @@ void ath10k_wmi_event_pdev_tpc_config(struct ath10k *ar, struct sk_buff *skb) ...@@ -4602,10 +4602,6 @@ void ath10k_wmi_event_pdev_tpc_config(struct ath10k *ar, struct sk_buff *skb)
ev = (struct wmi_pdev_tpc_config_event *)skb->data; ev = (struct wmi_pdev_tpc_config_event *)skb->data;
tpc_stats = kzalloc(sizeof(*tpc_stats), GFP_ATOMIC);
if (!tpc_stats)
return;
num_tx_chain = __le32_to_cpu(ev->num_tx_chain); num_tx_chain = __le32_to_cpu(ev->num_tx_chain);
if (num_tx_chain > WMI_TPC_TX_N_CHAIN) { if (num_tx_chain > WMI_TPC_TX_N_CHAIN) {
...@@ -4614,6 +4610,10 @@ void ath10k_wmi_event_pdev_tpc_config(struct ath10k *ar, struct sk_buff *skb) ...@@ -4614,6 +4610,10 @@ void ath10k_wmi_event_pdev_tpc_config(struct ath10k *ar, struct sk_buff *skb)
return; return;
} }
tpc_stats = kzalloc(sizeof(*tpc_stats), GFP_ATOMIC);
if (!tpc_stats)
return;
ath10k_wmi_tpc_config_get_rate_code(rate_code, pream_table, ath10k_wmi_tpc_config_get_rate_code(rate_code, pream_table,
num_tx_chain); num_tx_chain);
...@@ -5018,13 +5018,11 @@ static int ath10k_wmi_alloc_chunk(struct ath10k *ar, u32 req_id, ...@@ -5018,13 +5018,11 @@ static int ath10k_wmi_alloc_chunk(struct ath10k *ar, u32 req_id,
void *vaddr; void *vaddr;
pool_size = num_units * round_up(unit_len, 4); pool_size = num_units * round_up(unit_len, 4);
vaddr = dma_alloc_coherent(ar->dev, pool_size, &paddr, GFP_KERNEL); vaddr = dma_zalloc_coherent(ar->dev, pool_size, &paddr, GFP_KERNEL);
if (!vaddr) if (!vaddr)
return -ENOMEM; return -ENOMEM;
memset(vaddr, 0, pool_size);
ar->wmi.mem_chunks[idx].vaddr = vaddr; ar->wmi.mem_chunks[idx].vaddr = vaddr;
ar->wmi.mem_chunks[idx].paddr = paddr; ar->wmi.mem_chunks[idx].paddr = paddr;
ar->wmi.mem_chunks[idx].len = pool_size; ar->wmi.mem_chunks[idx].len = pool_size;
......
...@@ -670,6 +670,7 @@ ath5k_hw_init_beacon_timers(struct ath5k_hw *ah, u32 next_beacon, u32 interval) ...@@ -670,6 +670,7 @@ ath5k_hw_init_beacon_timers(struct ath5k_hw *ah, u32 next_beacon, u32 interval)
break; break;
case NL80211_IFTYPE_ADHOC: case NL80211_IFTYPE_ADHOC:
AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG, AR5K_TXCFG_ADHOC_BCN_ATIM); AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG, AR5K_TXCFG_ADHOC_BCN_ATIM);
/* fall through */
default: default:
/* On non-STA modes timer1 is used as next DMA /* On non-STA modes timer1 is used as next DMA
* beacon alert (DBA) timer and timer2 as next * beacon alert (DBA) timer and timer2 as next
......
...@@ -3899,16 +3899,19 @@ int ath6kl_cfg80211_init(struct ath6kl *ar) ...@@ -3899,16 +3899,19 @@ int ath6kl_cfg80211_init(struct ath6kl *ar)
switch (ar->hw.cap) { switch (ar->hw.cap) {
case WMI_11AN_CAP: case WMI_11AN_CAP:
ht = true; ht = true;
/* fall through */
case WMI_11A_CAP: case WMI_11A_CAP:
band_5gig = true; band_5gig = true;
break; break;
case WMI_11GN_CAP: case WMI_11GN_CAP:
ht = true; ht = true;
/* fall through */
case WMI_11G_CAP: case WMI_11G_CAP:
band_2gig = true; band_2gig = true;
break; break;
case WMI_11AGN_CAP: case WMI_11AGN_CAP:
ht = true; ht = true;
/* fall through */
case WMI_11AG_CAP: case WMI_11AG_CAP:
band_2gig = true; band_2gig = true;
band_5gig = true; band_5gig = true;
......
...@@ -1415,6 +1415,7 @@ static const struct sdio_device_id ath6kl_sdio_devices[] = { ...@@ -1415,6 +1415,7 @@ static const struct sdio_device_id ath6kl_sdio_devices[] = {
{SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6004_BASE | 0x1))}, {SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6004_BASE | 0x1))},
{SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6004_BASE | 0x2))}, {SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6004_BASE | 0x2))},
{SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6004_BASE | 0x18))}, {SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6004_BASE | 0x18))},
{SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6004_BASE | 0x19))},
{}, {},
}; };
......
...@@ -583,12 +583,14 @@ static void ar5008_hw_init_chain_masks(struct ath_hw *ah) ...@@ -583,12 +583,14 @@ static void ar5008_hw_init_chain_masks(struct ath_hw *ah)
case 0x5: case 0x5:
REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP, REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
AR_PHY_SWAP_ALT_CHAIN); AR_PHY_SWAP_ALT_CHAIN);
/* fall through */
case 0x3: case 0x3:
if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) { if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) {
REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7); REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7); REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
break; break;
} }
/* else: fall through */
case 0x1: case 0x1:
case 0x2: case 0x2:
case 0x7: case 0x7:
......
...@@ -119,6 +119,7 @@ static int ar9002_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan) ...@@ -119,6 +119,7 @@ static int ar9002_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
aModeRefSel = 2; aModeRefSel = 2;
if (aModeRefSel) if (aModeRefSel)
break; break;
/* else: fall through */
case 1: case 1:
default: default:
aModeRefSel = 0; aModeRefSel = 0;
......
...@@ -538,7 +538,7 @@ static int read_file_interrupt(struct seq_file *file, void *data) ...@@ -538,7 +538,7 @@ static int read_file_interrupt(struct seq_file *file, void *data)
if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) { if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
PR_IS("RXLP", rxlp); PR_IS("RXLP", rxlp);
PR_IS("RXHP", rxhp); PR_IS("RXHP", rxhp);
PR_IS("WATHDOG", bb_watchdog); PR_IS("WATCHDOG", bb_watchdog);
} else { } else {
PR_IS("RX", rxok); PR_IS("RX", rxok);
} }
......
...@@ -1928,6 +1928,7 @@ static int ath9k_ampdu_action(struct ieee80211_hw *hw, ...@@ -1928,6 +1928,7 @@ static int ath9k_ampdu_action(struct ieee80211_hw *hw,
case IEEE80211_AMPDU_TX_STOP_FLUSH: case IEEE80211_AMPDU_TX_STOP_FLUSH:
case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT: case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
flush = true; flush = true;
/* fall through */
case IEEE80211_AMPDU_TX_STOP_CONT: case IEEE80211_AMPDU_TX_STOP_CONT:
ath9k_ps_wakeup(sc); ath9k_ps_wakeup(sc);
ath_tx_aggr_stop(sc, sta, tid); ath_tx_aggr_stop(sc, sta, tid);
......
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