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Commit 4d0f04d4 authored by Kai Germaschewski's avatar Kai Germaschewski
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ISDN/HiSax: Helper functions for D-Channel {read,write}_reg() etc 

As a preparation for moving the B-Channel access functions into
an ops struct, introduce inline helper functions for using them.
parent 4559dc4a
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Showing with 241 additions and 170 deletions
drivers/isdn/hisax/arcofi.c
View file @ 4d0f04d4
......@@ -43,11 +43,11 @@ send_arcofi(struct IsdnCardState *cs) {
}
cs->dc.isac.mocr &= 0x0f;
cs->dc.isac.mocr |= 0xa0;
cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
val = cs->readisac(cs, ISAC_MOSR);
cs->writeisac(cs, ISAC_MOX1, cs->dc.isac.mon_tx[cs->dc.isac.mon_txp++]);
isac_write_reg(cs, ISAC_MOCR, cs->dc.isac.mocr);
val = isac_read_reg(cs, ISAC_MOSR);
isac_write_reg(cs, ISAC_MOX1, cs->dc.isac.mon_tx[cs->dc.isac.mon_txp++]);
cs->dc.isac.mocr |= 0x10;
cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
isac_write_reg(cs, ISAC_MOCR, cs->dc.isac.mocr);
}
int
......
drivers/isdn/hisax/icc.c
View file @ 4d0f04d4
......@@ -25,6 +25,30 @@
#define ARCOFI_USE 0
static spinlock_t icc_lock = SPIN_LOCK_UNLOCKED;
static inline u8
icc_read_reg(struct IsdnCardState *cs, u8 addr)
{
return cs->readisac(cs, addr);
}
static inline void
icc_write_reg(struct IsdnCardState *cs, u8 addr, u8 val)
{
cs->writeisac(cs, addr, val);
}
static inline void
icc_read_fifo(struct IsdnCardState *cs, u8 *p, int len)
{
return cs->readisacfifo(cs, p, len);
}
static inline void
icc_write_fifo(struct IsdnCardState *cs, u8 *p, int len)
{
return cs->writeisacfifo(cs, p, len);
}
static char *ICCVer[] __initdata =
{"2070 A1/A3", "2070 B1", "2070 B2/B3", "2070 V2.4"};
......@@ -33,7 +57,7 @@ ICCVersion(struct IsdnCardState *cs, char *s)
{
int val;
val = cs->readisac(cs, ICC_RBCH);
val = icc_read_reg(cs, ICC_RBCH);
printk(KERN_INFO "%s ICC version (%x): %s\n", s, val, ICCVer[(val >> 5) & 3]);
}
......@@ -42,7 +66,7 @@ ph_command(struct IsdnCardState *cs, unsigned int command)
{
if (cs->debug & L1_DEB_ISAC)
debugl1(cs, "ph_command %x", command);
cs->writeisac(cs, ICC_CIX0, (command << 2) | 3);
icc_write_reg(cs, ICC_CIX0, (command << 2) | 3);
}
......@@ -123,15 +147,15 @@ icc_empty_fifo(struct IsdnCardState *cs, int count)
if (cs->debug & L1_DEB_WARN)
debugl1(cs, "icc_empty_fifo overrun %d",
cs->rcvidx + count);
cs->writeisac(cs, ICC_CMDR, 0x80);
icc_write_reg(cs, ICC_CMDR, 0x80);
cs->rcvidx = 0;
return;
}
ptr = cs->rcvbuf + cs->rcvidx;
cs->rcvidx += count;
spin_lock_irqsave(&icc_lock, flags);
cs->readisacfifo(cs, ptr, count);
cs->writeisac(cs, ICC_CMDR, 0x80);
icc_read_fifo(cs, ptr, count);
icc_write_reg(cs, ICC_CMDR, 0x80);
spin_unlock_irqrestore(&icc_lock, flags);
if (cs->debug & L1_DEB_ISAC_FIFO) {
char *t = cs->dlog;
......@@ -154,8 +178,8 @@ icc_fill_fifo(struct IsdnCardState *cs)
return;
spin_lock_irqsave(&icc_lock, flags);
cs->writeisacfifo(cs, p, count);
cs->writeisac(cs, ICC_CMDR, more ? 0x8 : 0xa);
icc_write_fifo(cs, p, count);
icc_write_reg(cs, ICC_CMDR, more ? 0x8 : 0xa);
if (test_and_set_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) {
debugl1(cs, "icc_fill_fifo dbusytimer running");
del_timer(&cs->dbusytimer);
......@@ -177,7 +201,7 @@ icc_interrupt(struct IsdnCardState *cs, u_char val)
if (cs->debug & L1_DEB_ISAC)
debugl1(cs, "ICC interrupt %x", val);
if (val & 0x80) { /* RME */
exval = cs->readisac(cs, ICC_RSTA);
exval = icc_read_reg(cs, ICC_RSTA);
if ((exval & 0x70) != 0x20) {
if (exval & 0x40) {
if (cs->debug & L1_DEB_WARN)
......@@ -193,9 +217,9 @@ icc_interrupt(struct IsdnCardState *cs, u_char val)
cs->err_crc++;
#endif
}
cs->writeisac(cs, ICC_CMDR, 0x80);
icc_write_reg(cs, ICC_CMDR, 0x80);
} else {
count = cs->readisac(cs, ICC_RBCL) & 0x1f;
count = icc_read_reg(cs, ICC_RBCL) & 0x1f;
if (count == 0)
count = 32;
icc_empty_fifo(cs, count);
......@@ -226,7 +250,7 @@ icc_interrupt(struct IsdnCardState *cs, u_char val)
xmit_xpr_d(cs);
}
if (val & 0x04) { /* CISQ */
exval = cs->readisac(cs, ICC_CIR0);
exval = icc_read_reg(cs, ICC_CIR0);
if (cs->debug & L1_DEB_ISAC)
debugl1(cs, "ICC CIR0 %02X", exval );
if (exval & 2) {
......@@ -236,7 +260,7 @@ icc_interrupt(struct IsdnCardState *cs, u_char val)
sched_d_event(cs, D_L1STATECHANGE);
}
if (exval & 1) {
exval = cs->readisac(cs, ICC_CIR1);
exval = icc_read_reg(cs, ICC_CIR1);
if (cs->debug & L1_DEB_ISAC)
debugl1(cs, "ICC CIR1 %02X", exval );
}
......@@ -247,7 +271,7 @@ icc_interrupt(struct IsdnCardState *cs, u_char val)
debugl1(cs, "ICC SIN interrupt");
}
if (val & 0x01) { /* EXI */
exval = cs->readisac(cs, ICC_EXIR);
exval = icc_read_reg(cs, ICC_EXIR);
if (cs->debug & L1_DEB_WARN)
debugl1(cs, "ICC EXIR %02x", exval);
if (exval & 0x80) { /* XMR */
......@@ -258,7 +282,7 @@ icc_interrupt(struct IsdnCardState *cs, u_char val)
xmit_xdu_d(cs, NULL);
}
if (exval & 0x04) { /* MOS */
v1 = cs->readisac(cs, ICC_MOSR);
v1 = icc_read_reg(cs, ICC_MOSR);
if (cs->debug & L1_DEB_MONITOR)
debugl1(cs, "ICC MOSR %02x", v1);
#if ARCOFI_USE
......@@ -269,7 +293,7 @@ icc_interrupt(struct IsdnCardState *cs, u_char val)
debugl1(cs, "ICC MON RX out of memory!");
cs->dc.icc.mocr &= 0xf0;
cs->dc.icc.mocr |= 0x0a;
cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);
icc_write_reg(cs, ICC_MOCR, cs->dc.icc.mocr);
goto afterMONR0;
} else
cs->dc.icc.mon_rxp = 0;
......@@ -277,18 +301,18 @@ icc_interrupt(struct IsdnCardState *cs, u_char val)
if (cs->dc.icc.mon_rxp >= MAX_MON_FRAME) {
cs->dc.icc.mocr &= 0xf0;
cs->dc.icc.mocr |= 0x0a;
cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);
icc_write_reg(cs, ICC_MOCR, cs->dc.icc.mocr);
cs->dc.icc.mon_rxp = 0;
if (cs->debug & L1_DEB_WARN)
debugl1(cs, "ICC MON RX overflow!");
goto afterMONR0;
}
cs->dc.icc.mon_rx[cs->dc.icc.mon_rxp++] = cs->readisac(cs, ICC_MOR0);
cs->dc.icc.mon_rx[cs->dc.icc.mon_rxp++] = icc_read_reg(cs, ICC_MOR0);
if (cs->debug & L1_DEB_MONITOR)
debugl1(cs, "ICC MOR0 %02x", cs->dc.icc.mon_rx[cs->dc.icc.mon_rxp -1]);
if (cs->dc.icc.mon_rxp == 1) {
cs->dc.icc.mocr |= 0x04;
cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);
icc_write_reg(cs, ICC_MOCR, cs->dc.icc.mocr);
}
}
afterMONR0:
......@@ -299,7 +323,7 @@ icc_interrupt(struct IsdnCardState *cs, u_char val)
debugl1(cs, "ICC MON RX out of memory!");
cs->dc.icc.mocr &= 0x0f;
cs->dc.icc.mocr |= 0xa0;
cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);
icc_write_reg(cs, ICC_MOCR, cs->dc.icc.mocr);
goto afterMONR1;
} else
cs->dc.icc.mon_rxp = 0;
......@@ -307,31 +331,31 @@ icc_interrupt(struct IsdnCardState *cs, u_char val)
if (cs->dc.icc.mon_rxp >= MAX_MON_FRAME) {
cs->dc.icc.mocr &= 0x0f;
cs->dc.icc.mocr |= 0xa0;
cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);
icc_write_reg(cs, ICC_MOCR, cs->dc.icc.mocr);
cs->dc.icc.mon_rxp = 0;
if (cs->debug & L1_DEB_WARN)
debugl1(cs, "ICC MON RX overflow!");
goto afterMONR1;
}
cs->dc.icc.mon_rx[cs->dc.icc.mon_rxp++] = cs->readisac(cs, ICC_MOR1);
cs->dc.icc.mon_rx[cs->dc.icc.mon_rxp++] = icc_read_reg(cs, ICC_MOR1);
if (cs->debug & L1_DEB_MONITOR)
debugl1(cs, "ICC MOR1 %02x", cs->dc.icc.mon_rx[cs->dc.icc.mon_rxp -1]);
cs->dc.icc.mocr |= 0x40;
cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);
icc_write_reg(cs, ICC_MOCR, cs->dc.icc.mocr);
}
afterMONR1:
if (v1 & 0x04) {
cs->dc.icc.mocr &= 0xf0;
cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);
icc_write_reg(cs, ICC_MOCR, cs->dc.icc.mocr);
cs->dc.icc.mocr |= 0x0a;
cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);
icc_write_reg(cs, ICC_MOCR, cs->dc.icc.mocr);
sched_d_event(cs, D_RX_MON0);
}
if (v1 & 0x40) {
cs->dc.icc.mocr &= 0x0f;
cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);
icc_write_reg(cs, ICC_MOCR, cs->dc.icc.mocr);
cs->dc.icc.mocr |= 0xa0;
cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);
icc_write_reg(cs, ICC_MOCR, cs->dc.icc.mocr);
sched_d_event(cs, D_RX_MON1);
}
if (v1 & 0x02) {
......@@ -339,9 +363,9 @@ icc_interrupt(struct IsdnCardState *cs, u_char val)
(cs->dc.icc.mon_txp >= cs->dc.icc.mon_txc) &&
!(v1 & 0x08))) {
cs->dc.icc.mocr &= 0xf0;
cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);
icc_write_reg(cs, ICC_MOCR, cs->dc.icc.mocr);
cs->dc.icc.mocr |= 0x0a;
cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);
icc_write_reg(cs, ICC_MOCR, cs->dc.icc.mocr);
if (cs->dc.icc.mon_txc &&
(cs->dc.icc.mon_txp >= cs->dc.icc.mon_txc))
sched_d_event(cs, D_TX_MON0);
......@@ -351,7 +375,7 @@ icc_interrupt(struct IsdnCardState *cs, u_char val)
sched_d_event(cs, D_TX_MON0);
goto AfterMOX0;
}
cs->writeisac(cs, ICC_MOX0,
icc_write_reg(cs, ICC_MOX0,
cs->dc.icc.mon_tx[cs->dc.icc.mon_txp++]);
if (cs->debug & L1_DEB_MONITOR)
debugl1(cs, "ICC %02x -> MOX0", cs->dc.icc.mon_tx[cs->dc.icc.mon_txp -1]);
......@@ -362,9 +386,9 @@ icc_interrupt(struct IsdnCardState *cs, u_char val)
(cs->dc.icc.mon_txp >= cs->dc.icc.mon_txc) &&
!(v1 & 0x80))) {
cs->dc.icc.mocr &= 0x0f;
cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);
icc_write_reg(cs, ICC_MOCR, cs->dc.icc.mocr);
cs->dc.icc.mocr |= 0xa0;
cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr);
icc_write_reg(cs, ICC_MOCR, cs->dc.icc.mocr);
if (cs->dc.icc.mon_txc &&
(cs->dc.icc.mon_txp >= cs->dc.icc.mon_txc))
sched_d_event(cs, D_TX_MON1);
......@@ -374,7 +398,7 @@ icc_interrupt(struct IsdnCardState *cs, u_char val)
sched_d_event(cs, D_TX_MON1);
goto AfterMOX1;
}
cs->writeisac(cs, ICC_MOX1,
icc_write_reg(cs, ICC_MOX1,
cs->dc.icc.mon_tx[cs->dc.icc.mon_txp++]);
if (cs->debug & L1_DEB_MONITOR)
debugl1(cs, "ICC %02x -> MOX1", cs->dc.icc.mon_tx[cs->dc.icc.mon_txp -1]);
......@@ -427,19 +451,19 @@ ICC_l1hw(struct PStack *st, int pr, void *arg)
if (test_bit(HW_IOM1, &cs->HW_Flags)) {
/* IOM 1 Mode */
if (!val) {
cs->writeisac(cs, ICC_SPCR, 0xa);
cs->writeisac(cs, ICC_ADF1, 0x2);
icc_write_reg(cs, ICC_SPCR, 0xa);
icc_write_reg(cs, ICC_ADF1, 0x2);
} else {
cs->writeisac(cs, ICC_SPCR, val);
cs->writeisac(cs, ICC_ADF1, 0xa);
icc_write_reg(cs, ICC_SPCR, val);
icc_write_reg(cs, ICC_ADF1, 0xa);
}
} else {
/* IOM 2 Mode */
cs->writeisac(cs, ICC_SPCR, val);
icc_write_reg(cs, ICC_SPCR, val);
if (val)
cs->writeisac(cs, ICC_ADF1, 0x8);
icc_write_reg(cs, ICC_ADF1, 0x8);
else
cs->writeisac(cs, ICC_ADF1, 0x0);
icc_write_reg(cs, ICC_ADF1, 0x0);
}
break;
case (HW_DEACTIVATE | RESPONSE):
......@@ -486,8 +510,8 @@ dbusy_timer_handler(struct IsdnCardState *cs)
int rbch, star;
if (test_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) {
rbch = cs->readisac(cs, ICC_RBCH);
star = cs->readisac(cs, ICC_STAR);
rbch = icc_read_reg(cs, ICC_RBCH);
star = icc_read_reg(cs, ICC_STAR);
if (cs->debug)
debugl1(cs, "D-Channel Busy RBCH %02x STAR %02x",
rbch, star);
......@@ -509,7 +533,7 @@ dbusy_timer_handler(struct IsdnCardState *cs)
printk(KERN_WARNING "HiSax: ICC D-Channel Busy no skb\n");
debugl1(cs, "D-Channel Busy no skb");
}
cs->writeisac(cs, ICC_CMDR, 0x01); /* Transmitter reset */
icc_write_reg(cs, ICC_CMDR, 0x01); /* Transmitter reset */
cs->irq_func(cs->irq, cs, NULL);
}
}
......@@ -530,46 +554,46 @@ initicc(struct IsdnCardState *cs)
cs->dbusytimer.data = (long) cs;
init_timer(&cs->dbusytimer);
val = cs->readisac(cs, ICC_STAR);
val = icc_read_reg(cs, ICC_STAR);
debugl1(cs, "ICC STAR %x", val);
val = cs->readisac(cs, ICC_MODE);
val = icc_read_reg(cs, ICC_MODE);
debugl1(cs, "ICC MODE %x", val);
val = cs->readisac(cs, ICC_ADF2);
val = icc_read_reg(cs, ICC_ADF2);
debugl1(cs, "ICC ADF2 %x", val);
val = cs->readisac(cs, ICC_ISTA);
val = icc_read_reg(cs, ICC_ISTA);
debugl1(cs, "ICC ISTA %x", val);
if (val & 0x01) {
eval = cs->readisac(cs, ICC_EXIR);
eval = icc_read_reg(cs, ICC_EXIR);
debugl1(cs, "ICC EXIR %x", eval);
}
val = cs->readisac(cs, ICC_CIR0);
val = icc_read_reg(cs, ICC_CIR0);
debugl1(cs, "ICC CIR0 %x", val);
cs->dc.icc.ph_state = (val >> 2) & 0xf;
sched_d_event(cs, D_L1STATECHANGE);
/* Disable all IRQ */
cs->writeisac(cs, ICC_MASK, 0xFF);
icc_write_reg(cs, ICC_MASK, 0xFF);
cs->dc.icc.mocr = 0xaa;
if (test_bit(HW_IOM1, &cs->HW_Flags)) {
/* IOM 1 Mode */
cs->writeisac(cs, ICC_ADF2, 0x0);
cs->writeisac(cs, ICC_SPCR, 0xa);
cs->writeisac(cs, ICC_ADF1, 0x2);
cs->writeisac(cs, ICC_STCR, 0x70);
cs->writeisac(cs, ICC_MODE, 0xc9);
icc_write_reg(cs, ICC_ADF2, 0x0);
icc_write_reg(cs, ICC_SPCR, 0xa);
icc_write_reg(cs, ICC_ADF1, 0x2);
icc_write_reg(cs, ICC_STCR, 0x70);
icc_write_reg(cs, ICC_MODE, 0xc9);
} else {
/* IOM 2 Mode */
if (!cs->dc.icc.adf2)
cs->dc.icc.adf2 = 0x80;
cs->writeisac(cs, ICC_ADF2, cs->dc.icc.adf2);
cs->writeisac(cs, ICC_SQXR, 0xa0);
cs->writeisac(cs, ICC_SPCR, 0x20);
cs->writeisac(cs, ICC_STCR, 0x70);
cs->writeisac(cs, ICC_MODE, 0xca);
cs->writeisac(cs, ICC_TIMR, 0x00);
cs->writeisac(cs, ICC_ADF1, 0x20);
icc_write_reg(cs, ICC_ADF2, cs->dc.icc.adf2);
icc_write_reg(cs, ICC_SQXR, 0xa0);
icc_write_reg(cs, ICC_SPCR, 0x20);
icc_write_reg(cs, ICC_STCR, 0x70);
icc_write_reg(cs, ICC_MODE, 0xca);
icc_write_reg(cs, ICC_TIMR, 0x00);
icc_write_reg(cs, ICC_ADF1, 0x20);
}
ph_command(cs, ICC_CMD_RES);
cs->writeisac(cs, ICC_MASK, 0x0);
icc_write_reg(cs, ICC_MASK, 0x0);
ph_command(cs, ICC_CMD_DI);
}
drivers/isdn/hisax/ipacx.c
View file @ 4d0f04d4
......@@ -71,6 +71,29 @@ ipacx_bc_write_reg(struct BCState *bcs, u8 addr, u8 val)
cs->bc_hw_ops->write_reg(cs, hscx, addr, val);
}
static inline u8
ipacx_read_reg(struct IsdnCardState *cs, u8 addr)
{
return cs->readisac(cs, addr);
}
static inline void
ipacx_write_reg(struct IsdnCardState *cs, u8 addr, u8 val)
{
cs->writeisac(cs, addr, val);
}
static inline void
ipacx_read_fifo(struct IsdnCardState *cs, u8 *p, int len)
{
return cs->readisacfifo(cs, p, len);
}
static inline void
ipacx_write_fifo(struct IsdnCardState *cs, u8 *p, int len)
{
return cs->writeisacfifo(cs, p, len);
}
//----------------------------------------------------------
// Issue Layer 1 command to chip
//----------------------------------------------------------
......@@ -80,7 +103,7 @@ ph_command(struct IsdnCardState *cs, unsigned int command)
if (cs->debug &L1_DEB_ISAC)
debugl1(cs, "ph_command (%#x) in (%#x)", command,
cs->dc.isac.ph_state);
cs->writeisac(cs, IPACX_CIX0, (command << 4) | 0x0E);
ipacx_write_reg(cs, IPACX_CIX0, (command << 4) | 0x0E);
}
//----------------------------------------------------------
......@@ -91,7 +114,7 @@ cic_int(struct IsdnCardState *cs)
{
u_char event;
event = cs->readisac(cs, IPACX_CIR0) >> 4;
event = ipacx_read_reg(cs, IPACX_CIR0) >> 4;
if (cs->debug &L1_DEB_ISAC) debugl1(cs, "cic_int(event=%#x)", event);
cs->dc.isac.ph_state = event;
sched_d_event(cs, D_L1STATECHANGE);
......@@ -131,21 +154,21 @@ dch_l2l1(struct PStack *st, int pr, void *arg)
break;
case (HW_TESTLOOP | REQUEST):
cs->writeisac(cs, IPACX_CDA_TSDP10, 0x80); // Timeslot 0 is B1
cs->writeisac(cs, IPACX_CDA_TSDP11, 0x81); // Timeslot 0 is B1
cda1_cr = cs->readisac(cs, IPACX_CDA1_CR);
cda2_cr = cs->readisac(cs, IPACX_CDA2_CR);
ipacx_write_reg(cs, IPACX_CDA_TSDP10, 0x80); // Timeslot 0 is B1
ipacx_write_reg(cs, IPACX_CDA_TSDP11, 0x81); // Timeslot 0 is B1
cda1_cr = ipacx_read_reg(cs, IPACX_CDA1_CR);
cda2_cr = ipacx_read_reg(cs, IPACX_CDA2_CR);
if ((long)arg &1) { // loop B1
cs->writeisac(cs, IPACX_CDA1_CR, cda1_cr |0x0a);
ipacx_write_reg(cs, IPACX_CDA1_CR, cda1_cr |0x0a);
}
else { // B1 off
cs->writeisac(cs, IPACX_CDA1_CR, cda1_cr &~0x0a);
ipacx_write_reg(cs, IPACX_CDA1_CR, cda1_cr &~0x0a);
}
if ((long)arg &2) { // loop B2
cs->writeisac(cs, IPACX_CDA1_CR, cda1_cr |0x14);
ipacx_write_reg(cs, IPACX_CDA1_CR, cda1_cr |0x14);
}
else { // B2 off
cs->writeisac(cs, IPACX_CDA1_CR, cda1_cr &~0x14);
ipacx_write_reg(cs, IPACX_CDA1_CR, cda1_cr &~0x14);
}
break;
......@@ -175,8 +198,8 @@ dbusy_timer_handler(struct IsdnCardState *cs)
int rbchd, stard;
if (test_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) {
rbchd = cs->readisac(cs, IPACX_RBCHD);
stard = cs->readisac(cs, IPACX_STARD);
rbchd = ipacx_read_reg(cs, IPACX_RBCHD);
stard = ipacx_read_reg(cs, IPACX_STARD);
if (cs->debug)
debugl1(cs, "D-Channel Busy RBCHD %02x STARD %02x", rbchd, stard);
if (!(stard &0x40)) { // D-Channel Busy
......@@ -195,7 +218,7 @@ dbusy_timer_handler(struct IsdnCardState *cs)
printk(KERN_WARNING "HiSax: ISAC D-Channel Busy no skb\n");
debugl1(cs, "D-Channel Busy no skb");
}
cs->writeisac(cs, IPACX_CMDRD, 0x01); // Tx reset, generates XPR
ipacx_write_reg(cs, IPACX_CMDRD, 0x01); // Tx reset, generates XPR
}
}
}
......@@ -291,7 +314,7 @@ dch_empty_fifo(struct IsdnCardState *cs, int count)
if ((cs->rcvidx + count) >= MAX_DFRAME_LEN_L1) {
if (cs->debug &L1_DEB_WARN)
debugl1(cs, "dch_empty_fifo() incoming message too large");
cs->writeisac(cs, IPACX_CMDRD, 0x80); // RMC
ipacx_write_reg(cs, IPACX_CMDRD, 0x80); // RMC
cs->rcvidx = 0;
return;
}
......@@ -299,8 +322,8 @@ dch_empty_fifo(struct IsdnCardState *cs, int count)
ptr = cs->rcvbuf + cs->rcvidx;
cs->rcvidx += count;
cs->readisacfifo(cs, ptr, count);
cs->writeisac(cs, IPACX_CMDRD, 0x80); // RMC
ipacx_read_fifo(cs, ptr, count);
ipacx_write_reg(cs, IPACX_CMDRD, 0x80); // RMC
if (cs->debug &L1_DEB_ISAC_FIFO) {
char *t = cs->dlog;
......@@ -330,8 +353,8 @@ dch_fill_fifo(struct IsdnCardState *cs)
cmd = 0x0A; // XTF | XME
}
cs->writeisacfifo(cs, p, count);
cs->writeisac(cs, IPACX_CMDRD, cmd);
ipacx_write_fifo(cs, p, count);
ipacx_write_reg(cs, IPACX_CMDRD, cmd);
// set timeout for transmission contol
if (test_and_set_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) {
......@@ -353,10 +376,10 @@ dch_int(struct IsdnCardState *cs)
u_char istad, rstad;
int count;
istad = cs->readisac(cs, IPACX_ISTAD);
istad = ipacx_read_reg(cs, IPACX_ISTAD);
if (istad &0x80) { // RME
rstad = cs->readisac(cs, IPACX_RSTAD);
rstad = ipacx_read_reg(cs, IPACX_RSTAD);
if ((rstad &0xf0) != 0xa0) { // !(VFR && !RDO && CRC && !RAB)
if (!(rstad &0x80))
if (cs->debug &L1_DEB_WARN)
......@@ -367,9 +390,9 @@ dch_int(struct IsdnCardState *cs)
if (!(rstad &0x20))
if (cs->debug &L1_DEB_WARN)
debugl1(cs, "dch_int(): CRC error");
cs->writeisac(cs, IPACX_CMDRD, 0x80); // RMC
ipacx_write_reg(cs, IPACX_CMDRD, 0x80); // RMC
} else { // received frame ok
count = cs->readisac(cs, IPACX_RBCLD);
count = ipacx_read_reg(cs, IPACX_RBCLD);
if (count) count--; // RSTAB is last byte
count &= D_FIFO_SIZE-1;
if (count == 0) count = D_FIFO_SIZE;
......@@ -394,7 +417,7 @@ dch_int(struct IsdnCardState *cs)
if (istad &0x20) { // RFO
if (cs->debug &L1_DEB_WARN) debugl1(cs, "dch_int(): RFO");
cs->writeisac(cs, IPACX_CMDRD, 0x40); //RRES
ipacx_write_reg(cs, IPACX_CMDRD, 0x40); //RRES
}
if (istad &0x10) { // XPR
......@@ -428,10 +451,10 @@ dch_init(struct IsdnCardState *cs)
cs->dbusytimer.data = (long) cs;
init_timer(&cs->dbusytimer);
cs->writeisac(cs, IPACX_TR_CONF0, 0x00); // clear LDD
cs->writeisac(cs, IPACX_TR_CONF2, 0x00); // enable transmitter
cs->writeisac(cs, IPACX_MODED, 0xC9); // transparent mode 0, RAC, stop/go
cs->writeisac(cs, IPACX_MON_CR, 0x00); // disable monitor channel
ipacx_write_reg(cs, IPACX_TR_CONF0, 0x00); // clear LDD
ipacx_write_reg(cs, IPACX_TR_CONF2, 0x00); // enable transmitter
ipacx_write_reg(cs, IPACX_MODED, 0xC9); // transparent mode 0, RAC, stop/go
ipacx_write_reg(cs, IPACX_MON_CR, 0x00); // disable monitor channel
}
......@@ -639,13 +662,13 @@ bch_mode(struct BCState *bcs, int mode, int bc)
// map controller to according timeslot
if (!hscx)
{
cs->writeisac(cs, IPACX_BCHA_TSDP_BC1, 0x80 | bc);
cs->writeisac(cs, IPACX_BCHA_CR, 0x88);
ipacx_write_reg(cs, IPACX_BCHA_TSDP_BC1, 0x80 | bc);
ipacx_write_reg(cs, IPACX_BCHA_CR, 0x88);
}
else
{
cs->writeisac(cs, IPACX_BCHB_TSDP_BC1, 0x80 | bc);
cs->writeisac(cs, IPACX_BCHB_CR, 0x88);
ipacx_write_reg(cs, IPACX_BCHB_TSDP_BC1, 0x80 | bc);
ipacx_write_reg(cs, IPACX_BCHB_CR, 0x88);
}
switch (mode) {
......@@ -767,7 +790,7 @@ interrupt_ipacx(struct IsdnCardState *cs)
u_char ista;
spin_lock(&cs->lock);
while ((ista = cs->readisac(cs, IPACX_ISTA))) {
while ((ista = ipacx_read_reg(cs, IPACX_ISTA))) {
if (ista &0x80) bch_int(cs, 0); // B channel interrupts
if (ista &0x40) bch_int(cs, 1);
if (ista &0x01) dch_int(cs); // D channel
......@@ -785,16 +808,16 @@ clear_pending_ints(struct IsdnCardState *cs)
int ista;
// all interrupts off
cs->writeisac(cs, IPACX_MASK, 0xff);
cs->writeisac(cs, IPACX_MASKD, 0xff);
ipacx_write_reg(cs, IPACX_MASK, 0xff);
ipacx_write_reg(cs, IPACX_MASKD, 0xff);
cs->bc_hw_ops->write_reg(cs, 0, IPACX_MASKB, 0xff);
cs->bc_hw_ops->write_reg(cs, 1, IPACX_MASKB, 0xff);
ista = cs->readisac(cs, IPACX_ISTA);
ista = ipacx_read_reg(cs, IPACX_ISTA);
if (ista &0x80) cs->bc_hw_ops->read_reg(cs, 0, IPACX_ISTAB);
if (ista &0x40) cs->bc_hw_ops->read_reg(cs, 1, IPACX_ISTAB);
if (ista &0x10) cs->readisac(cs, IPACX_CIR0);
if (ista &0x01) cs->readisac(cs, IPACX_ISTAD);
if (ista &0x10) ipacx_read_reg(cs, IPACX_CIR0);
if (ista &0x01) ipacx_read_reg(cs, IPACX_ISTAD);
}
//----------------------------------------------------------
......@@ -813,11 +836,11 @@ init_ipacx(struct IsdnCardState *cs, int part)
if (part &2) { // reenable all interrupts and start chip
cs->bc_hw_ops->write_reg(cs, 0, IPACX_MASKB, _MASKB_IMASK);
cs->bc_hw_ops->write_reg(cs, 1, IPACX_MASKB, _MASKB_IMASK);
cs->writeisac(cs, IPACX_MASKD, _MASKD_IMASK);
cs->writeisac(cs, IPACX_MASK, _MASK_IMASK); // global mask register
ipacx_write_reg(cs, IPACX_MASKD, _MASKD_IMASK);
ipacx_write_reg(cs, IPACX_MASK, _MASK_IMASK); // global mask register
// reset HDLC Transmitters/receivers
cs->writeisac(cs, IPACX_CMDRD, 0x41);
ipacx_write_reg(cs, IPACX_CMDRD, 0x41);
cs->bc_hw_ops->write_reg(cs, 0, IPACX_CMDRB, 0x41);
cs->bc_hw_ops->write_reg(cs, 1, IPACX_CMDRB, 0x41);
ph_command(cs, IPACX_CMD_RES);
......
drivers/isdn/hisax/isac.c
View file @ 4d0f04d4
......@@ -32,7 +32,7 @@ ISACVersion(struct IsdnCardState *cs, char *s)
{
int val;
val = cs->readisac(cs, ISAC_RBCH);
val = isac_read_reg(cs, ISAC_RBCH);
printk(KERN_INFO "%s ISAC version (%x): %s\n", s, val, ISACVer[(val >> 5) & 3]);
}
......@@ -41,7 +41,7 @@ ph_command(struct IsdnCardState *cs, unsigned int command)
{
if (cs->debug & L1_DEB_ISAC)
debugl1(cs, "ph_command %x", command);
cs->writeisac(cs, ISAC_CIX0, (command << 2) | 3);
isac_write_reg(cs, ISAC_CIX0, (command << 2) | 3);
}
......@@ -125,14 +125,14 @@ isac_empty_fifo(struct IsdnCardState *cs, int count)
if (cs->debug & L1_DEB_WARN)
debugl1(cs, "isac_empty_fifo overrun %d",
cs->rcvidx + count);
cs->writeisac(cs, ISAC_CMDR, 0x80);
isac_write_reg(cs, ISAC_CMDR, 0x80);
cs->rcvidx = 0;
return;
}
ptr = cs->rcvbuf + cs->rcvidx;
cs->rcvidx += count;
cs->readisacfifo(cs, ptr, count);
cs->writeisac(cs, ISAC_CMDR, 0x80);
isac_read_fifo(cs, ptr, count);
isac_write_reg(cs, ISAC_CMDR, 0x80);
if (cs->debug & L1_DEB_ISAC_FIFO) {
char *t = cs->dlog;
......@@ -152,8 +152,8 @@ isac_fill_fifo(struct IsdnCardState *cs)
if (!p)
return;
cs->writeisacfifo(cs, p, count);
cs->writeisac(cs, ISAC_CMDR, more ? 0x8 : 0xa);
isac_write_fifo(cs, p, count);
isac_write_reg(cs, ISAC_CMDR, more ? 0x8 : 0xa);
if (test_and_set_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) {
debugl1(cs, "isac_fill_fifo dbusytimer running");
del_timer(&cs->dbusytimer);
......@@ -173,7 +173,7 @@ isac_interrupt(struct IsdnCardState *cs, u_char val)
if (cs->debug & L1_DEB_ISAC)
debugl1(cs, "ISAC interrupt %x", val);
if (val & 0x80) { /* RME */
exval = cs->readisac(cs, ISAC_RSTA);
exval = isac_read_reg(cs, ISAC_RSTA);
if ((exval & 0x70) != 0x20) {
if (exval & 0x40) {
if (cs->debug & L1_DEB_WARN)
......@@ -189,9 +189,9 @@ isac_interrupt(struct IsdnCardState *cs, u_char val)
cs->err_crc++;
#endif
}
cs->writeisac(cs, ISAC_CMDR, 0x80);
isac_write_reg(cs, ISAC_CMDR, 0x80);
} else {
count = cs->readisac(cs, ISAC_RBCL) & 0x1f;
count = isac_read_reg(cs, ISAC_RBCL) & 0x1f;
if (count == 0)
count = 32;
isac_empty_fifo(cs, count);
......@@ -220,7 +220,7 @@ isac_interrupt(struct IsdnCardState *cs, u_char val)
xmit_xpr_d(cs);
}
if (val & 0x04) { /* CISQ */
exval = cs->readisac(cs, ISAC_CIR0);
exval = isac_read_reg(cs, ISAC_CIR0);
if (cs->debug & L1_DEB_ISAC)
debugl1(cs, "ISAC CIR0 %02X", exval );
if (exval & 2) {
......@@ -230,7 +230,7 @@ isac_interrupt(struct IsdnCardState *cs, u_char val)
sched_d_event(cs, D_L1STATECHANGE);
}
if (exval & 1) {
exval = cs->readisac(cs, ISAC_CIR1);
exval = isac_read_reg(cs, ISAC_CIR1);
if (cs->debug & L1_DEB_ISAC)
debugl1(cs, "ISAC CIR1 %02X", exval );
}
......@@ -241,7 +241,7 @@ isac_interrupt(struct IsdnCardState *cs, u_char val)
debugl1(cs, "ISAC SIN interrupt");
}
if (val & 0x01) { /* EXI */
exval = cs->readisac(cs, ISAC_EXIR);
exval = isac_read_reg(cs, ISAC_EXIR);
if (cs->debug & L1_DEB_WARN)
debugl1(cs, "ISAC EXIR %02x", exval);
if (exval & 0x80) { /* XMR */
......@@ -252,7 +252,7 @@ isac_interrupt(struct IsdnCardState *cs, u_char val)
xmit_xdu_d(cs, NULL);
}
if (exval & 0x04) { /* MOS */
v1 = cs->readisac(cs, ISAC_MOSR);
v1 = isac_read_reg(cs, ISAC_MOSR);
if (cs->debug & L1_DEB_MONITOR)
debugl1(cs, "ISAC MOSR %02x", v1);
#if ARCOFI_USE
......@@ -263,7 +263,7 @@ isac_interrupt(struct IsdnCardState *cs, u_char val)
debugl1(cs, "ISAC MON RX out of memory!");
cs->dc.isac.mocr &= 0xf0;
cs->dc.isac.mocr |= 0x0a;
cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
isac_write_reg(cs, ISAC_MOCR, cs->dc.isac.mocr);
goto afterMONR0;
} else
cs->dc.isac.mon_rxp = 0;
......@@ -271,18 +271,18 @@ isac_interrupt(struct IsdnCardState *cs, u_char val)
if (cs->dc.isac.mon_rxp >= MAX_MON_FRAME) {
cs->dc.isac.mocr &= 0xf0;
cs->dc.isac.mocr |= 0x0a;
cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
isac_write_reg(cs, ISAC_MOCR, cs->dc.isac.mocr);
cs->dc.isac.mon_rxp = 0;
if (cs->debug & L1_DEB_WARN)
debugl1(cs, "ISAC MON RX overflow!");
goto afterMONR0;
}
cs->dc.isac.mon_rx[cs->dc.isac.mon_rxp++] = cs->readisac(cs, ISAC_MOR0);
cs->dc.isac.mon_rx[cs->dc.isac.mon_rxp++] = isac_read_reg(cs, ISAC_MOR0);
if (cs->debug & L1_DEB_MONITOR)
debugl1(cs, "ISAC MOR0 %02x", cs->dc.isac.mon_rx[cs->dc.isac.mon_rxp -1]);
if (cs->dc.isac.mon_rxp == 1) {
cs->dc.isac.mocr |= 0x04;
cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
isac_write_reg(cs, ISAC_MOCR, cs->dc.isac.mocr);
}
}
afterMONR0:
......@@ -293,7 +293,7 @@ isac_interrupt(struct IsdnCardState *cs, u_char val)
debugl1(cs, "ISAC MON RX out of memory!");
cs->dc.isac.mocr &= 0x0f;
cs->dc.isac.mocr |= 0xa0;
cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
isac_write_reg(cs, ISAC_MOCR, cs->dc.isac.mocr);
goto afterMONR1;
} else
cs->dc.isac.mon_rxp = 0;
......@@ -301,31 +301,31 @@ isac_interrupt(struct IsdnCardState *cs, u_char val)
if (cs->dc.isac.mon_rxp >= MAX_MON_FRAME) {
cs->dc.isac.mocr &= 0x0f;
cs->dc.isac.mocr |= 0xa0;
cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
isac_write_reg(cs, ISAC_MOCR, cs->dc.isac.mocr);
cs->dc.isac.mon_rxp = 0;
if (cs->debug & L1_DEB_WARN)
debugl1(cs, "ISAC MON RX overflow!");
goto afterMONR1;
}
cs->dc.isac.mon_rx[cs->dc.isac.mon_rxp++] = cs->readisac(cs, ISAC_MOR1);
cs->dc.isac.mon_rx[cs->dc.isac.mon_rxp++] = isac_read_reg(cs, ISAC_MOR1);
if (cs->debug & L1_DEB_MONITOR)
debugl1(cs, "ISAC MOR1 %02x", cs->dc.isac.mon_rx[cs->dc.isac.mon_rxp -1]);
cs->dc.isac.mocr |= 0x40;
cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
isac_write_reg(cs, ISAC_MOCR, cs->dc.isac.mocr);
}
afterMONR1:
if (v1 & 0x04) {
cs->dc.isac.mocr &= 0xf0;
cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
isac_write_reg(cs, ISAC_MOCR, cs->dc.isac.mocr);
cs->dc.isac.mocr |= 0x0a;
cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
isac_write_reg(cs, ISAC_MOCR, cs->dc.isac.mocr);
sched_d_event(cs, D_RX_MON0);
}
if (v1 & 0x40) {
cs->dc.isac.mocr &= 0x0f;
cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
isac_write_reg(cs, ISAC_MOCR, cs->dc.isac.mocr);
cs->dc.isac.mocr |= 0xa0;
cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
isac_write_reg(cs, ISAC_MOCR, cs->dc.isac.mocr);
sched_d_event(cs, D_RX_MON1);
}
if (v1 & 0x02) {
......@@ -333,9 +333,9 @@ isac_interrupt(struct IsdnCardState *cs, u_char val)
(cs->dc.isac.mon_txp >= cs->dc.isac.mon_txc) &&
!(v1 & 0x08))) {
cs->dc.isac.mocr &= 0xf0;
cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
isac_write_reg(cs, ISAC_MOCR, cs->dc.isac.mocr);
cs->dc.isac.mocr |= 0x0a;
cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
isac_write_reg(cs, ISAC_MOCR, cs->dc.isac.mocr);
if (cs->dc.isac.mon_txc &&
(cs->dc.isac.mon_txp >= cs->dc.isac.mon_txc))
sched_d_event(cs, D_TX_MON0);
......@@ -345,7 +345,7 @@ isac_interrupt(struct IsdnCardState *cs, u_char val)
sched_d_event(cs, D_TX_MON0);
goto AfterMOX0;
}
cs->writeisac(cs, ISAC_MOX0,
isac_write_reg(cs, ISAC_MOX0,
cs->dc.isac.mon_tx[cs->dc.isac.mon_txp++]);
if (cs->debug & L1_DEB_MONITOR)
debugl1(cs, "ISAC %02x -> MOX0", cs->dc.isac.mon_tx[cs->dc.isac.mon_txp -1]);
......@@ -356,9 +356,9 @@ isac_interrupt(struct IsdnCardState *cs, u_char val)
(cs->dc.isac.mon_txp >= cs->dc.isac.mon_txc) &&
!(v1 & 0x80))) {
cs->dc.isac.mocr &= 0x0f;
cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
isac_write_reg(cs, ISAC_MOCR, cs->dc.isac.mocr);
cs->dc.isac.mocr |= 0xa0;
cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
isac_write_reg(cs, ISAC_MOCR, cs->dc.isac.mocr);
if (cs->dc.isac.mon_txc &&
(cs->dc.isac.mon_txp >= cs->dc.isac.mon_txc))
sched_d_event(cs, D_TX_MON1);
......@@ -368,7 +368,7 @@ isac_interrupt(struct IsdnCardState *cs, u_char val)
sched_d_event(cs, D_TX_MON1);
goto AfterMOX1;
}
cs->writeisac(cs, ISAC_MOX1,
isac_write_reg(cs, ISAC_MOX1,
cs->dc.isac.mon_tx[cs->dc.isac.mon_txp++]);
if (cs->debug & L1_DEB_MONITOR)
debugl1(cs, "ISAC %02x -> MOX1", cs->dc.isac.mon_tx[cs->dc.isac.mon_txp -1]);
......@@ -419,19 +419,19 @@ ISAC_l1hw(struct PStack *st, int pr, void *arg)
if (test_bit(HW_IOM1, &cs->HW_Flags)) {
/* IOM 1 Mode */
if (!val) {
cs->writeisac(cs, ISAC_SPCR, 0xa);
cs->writeisac(cs, ISAC_ADF1, 0x2);
isac_write_reg(cs, ISAC_SPCR, 0xa);
isac_write_reg(cs, ISAC_ADF1, 0x2);
} else {
cs->writeisac(cs, ISAC_SPCR, val);
cs->writeisac(cs, ISAC_ADF1, 0xa);
isac_write_reg(cs, ISAC_SPCR, val);
isac_write_reg(cs, ISAC_ADF1, 0xa);
}
} else {
/* IOM 2 Mode */
cs->writeisac(cs, ISAC_SPCR, val);
isac_write_reg(cs, ISAC_SPCR, val);
if (val)
cs->writeisac(cs, ISAC_ADF1, 0x8);
isac_write_reg(cs, ISAC_ADF1, 0x8);
else
cs->writeisac(cs, ISAC_ADF1, 0x0);
isac_write_reg(cs, ISAC_ADF1, 0x0);
}
break;
case (HW_DEACTIVATE | RESPONSE):
......@@ -478,8 +478,8 @@ dbusy_timer_handler(struct IsdnCardState *cs)
int rbch, star;
if (test_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) {
rbch = cs->readisac(cs, ISAC_RBCH);
star = cs->readisac(cs, ISAC_STAR);
rbch = isac_read_reg(cs, ISAC_RBCH);
star = isac_read_reg(cs, ISAC_STAR);
if (cs->debug)
debugl1(cs, "D-Channel Busy RBCH %02x STAR %02x",
rbch, star);
......@@ -501,7 +501,7 @@ dbusy_timer_handler(struct IsdnCardState *cs)
printk(KERN_WARNING "HiSax: ISAC D-Channel Busy no skb\n");
debugl1(cs, "D-Channel Busy no skb");
}
cs->writeisac(cs, ISAC_CMDR, 0x01); /* Transmitter reset */
isac_write_reg(cs, ISAC_CMDR, 0x01); /* Transmitter reset */
cs->irq_func(cs->irq, cs, NULL);
}
}
......@@ -512,20 +512,20 @@ initisac(struct IsdnCardState *cs)
{
int val, eval;
val = cs->readisac(cs, ISAC_STAR);
val = isac_read_reg(cs, ISAC_STAR);
debugl1(cs, "ISAC STAR %x", val);
val = cs->readisac(cs, ISAC_MODE);
val = isac_read_reg(cs, ISAC_MODE);
debugl1(cs, "ISAC MODE %x", val);
val = cs->readisac(cs, ISAC_ADF2);
val = isac_read_reg(cs, ISAC_ADF2);
debugl1(cs, "ISAC ADF2 %x", val);
val = cs->readisac(cs, ISAC_ISTA);
val = isac_read_reg(cs, ISAC_ISTA);
debugl1(cs, "ISAC ISTA %x", val);
if (val & 0x01) {
eval = cs->readisac(cs, ISAC_EXIR);
eval = isac_read_reg(cs, ISAC_EXIR);
debugl1(cs, "ISAC EXIR %x", eval);
}
/* Disable all IRQ */
cs->writeisac(cs, ISAC_MASK, 0xFF);
isac_write_reg(cs, ISAC_MASK, 0xFF);
INIT_WORK(&cs->work, isac_bh, cs);
cs->setstack_d = setstack_isac;
......@@ -536,35 +536,35 @@ initisac(struct IsdnCardState *cs)
cs->dbusytimer.function = (void *) dbusy_timer_handler;
cs->dbusytimer.data = (long) cs;
init_timer(&cs->dbusytimer);
cs->writeisac(cs, ISAC_MASK, 0xff);
isac_write_reg(cs, ISAC_MASK, 0xff);
cs->dc.isac.mocr = 0xaa;
if (test_bit(HW_IOM1, &cs->HW_Flags)) {
/* IOM 1 Mode */
cs->writeisac(cs, ISAC_ADF2, 0x0);
cs->writeisac(cs, ISAC_SPCR, 0xa);
cs->writeisac(cs, ISAC_ADF1, 0x2);
cs->writeisac(cs, ISAC_STCR, 0x70);
cs->writeisac(cs, ISAC_MODE, 0xc9);
isac_write_reg(cs, ISAC_ADF2, 0x0);
isac_write_reg(cs, ISAC_SPCR, 0xa);
isac_write_reg(cs, ISAC_ADF1, 0x2);
isac_write_reg(cs, ISAC_STCR, 0x70);
isac_write_reg(cs, ISAC_MODE, 0xc9);
} else {
/* IOM 2 Mode */
if (!cs->dc.isac.adf2)
cs->dc.isac.adf2 = 0x80;
cs->writeisac(cs, ISAC_ADF2, cs->dc.isac.adf2);
cs->writeisac(cs, ISAC_SQXR, 0x2f);
cs->writeisac(cs, ISAC_SPCR, 0x00);
cs->writeisac(cs, ISAC_STCR, 0x70);
cs->writeisac(cs, ISAC_MODE, 0xc9);
cs->writeisac(cs, ISAC_TIMR, 0x00);
cs->writeisac(cs, ISAC_ADF1, 0x00);
isac_write_reg(cs, ISAC_ADF2, cs->dc.isac.adf2);
isac_write_reg(cs, ISAC_SQXR, 0x2f);
isac_write_reg(cs, ISAC_SPCR, 0x00);
isac_write_reg(cs, ISAC_STCR, 0x70);
isac_write_reg(cs, ISAC_MODE, 0xc9);
isac_write_reg(cs, ISAC_TIMR, 0x00);
isac_write_reg(cs, ISAC_ADF1, 0x00);
}
ph_command(cs, ISAC_CMD_RS);
cs->writeisac(cs, ISAC_MASK, 0x0);
isac_write_reg(cs, ISAC_MASK, 0x0);
val = cs->readisac(cs, ISAC_CIR0);
val = isac_read_reg(cs, ISAC_CIR0);
debugl1(cs, "ISAC CIR0 %x", val);
cs->dc.isac.ph_state = (val >> 2) & 0xf;
sched_d_event(cs, D_L1STATECHANGE);
/* RESET Receiver and Transmitter */
cs->writeisac(cs, ISAC_CMDR, 0x41);
isac_write_reg(cs, ISAC_CMDR, 0x41);
}
drivers/isdn/hisax/isac.h
View file @ 4d0f04d4
......@@ -66,3 +66,27 @@
extern void ISACVersion(struct IsdnCardState *cs, char *s);
extern void initisac(struct IsdnCardState *cs);
extern void isac_interrupt(struct IsdnCardState *cs, u_char val);
static inline u8
isac_read_reg(struct IsdnCardState *cs, u8 addr)
{
return cs->readisac(cs, addr);
}
static inline void
isac_write_reg(struct IsdnCardState *cs, u8 addr, u8 val)
{
cs->writeisac(cs, addr, val);
}
static inline void
isac_read_fifo(struct IsdnCardState *cs, u8 *p, int len)
{
return cs->readisacfifo(cs, p, len);
}
static inline void
isac_write_fifo(struct IsdnCardState *cs, u8 *p, int len)
{
return cs->writeisacfifo(cs, p, len);
}
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