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Commit 4d0f04d4 authored by Kai Germaschewski's avatar Kai Germaschewski
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ISDN/HiSax: Helper functions for D-Channel {read,write}_reg() etc 

As a preparation for moving the B-Channel access functions into
an ops struct, introduce inline helper functions for using them.
parent 4559dc4a
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Showing with 241 additions and 170 deletions
drivers/isdn/hisax/arcofi.c
View file @ 4d0f04d4
......@@ -43,11 +43,11 @@ send_arcofi(struct IsdnCardState *cs) {
}
cs->dc.isac.mocr &= 0x0f;
cs->dc.isac.mocr |= 0xa0;
cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
val = cs->readisac(cs, ISAC_MOSR);
cs->writeisac(cs, ISAC_MOX1, cs->dc.isac.mon_tx[cs->dc.isac.mon_txp++]);
isac_write_reg(cs, ISAC_MOCR, cs->dc.isac.mocr);
val = isac_read_reg(cs, ISAC_MOSR);
isac_write_reg(cs, ISAC_MOX1, cs->dc.isac.mon_tx[cs->dc.isac.mon_txp++]);
cs->dc.isac.mocr |= 0x10;
cs->writeisac(cs, ISAC_MOCR, cs->dc.isac.mocr);
isac_write_reg(cs, ISAC_MOCR, cs->dc.isac.mocr);
}
int
......
drivers/isdn/hisax/icc.c
View file @ 4d0f04d4
This diff is collapsed.
drivers/isdn/hisax/ipacx.c
View file @ 4d0f04d4
......@@ -71,6 +71,29 @@ ipacx_bc_write_reg(struct BCState *bcs, u8 addr, u8 val)
cs->bc_hw_ops->write_reg(cs, hscx, addr, val);
}
static inline u8
ipacx_read_reg(struct IsdnCardState *cs, u8 addr)
{
return cs->readisac(cs, addr);
}
static inline void
ipacx_write_reg(struct IsdnCardState *cs, u8 addr, u8 val)
{
cs->writeisac(cs, addr, val);
}
static inline void
ipacx_read_fifo(struct IsdnCardState *cs, u8 *p, int len)
{
return cs->readisacfifo(cs, p, len);
}
static inline void
ipacx_write_fifo(struct IsdnCardState *cs, u8 *p, int len)
{
return cs->writeisacfifo(cs, p, len);
}
//----------------------------------------------------------
// Issue Layer 1 command to chip
//----------------------------------------------------------
......@@ -80,7 +103,7 @@ ph_command(struct IsdnCardState *cs, unsigned int command)
if (cs->debug &L1_DEB_ISAC)
debugl1(cs, "ph_command (%#x) in (%#x)", command,
cs->dc.isac.ph_state);
cs->writeisac(cs, IPACX_CIX0, (command << 4) | 0x0E);
ipacx_write_reg(cs, IPACX_CIX0, (command << 4) | 0x0E);
}
//----------------------------------------------------------
......@@ -91,7 +114,7 @@ cic_int(struct IsdnCardState *cs)
{
u_char event;
event = cs->readisac(cs, IPACX_CIR0) >> 4;
event = ipacx_read_reg(cs, IPACX_CIR0) >> 4;
if (cs->debug &L1_DEB_ISAC) debugl1(cs, "cic_int(event=%#x)", event);
cs->dc.isac.ph_state = event;
sched_d_event(cs, D_L1STATECHANGE);
......@@ -131,21 +154,21 @@ dch_l2l1(struct PStack *st, int pr, void *arg)
break;
case (HW_TESTLOOP | REQUEST):
cs->writeisac(cs, IPACX_CDA_TSDP10, 0x80); // Timeslot 0 is B1
cs->writeisac(cs, IPACX_CDA_TSDP11, 0x81); // Timeslot 0 is B1
cda1_cr = cs->readisac(cs, IPACX_CDA1_CR);
cda2_cr = cs->readisac(cs, IPACX_CDA2_CR);
ipacx_write_reg(cs, IPACX_CDA_TSDP10, 0x80); // Timeslot 0 is B1
ipacx_write_reg(cs, IPACX_CDA_TSDP11, 0x81); // Timeslot 0 is B1
cda1_cr = ipacx_read_reg(cs, IPACX_CDA1_CR);
cda2_cr = ipacx_read_reg(cs, IPACX_CDA2_CR);
if ((long)arg &1) { // loop B1
cs->writeisac(cs, IPACX_CDA1_CR, cda1_cr |0x0a);
ipacx_write_reg(cs, IPACX_CDA1_CR, cda1_cr |0x0a);
}
else { // B1 off
cs->writeisac(cs, IPACX_CDA1_CR, cda1_cr &~0x0a);
ipacx_write_reg(cs, IPACX_CDA1_CR, cda1_cr &~0x0a);
}
if ((long)arg &2) { // loop B2
cs->writeisac(cs, IPACX_CDA1_CR, cda1_cr |0x14);
ipacx_write_reg(cs, IPACX_CDA1_CR, cda1_cr |0x14);
}
else { // B2 off
cs->writeisac(cs, IPACX_CDA1_CR, cda1_cr &~0x14);
ipacx_write_reg(cs, IPACX_CDA1_CR, cda1_cr &~0x14);
}
break;
......@@ -175,8 +198,8 @@ dbusy_timer_handler(struct IsdnCardState *cs)
int rbchd, stard;
if (test_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) {
rbchd = cs->readisac(cs, IPACX_RBCHD);
stard = cs->readisac(cs, IPACX_STARD);
rbchd = ipacx_read_reg(cs, IPACX_RBCHD);
stard = ipacx_read_reg(cs, IPACX_STARD);
if (cs->debug)
debugl1(cs, "D-Channel Busy RBCHD %02x STARD %02x", rbchd, stard);
if (!(stard &0x40)) { // D-Channel Busy
......@@ -195,7 +218,7 @@ dbusy_timer_handler(struct IsdnCardState *cs)
printk(KERN_WARNING "HiSax: ISAC D-Channel Busy no skb\n");
debugl1(cs, "D-Channel Busy no skb");
}
cs->writeisac(cs, IPACX_CMDRD, 0x01); // Tx reset, generates XPR
ipacx_write_reg(cs, IPACX_CMDRD, 0x01); // Tx reset, generates XPR
}
}
}
......@@ -291,7 +314,7 @@ dch_empty_fifo(struct IsdnCardState *cs, int count)
if ((cs->rcvidx + count) >= MAX_DFRAME_LEN_L1) {
if (cs->debug &L1_DEB_WARN)
debugl1(cs, "dch_empty_fifo() incoming message too large");
cs->writeisac(cs, IPACX_CMDRD, 0x80); // RMC
ipacx_write_reg(cs, IPACX_CMDRD, 0x80); // RMC
cs->rcvidx = 0;
return;
}
......@@ -299,8 +322,8 @@ dch_empty_fifo(struct IsdnCardState *cs, int count)
ptr = cs->rcvbuf + cs->rcvidx;
cs->rcvidx += count;
cs->readisacfifo(cs, ptr, count);
cs->writeisac(cs, IPACX_CMDRD, 0x80); // RMC
ipacx_read_fifo(cs, ptr, count);
ipacx_write_reg(cs, IPACX_CMDRD, 0x80); // RMC
if (cs->debug &L1_DEB_ISAC_FIFO) {
char *t = cs->dlog;
......@@ -330,8 +353,8 @@ dch_fill_fifo(struct IsdnCardState *cs)
cmd = 0x0A; // XTF | XME
}
cs->writeisacfifo(cs, p, count);
cs->writeisac(cs, IPACX_CMDRD, cmd);
ipacx_write_fifo(cs, p, count);
ipacx_write_reg(cs, IPACX_CMDRD, cmd);
// set timeout for transmission contol
if (test_and_set_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) {
......@@ -353,10 +376,10 @@ dch_int(struct IsdnCardState *cs)
u_char istad, rstad;
int count;
istad = cs->readisac(cs, IPACX_ISTAD);
istad = ipacx_read_reg(cs, IPACX_ISTAD);
if (istad &0x80) { // RME
rstad = cs->readisac(cs, IPACX_RSTAD);
rstad = ipacx_read_reg(cs, IPACX_RSTAD);
if ((rstad &0xf0) != 0xa0) { // !(VFR && !RDO && CRC && !RAB)
if (!(rstad &0x80))
if (cs->debug &L1_DEB_WARN)
......@@ -367,9 +390,9 @@ dch_int(struct IsdnCardState *cs)
if (!(rstad &0x20))
if (cs->debug &L1_DEB_WARN)
debugl1(cs, "dch_int(): CRC error");
cs->writeisac(cs, IPACX_CMDRD, 0x80); // RMC
ipacx_write_reg(cs, IPACX_CMDRD, 0x80); // RMC
} else { // received frame ok
count = cs->readisac(cs, IPACX_RBCLD);
count = ipacx_read_reg(cs, IPACX_RBCLD);
if (count) count--; // RSTAB is last byte
count &= D_FIFO_SIZE-1;
if (count == 0) count = D_FIFO_SIZE;
......@@ -394,7 +417,7 @@ dch_int(struct IsdnCardState *cs)
if (istad &0x20) { // RFO
if (cs->debug &L1_DEB_WARN) debugl1(cs, "dch_int(): RFO");
cs->writeisac(cs, IPACX_CMDRD, 0x40); //RRES
ipacx_write_reg(cs, IPACX_CMDRD, 0x40); //RRES
}
if (istad &0x10) { // XPR
......@@ -428,10 +451,10 @@ dch_init(struct IsdnCardState *cs)
cs->dbusytimer.data = (long) cs;
init_timer(&cs->dbusytimer);
cs->writeisac(cs, IPACX_TR_CONF0, 0x00); // clear LDD
cs->writeisac(cs, IPACX_TR_CONF2, 0x00); // enable transmitter
cs->writeisac(cs, IPACX_MODED, 0xC9); // transparent mode 0, RAC, stop/go
cs->writeisac(cs, IPACX_MON_CR, 0x00); // disable monitor channel
ipacx_write_reg(cs, IPACX_TR_CONF0, 0x00); // clear LDD
ipacx_write_reg(cs, IPACX_TR_CONF2, 0x00); // enable transmitter
ipacx_write_reg(cs, IPACX_MODED, 0xC9); // transparent mode 0, RAC, stop/go
ipacx_write_reg(cs, IPACX_MON_CR, 0x00); // disable monitor channel
}
......@@ -639,13 +662,13 @@ bch_mode(struct BCState *bcs, int mode, int bc)
// map controller to according timeslot
if (!hscx)
{
cs->writeisac(cs, IPACX_BCHA_TSDP_BC1, 0x80 | bc);
cs->writeisac(cs, IPACX_BCHA_CR, 0x88);
ipacx_write_reg(cs, IPACX_BCHA_TSDP_BC1, 0x80 | bc);
ipacx_write_reg(cs, IPACX_BCHA_CR, 0x88);
}
else
{
cs->writeisac(cs, IPACX_BCHB_TSDP_BC1, 0x80 | bc);
cs->writeisac(cs, IPACX_BCHB_CR, 0x88);
ipacx_write_reg(cs, IPACX_BCHB_TSDP_BC1, 0x80 | bc);
ipacx_write_reg(cs, IPACX_BCHB_CR, 0x88);
}
switch (mode) {
......@@ -767,7 +790,7 @@ interrupt_ipacx(struct IsdnCardState *cs)
u_char ista;
spin_lock(&cs->lock);
while ((ista = cs->readisac(cs, IPACX_ISTA))) {
while ((ista = ipacx_read_reg(cs, IPACX_ISTA))) {
if (ista &0x80) bch_int(cs, 0); // B channel interrupts
if (ista &0x40) bch_int(cs, 1);
if (ista &0x01) dch_int(cs); // D channel
......@@ -785,16 +808,16 @@ clear_pending_ints(struct IsdnCardState *cs)
int ista;
// all interrupts off
cs->writeisac(cs, IPACX_MASK, 0xff);
cs->writeisac(cs, IPACX_MASKD, 0xff);
ipacx_write_reg(cs, IPACX_MASK, 0xff);
ipacx_write_reg(cs, IPACX_MASKD, 0xff);
cs->bc_hw_ops->write_reg(cs, 0, IPACX_MASKB, 0xff);
cs->bc_hw_ops->write_reg(cs, 1, IPACX_MASKB, 0xff);
ista = cs->readisac(cs, IPACX_ISTA);
ista = ipacx_read_reg(cs, IPACX_ISTA);
if (ista &0x80) cs->bc_hw_ops->read_reg(cs, 0, IPACX_ISTAB);
if (ista &0x40) cs->bc_hw_ops->read_reg(cs, 1, IPACX_ISTAB);
if (ista &0x10) cs->readisac(cs, IPACX_CIR0);
if (ista &0x01) cs->readisac(cs, IPACX_ISTAD);
if (ista &0x10) ipacx_read_reg(cs, IPACX_CIR0);
if (ista &0x01) ipacx_read_reg(cs, IPACX_ISTAD);
}
//----------------------------------------------------------
......@@ -813,11 +836,11 @@ init_ipacx(struct IsdnCardState *cs, int part)
if (part &2) { // reenable all interrupts and start chip
cs->bc_hw_ops->write_reg(cs, 0, IPACX_MASKB, _MASKB_IMASK);
cs->bc_hw_ops->write_reg(cs, 1, IPACX_MASKB, _MASKB_IMASK);
cs->writeisac(cs, IPACX_MASKD, _MASKD_IMASK);
cs->writeisac(cs, IPACX_MASK, _MASK_IMASK); // global mask register
ipacx_write_reg(cs, IPACX_MASKD, _MASKD_IMASK);
ipacx_write_reg(cs, IPACX_MASK, _MASK_IMASK); // global mask register
// reset HDLC Transmitters/receivers
cs->writeisac(cs, IPACX_CMDRD, 0x41);
ipacx_write_reg(cs, IPACX_CMDRD, 0x41);
cs->bc_hw_ops->write_reg(cs, 0, IPACX_CMDRB, 0x41);
cs->bc_hw_ops->write_reg(cs, 1, IPACX_CMDRB, 0x41);
ph_command(cs, IPACX_CMD_RES);
......
drivers/isdn/hisax/isac.c
View file @ 4d0f04d4
This diff is collapsed.
drivers/isdn/hisax/isac.h
View file @ 4d0f04d4
......@@ -66,3 +66,27 @@
extern void ISACVersion(struct IsdnCardState *cs, char *s);
extern void initisac(struct IsdnCardState *cs);
extern void isac_interrupt(struct IsdnCardState *cs, u_char val);
static inline u8
isac_read_reg(struct IsdnCardState *cs, u8 addr)
{
return cs->readisac(cs, addr);
}
static inline void
isac_write_reg(struct IsdnCardState *cs, u8 addr, u8 val)
{
cs->writeisac(cs, addr, val);
}
static inline void
isac_read_fifo(struct IsdnCardState *cs, u8 *p, int len)
{
return cs->readisacfifo(cs, p, len);
}
static inline void
isac_write_fifo(struct IsdnCardState *cs, u8 *p, int len)
{
return cs->writeisacfifo(cs, p, len);
}
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