Commit 4e6b788c authored by Daniel Vetter's avatar Daniel Vetter

drm/i915: Disable dp aux irq on g4x

Apparently it's broken in the exact same way as the gmbus irq. For
reference of the full story see

commit c12aba5a
Author: Jiri Kosina <jkosina@suse.cz>
Date:   Tue Mar 19 09:56:57 2013 +0100

    drm/i915: stop using GMBUS IRQs on Gen4 chips

The effect is that we have a storm of unclaimed interrupts on the
legacy irq line. If that one is used by a different device then the
kernel will complain and rather quickly kill the irq source. Which
breaks any device trying to actually use the legacy irq line.

This regression has been introduced

commit 4aeebd74
Author: Daniel Vetter <daniel.vetter@ffwll.ch>
Date:   Thu Oct 31 09:53:36 2013 +0100

    drm/i915: dp aux irq support for g4x/vlv

Note that disabling MSI works around the issue, but we can't do that
since apparently then the hw will miss interrupts. At least if
relevant comments in i915_irq.c are accurate.

v2: Cross-reference dp aux and gmbus gen4 comments.

v3: Consolidate harder into i915_drv.h as suggested by Chris.

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Jiri Kosina <jkosina@suse.cz>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reported-and-tested-by: default avatarJiri Kosina <jkosina@suse.cz>
Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent bdde5c6a
...@@ -1831,6 +1831,14 @@ struct drm_i915_file_private { ...@@ -1831,6 +1831,14 @@ struct drm_i915_file_private {
/* Early gen2 have a totally busted CS tlb and require pinned batches. */ /* Early gen2 have a totally busted CS tlb and require pinned batches. */
#define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev)) #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
/*
* dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
* even when in MSI mode. This results in spurious interrupt warnings if the
* legacy irq no. is shared with another device. The kernel then disables that
* interrupt source and so prevents the other device from working properly.
*/
#define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
#define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
/* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
* rows, which changed the alignment requirements and fence programming. * rows, which changed the alignment requirements and fence programming.
......
...@@ -404,7 +404,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp, ...@@ -404,7 +404,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
int i, ret, recv_bytes; int i, ret, recv_bytes;
uint32_t status; uint32_t status;
int try, precharge, clock = 0; int try, precharge, clock = 0;
bool has_aux_irq = true; bool has_aux_irq = HAS_AUX_IRQ(dev);
uint32_t timeout; uint32_t timeout;
/* dp aux is extremely sensitive to irq latency, hence request the /* dp aux is extremely sensitive to irq latency, hence request the
......
...@@ -258,13 +258,6 @@ intel_gpio_setup(struct intel_gmbus *bus, u32 pin) ...@@ -258,13 +258,6 @@ intel_gpio_setup(struct intel_gmbus *bus, u32 pin)
algo->data = bus; algo->data = bus;
} }
/*
* gmbus on gen4 seems to be able to generate legacy interrupts even when in MSI
* mode. This results in spurious interrupt warnings if the legacy irq no. is
* shared with another device. The kernel then disables that interrupt source
* and so prevents the other device from working properly.
*/
#define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
static int static int
gmbus_wait_hw_status(struct drm_i915_private *dev_priv, gmbus_wait_hw_status(struct drm_i915_private *dev_priv,
u32 gmbus2_status, u32 gmbus2_status,
......
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