flexcan: disable bus error interrupts for the i.MX28
Due to a bug in most Flexcan cores, the bus error interrupt needs to be enabled. Otherwise we don't get any error warning or passive interrupts. This is _not_ necessary for the i.MX28 and this patch disables bus error interrupts if "berr-reporting" is not requested. This avoids bus error flooding, which might harm, especially on low-end systems. To handle such quirks of the Flexcan cores, a hardware feature flag has been introduced, also replacing the "hw_ver" variable. So far nobody could tell what Flexcan core version is available on what Freescale SOC, apart from the i.MX6Q and P1010, and which bugs or features are present on the various "hw_rev". CC: Hui Wang <jason77.wang@gmail.com> CC: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Wolfgang Grandegger <wg@grandegger.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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