drm/xe/pat: Use table-based programming of PAT settings

Provide per-platform tables of PAT values rather than per-platform
functions.  This will simplify the handling of unicast vs MCR registers
in the upcoming patches.
Reviewed-by: Nirmoy Das <nirmoy.das@intel.com>
Link: https://lore.kernel.org/r/20230324210415.2434992-3-matthew.d.roper@intel.comSigned-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

drivers/gpu/drm/xe/xe_pat.c

@@ -17,34 +17,27 @@
 #define GEN8_PPAT_UC			(0<<0)
 #define GEN12_PPAT_CLOS(x)              ((x)<<2)
 
-static void tgl_setup_private_ppat(struct xe_gt *gt)
-{
-	/* TGL doesn't support LLC or AGE settings */
-	xe_mmio_write32(gt, GEN12_PAT_INDEX(0).reg, GEN8_PPAT_WB);
-	xe_mmio_write32(gt, GEN12_PAT_INDEX(1).reg, GEN8_PPAT_WC);
-	xe_mmio_write32(gt, GEN12_PAT_INDEX(2).reg, GEN8_PPAT_WT);
-	xe_mmio_write32(gt, GEN12_PAT_INDEX(3).reg, GEN8_PPAT_UC);
-	xe_mmio_write32(gt, GEN12_PAT_INDEX(4).reg, GEN8_PPAT_WB);
-	xe_mmio_write32(gt, GEN12_PAT_INDEX(5).reg, GEN8_PPAT_WB);
-	xe_mmio_write32(gt, GEN12_PAT_INDEX(6).reg, GEN8_PPAT_WB);
-	xe_mmio_write32(gt, GEN12_PAT_INDEX(7).reg, GEN8_PPAT_WB);
-}
+const u32 tgl_pat_table[] = {
+	[0] = GEN8_PPAT_WB,
+	[1] = GEN8_PPAT_WC,
+	[2] = GEN8_PPAT_WT,
+	[3] = GEN8_PPAT_UC,
+	[4] = GEN8_PPAT_WB,
+	[5] = GEN8_PPAT_WB,
+	[6] = GEN8_PPAT_WB,
+	[7] = GEN8_PPAT_WB,
+};
 
-static void pvc_setup_private_ppat(struct xe_gt *gt)
-{
-	xe_mmio_write32(gt, GEN12_PAT_INDEX(0).reg, GEN8_PPAT_UC);
-	xe_mmio_write32(gt, GEN12_PAT_INDEX(1).reg, GEN8_PPAT_WC);
-	xe_mmio_write32(gt, GEN12_PAT_INDEX(2).reg, GEN8_PPAT_WT);
-	xe_mmio_write32(gt, GEN12_PAT_INDEX(3).reg, GEN8_PPAT_WB);
-	xe_mmio_write32(gt, GEN12_PAT_INDEX(4).reg,
-			GEN12_PPAT_CLOS(1) | GEN8_PPAT_WT);
-	xe_mmio_write32(gt, GEN12_PAT_INDEX(5).reg,
-			GEN12_PPAT_CLOS(1) | GEN8_PPAT_WB);
-	xe_mmio_write32(gt, GEN12_PAT_INDEX(6).reg,
-			GEN12_PPAT_CLOS(2) | GEN8_PPAT_WT);
-	xe_mmio_write32(gt, GEN12_PAT_INDEX(7).reg,
-			GEN12_PPAT_CLOS(2) | GEN8_PPAT_WB);
-}
+const u32 pvc_pat_table[] = {
+	[0] = GEN8_PPAT_UC,
+	[1] = GEN8_PPAT_WC,
+	[2] = GEN8_PPAT_WT,
+	[3] = GEN8_PPAT_WB,
+	[4] = GEN12_PPAT_CLOS(1) | GEN8_PPAT_WT,
+	[5] = GEN12_PPAT_CLOS(1) | GEN8_PPAT_WB,
+	[6] = GEN12_PPAT_CLOS(2) | GEN8_PPAT_WT,
+	[7] = GEN12_PPAT_CLOS(2) | GEN8_PPAT_WB,
+};
 
 #define MTL_PPAT_L4_CACHE_POLICY_MASK   REG_GENMASK(3, 2)
 #define MTL_PAT_INDEX_COH_MODE_MASK     REG_GENMASK(1, 0)
@@ -55,27 +48,27 @@ static void pvc_setup_private_ppat(struct xe_gt *gt)
 #define MTL_2_COH_1W    REG_FIELD_PREP(MTL_PAT_INDEX_COH_MODE_MASK, 2)
 #define MTL_0_COH_NON   REG_FIELD_PREP(MTL_PAT_INDEX_COH_MODE_MASK, 0)
 
-static void mtl_setup_private_ppat(struct xe_gt *gt)
-{
-	xe_mmio_write32(gt, GEN12_PAT_INDEX(0).reg, MTL_PPAT_0_WB);
-	xe_mmio_write32(gt, GEN12_PAT_INDEX(1).reg,
-			MTL_PPAT_1_WT | MTL_2_COH_1W);
-	xe_mmio_write32(gt, GEN12_PAT_INDEX(2).reg,
-			MTL_PPAT_3_UC | MTL_2_COH_1W);
-	xe_mmio_write32(gt, GEN12_PAT_INDEX(3).reg,
-			MTL_PPAT_0_WB | MTL_2_COH_1W);
-	xe_mmio_write32(gt, GEN12_PAT_INDEX(4).reg,
-			MTL_PPAT_0_WB | MTL_3_COH_2W);
-}
+const u32 mtl_pat_table[] = {
+	[0] = MTL_PPAT_0_WB,
+	[1] = MTL_PPAT_1_WT | MTL_2_COH_1W,
+	[2] = MTL_PPAT_3_UC | MTL_2_COH_1W,
+	[3] = MTL_PPAT_0_WB | MTL_2_COH_1W,
+	[4] = MTL_PPAT_0_WB | MTL_3_COH_2W,
+};
+
+#define PROGRAM_PAT_UNICAST(gt, table) do { \
+	for (int i = 0; i < ARRAY_SIZE(table); i++) \
+		xe_mmio_write32(gt, GEN12_PAT_INDEX(i).reg, table[i]); \
+} while (0)
 
 void xe_pat_init(struct xe_gt *gt)
 {
 	struct xe_device *xe = gt_to_xe(gt);
 
 	if (xe->info.platform == XE_METEORLAKE)
-		mtl_setup_private_ppat(gt);
+		PROGRAM_PAT_UNICAST(gt, mtl_pat_table);
 	else if (xe->info.platform == XE_PVC)
-		pvc_setup_private_ppat(gt);
+		PROGRAM_PAT_UNICAST(gt, pvc_pat_table);
 	else
-		tgl_setup_private_ppat(gt);
+		PROGRAM_PAT_UNICAST(gt, tgl_pat_table);
 }