drm/amd/display: Roll core_stream into dc_stream

Signed-off-by: Leo (Sunpeng) Li <sunpeng.li@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

@@ -1401,7 +1401,7 @@ static int amdgpu_notify_freesync(struct drm_device *dev, void *data,
 	num_streams = dc_get_current_stream_count(adev->dm.dc);
 
 	for (i = 0; i < num_streams; i++) {
-		const struct dc_stream *stream;
+		struct dc_stream *stream;
 		stream = dc_get_stream_at_index(adev->dm.dc, i);
 
 		mod_freesync_update_state(adev->dm.freesync_module,

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.c

@@ -2196,7 +2196,7 @@ static bool is_scaling_state_different(
 static void remove_stream(
 		struct amdgpu_device *adev,
 		struct amdgpu_crtc *acrtc,
-		const struct dc_stream *stream)
+		struct dc_stream *stream)
 {
 	/* this is the update mode case */
 	if (adev->dm.freesync_module)
@@ -2351,7 +2351,7 @@ static void amdgpu_dm_commit_surfaces(struct drm_atomic_state *state,
 	uint32_t i;
 	struct drm_plane *plane;
 	struct drm_plane_state *old_plane_state;
-	const struct dc_stream *dc_stream_attach;
+	struct dc_stream *dc_stream_attach;
 	struct dc_surface *dc_surfaces_constructed[MAX_SURFACES];
 	struct amdgpu_crtc *acrtc_attach = to_amdgpu_crtc(pcrtc);
 	struct dm_crtc_state *acrtc_state = to_dm_crtc_state(pcrtc->state);
@@ -2487,7 +2487,7 @@ void amdgpu_dm_atomic_commit_tail(
 	struct drm_crtc *crtc, *pcrtc;
 	struct drm_crtc_state *old_crtc_state;
 	struct amdgpu_crtc *new_crtcs[MAX_STREAMS];
-	const struct dc_stream *new_stream;
+	struct dc_stream *new_stream = NULL;
 	unsigned long flags;
 	bool wait_for_vblank = true;
 	struct drm_connector *connector;
@@ -2822,8 +2822,8 @@ static uint32_t add_val_sets_surface(
 static uint32_t update_in_val_sets_stream(
 	struct dc_validation_set *val_sets,
 	uint32_t set_count,
-	const struct dc_stream *old_stream,
-	const struct dc_stream *new_stream,
+	struct dc_stream *old_stream,
+	struct dc_stream *new_stream,
 	struct drm_crtc *crtc)
 {
 	uint32_t i = 0;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_types.h

@@ -45,7 +45,7 @@ struct dm_plane_state {
 
 struct dm_crtc_state {
 	struct drm_crtc_state base;
-	const struct dc_stream *stream;
+	struct dc_stream *stream;
 };
 
 #define to_dm_crtc_state(x)    container_of(x, struct dm_crtc_state, base)

drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c

@@ -2610,9 +2610,9 @@ static void populate_initial_data(
 
 		data->fbc_en[num_displays + 4] = false;
 		data->lpt_en[num_displays + 4] = false;
-		data->h_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->public.timing.h_total);
-		data->v_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->public.timing.v_total);
-		data->pixel_rate[num_displays + 4] = bw_frc_to_fixed(pipe[i].stream->public.timing.pix_clk_khz, 1000);
+		data->h_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.h_total);
+		data->v_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.v_total);
+		data->pixel_rate[num_displays + 4] = bw_frc_to_fixed(pipe[i].stream->timing.pix_clk_khz, 1000);
 		data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].scl_data.viewport.width);
 		data->pitch_in_pixels[num_displays + 4] = data->src_width[num_displays + 4];
 		data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].scl_data.viewport.height);
@@ -2707,9 +2707,9 @@ static void populate_initial_data(
 
 		data->fbc_en[num_displays + 4] = false;
 		data->lpt_en[num_displays + 4] = false;
-		data->h_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->public.timing.h_total);
-		data->v_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->public.timing.v_total);
-		data->pixel_rate[num_displays + 4] = bw_frc_to_fixed(pipe[i].stream->public.timing.pix_clk_khz, 1000);
+		data->h_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.h_total);
+		data->v_total[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.v_total);
+		data->pixel_rate[num_displays + 4] = bw_frc_to_fixed(pipe[i].stream->timing.pix_clk_khz, 1000);
 		if (pipe[i].surface) {
 			data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].scl_data.viewport.width);
 			data->pitch_in_pixels[num_displays + 4] = data->src_width[num_displays + 4];
@@ -2759,9 +2759,9 @@ static void populate_initial_data(
 				break;
 			}
 		} else {
-			data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->public.timing.h_addressable);
+			data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.h_addressable);
 			data->pitch_in_pixels[num_displays + 4] = data->src_width[num_displays + 4];
-			data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->public.timing.v_addressable);
+			data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].stream->timing.v_addressable);
 			data->h_taps[num_displays + 4] = bw_int_to_fixed(1);
 			data->v_taps[num_displays + 4] = bw_int_to_fixed(1);
 			data->h_scale_ratio[num_displays + 4] = bw_int_to_fixed(1);

drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c

@@ -365,7 +365,7 @@ static void pipe_ctx_to_e2e_pipe_params (
 	}
 
 
-	input->dest.vactive        = pipe->stream->public.timing.v_addressable;
+	input->dest.vactive        = pipe->stream->timing.v_addressable;
 
 	input->dest.recout_width   = pipe->scl_data.recout.width;
 	input->dest.recout_height  = pipe->scl_data.recout.height;
@@ -373,24 +373,24 @@ static void pipe_ctx_to_e2e_pipe_params (
 	input->dest.full_recout_width   = pipe->scl_data.recout.width;
 	input->dest.full_recout_height  = pipe->scl_data.recout.height;
 
-	input->dest.htotal         = pipe->stream->public.timing.h_total;
-	input->dest.hblank_start   = input->dest.htotal - pipe->stream->public.timing.h_front_porch;
+	input->dest.htotal         = pipe->stream->timing.h_total;
+	input->dest.hblank_start   = input->dest.htotal - pipe->stream->timing.h_front_porch;
 	input->dest.hblank_end     = input->dest.hblank_start
-			- pipe->stream->public.timing.h_addressable
-			- pipe->stream->public.timing.h_border_left
-			- pipe->stream->public.timing.h_border_right;
+			- pipe->stream->timing.h_addressable
+			- pipe->stream->timing.h_border_left
+			- pipe->stream->timing.h_border_right;
 
-	input->dest.vtotal         = pipe->stream->public.timing.v_total;
-	input->dest.vblank_start   = input->dest.vtotal - pipe->stream->public.timing.v_front_porch;
+	input->dest.vtotal         = pipe->stream->timing.v_total;
+	input->dest.vblank_start   = input->dest.vtotal - pipe->stream->timing.v_front_porch;
 	input->dest.vblank_end     = input->dest.vblank_start
-			- pipe->stream->public.timing.v_addressable
-			- pipe->stream->public.timing.v_border_bottom
-			- pipe->stream->public.timing.v_border_top;
-
-	input->dest.vsync_plus_back_porch = pipe->stream->public.timing.v_total
-			- pipe->stream->public.timing.v_addressable
-			- pipe->stream->public.timing.v_front_porch;
-	input->dest.pixel_rate_mhz = pipe->stream->public.timing.pix_clk_khz/1000.0;
+			- pipe->stream->timing.v_addressable
+			- pipe->stream->timing.v_border_bottom
+			- pipe->stream->timing.v_border_top;
+
+	input->dest.vsync_plus_back_porch = pipe->stream->timing.v_total
+			- pipe->stream->timing.v_addressable
+			- pipe->stream->timing.v_front_porch;
+	input->dest.pixel_rate_mhz = pipe->stream->timing.pix_clk_khz/1000.0;
 	input->dest.vstartup_start = pipe->pipe_dlg_param.vstartup_start;
 	input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset;
 	input->dest.vupdate_offset = pipe->pipe_dlg_param.vupdate_offset;
@@ -851,14 +851,14 @@ bool dcn_validate_bandwidth(
 		v->underscan_output[input_idx] = false; /* taken care of in recout already*/
 		v->interlace_output[input_idx] = false;
 
-		v->htotal[input_idx] = pipe->stream->public.timing.h_total;
-		v->vtotal[input_idx] = pipe->stream->public.timing.v_total;
-		v->v_sync_plus_back_porch[input_idx] = pipe->stream->public.timing.v_total
-				- pipe->stream->public.timing.v_addressable
-				- pipe->stream->public.timing.v_front_porch;
-		v->vactive[input_idx] = pipe->stream->public.timing.v_addressable;
-		v->pixel_clock[input_idx] = pipe->stream->public.timing.pix_clk_khz / 1000.0f;
-		if (pipe->stream->public.timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
+		v->htotal[input_idx] = pipe->stream->timing.h_total;
+		v->vtotal[input_idx] = pipe->stream->timing.v_total;
+		v->v_sync_plus_back_porch[input_idx] = pipe->stream->timing.v_total
+				- pipe->stream->timing.v_addressable
+				- pipe->stream->timing.v_front_porch;
+		v->vactive[input_idx] = pipe->stream->timing.v_addressable;
+		v->pixel_clock[input_idx] = pipe->stream->timing.pix_clk_khz / 1000.0f;
+		if (pipe->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
 			v->pixel_clock[input_idx] /= 2;
 
 
@@ -867,10 +867,10 @@ bool dcn_validate_bandwidth(
 			v->source_pixel_format[input_idx] = dcn_bw_rgb_sub_32;
 			v->source_surface_mode[input_idx] = dcn_bw_sw_4_kb_s;
 			v->lb_bit_per_pixel[input_idx] = 30;
-			v->viewport_width[input_idx] = pipe->stream->public.timing.h_addressable;
-			v->viewport_height[input_idx] = pipe->stream->public.timing.v_addressable;
-			v->scaler_rec_out_width[input_idx] = pipe->stream->public.timing.h_addressable;
-			v->scaler_recout_height[input_idx] = pipe->stream->public.timing.v_addressable;
+			v->viewport_width[input_idx] = pipe->stream->timing.h_addressable;
+			v->viewport_height[input_idx] = pipe->stream->timing.v_addressable;
+			v->scaler_rec_out_width[input_idx] = pipe->stream->timing.h_addressable;
+			v->scaler_recout_height[input_idx] = pipe->stream->timing.v_addressable;
 			v->override_hta_ps[input_idx] = 1;
 			v->override_vta_ps[input_idx] = 1;
 			v->override_hta_pschroma[input_idx] = 1;
@@ -995,22 +995,22 @@ bool dcn_validate_bandwidth(
 			pipe->pipe_dlg_param.vready_offset = v->v_ready_offset[input_idx];
 			pipe->pipe_dlg_param.vstartup_start = v->v_startup[input_idx];
 
-			pipe->pipe_dlg_param.htotal = pipe->stream->public.timing.h_total;
-			pipe->pipe_dlg_param.vtotal = pipe->stream->public.timing.v_total;
-			vesa_sync_start = pipe->stream->public.timing.v_addressable +
-						pipe->stream->public.timing.v_border_bottom +
-						pipe->stream->public.timing.v_front_porch;
+			pipe->pipe_dlg_param.htotal = pipe->stream->timing.h_total;
+			pipe->pipe_dlg_param.vtotal = pipe->stream->timing.v_total;
+			vesa_sync_start = pipe->stream->timing.v_addressable +
+						pipe->stream->timing.v_border_bottom +
+						pipe->stream->timing.v_front_porch;
 
-			asic_blank_end = (pipe->stream->public.timing.v_total -
+			asic_blank_end = (pipe->stream->timing.v_total -
 						vesa_sync_start -
-						pipe->stream->public.timing.v_border_top)
-			* (pipe->stream->public.timing.flags.INTERLACE ? 1 : 0);
+						pipe->stream->timing.v_border_top)
+			* (pipe->stream->timing.flags.INTERLACE ? 1 : 0);
 
 			asic_blank_start = asic_blank_end +
-						(pipe->stream->public.timing.v_border_top +
-						pipe->stream->public.timing.v_addressable +
-						pipe->stream->public.timing.v_border_bottom)
-			* (pipe->stream->public.timing.flags.INTERLACE ? 1 : 0);
+						(pipe->stream->timing.v_border_top +
+						pipe->stream->timing.v_addressable +
+						pipe->stream->timing.v_border_bottom)
+			* (pipe->stream->timing.flags.INTERLACE ? 1 : 0);
 
 			pipe->pipe_dlg_param.vblank_start = asic_blank_start;
 			pipe->pipe_dlg_param.vblank_end = asic_blank_end;
@@ -1019,13 +1019,13 @@ bool dcn_validate_bandwidth(
 				struct pipe_ctx *hsplit_pipe = pipe->bottom_pipe;
 
 				if (v->dpp_per_plane[input_idx] == 2 ||
-					((pipe->stream->public.view_format ==
+					((pipe->stream->view_format ==
 					  VIEW_3D_FORMAT_SIDE_BY_SIDE ||
-					  pipe->stream->public.view_format ==
+					  pipe->stream->view_format ==
 					  VIEW_3D_FORMAT_TOP_AND_BOTTOM) &&
-					(pipe->stream->public.timing.timing_3d_format ==
+					(pipe->stream->timing.timing_3d_format ==
 					 TIMING_3D_FORMAT_TOP_AND_BOTTOM ||
-					 pipe->stream->public.timing.timing_3d_format ==
+					 pipe->stream->timing.timing_3d_format ==
 					 TIMING_3D_FORMAT_SIDE_BY_SIDE))) {
 					if (hsplit_pipe && hsplit_pipe->surface == pipe->surface) {
 						/* update previously split pipe */
@@ -1034,8 +1034,8 @@ bool dcn_validate_bandwidth(
 						hsplit_pipe->pipe_dlg_param.vready_offset = v->v_ready_offset[input_idx];
 						hsplit_pipe->pipe_dlg_param.vstartup_start = v->v_startup[input_idx];
 
-						hsplit_pipe->pipe_dlg_param.htotal = pipe->stream->public.timing.h_total;
-						hsplit_pipe->pipe_dlg_param.vtotal = pipe->stream->public.timing.v_total;
+						hsplit_pipe->pipe_dlg_param.htotal = pipe->stream->timing.h_total;
+						hsplit_pipe->pipe_dlg_param.vtotal = pipe->stream->timing.v_total;
 						hsplit_pipe->pipe_dlg_param.vblank_start = pipe->pipe_dlg_param.vblank_start;
 						hsplit_pipe->pipe_dlg_param.vblank_end = pipe->pipe_dlg_param.vblank_end;
 					} else {

drivers/gpu/drm/amd/display/dc/core/dc_debug.c

@@ -321,8 +321,8 @@ void context_timing_trace(
 
 		TIMING_TRACE("OTG_%d   H_tot:%d  V_tot:%d   H_pos:%d  V_pos:%d\n",
 				pipe_ctx->tg->inst,
-				pipe_ctx->stream->public.timing.h_total,
-				pipe_ctx->stream->public.timing.v_total,
+				pipe_ctx->stream->timing.h_total,
+				pipe_ctx->stream->timing.v_total,
 				h_pos[i], v_pos[i]);
 	}
 }

drivers/gpu/drm/amd/display/dc/core/dc_link.c

@@ -1143,7 +1143,7 @@ static void dpcd_configure_panel_mode(
 
 static void enable_stream_features(struct pipe_ctx *pipe_ctx)
 {
-	struct core_stream *stream = pipe_ctx->stream;
+	struct dc_stream *stream = pipe_ctx->stream;
 	struct dc_link *link = stream->sink->link;
 	union down_spread_ctrl downspread;
 
@@ -1151,7 +1151,7 @@ static void enable_stream_features(struct pipe_ctx *pipe_ctx)
 			&downspread.raw, sizeof(downspread));
 
 	downspread.bits.IGNORE_MSA_TIMING_PARAM =
-			(stream->public.ignore_msa_timing_param) ? 1 : 0;
+			(stream->ignore_msa_timing_param) ? 1 : 0;
 
 	core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL,
 			&downspread.raw, sizeof(downspread));
@@ -1159,7 +1159,7 @@ static void enable_stream_features(struct pipe_ctx *pipe_ctx)
 
 static enum dc_status enable_link_dp(struct pipe_ctx *pipe_ctx)
 {
-	struct core_stream *stream = pipe_ctx->stream;
+	struct dc_stream *stream = pipe_ctx->stream;
 	enum dc_status status;
 	bool skip_video_pattern;
 	struct dc_link *link = stream->sink->link;
@@ -1250,7 +1250,7 @@ static enum dc_status enable_link_dp_mst(struct pipe_ctx *pipe_ctx)
 
 static void enable_link_hdmi(struct pipe_ctx *pipe_ctx)
 {
-	struct core_stream *stream = pipe_ctx->stream;
+	struct dc_stream *stream = pipe_ctx->stream;
 	struct dc_link *link = stream->sink->link;
 	enum dc_color_depth display_color_depth;
 
@@ -1258,13 +1258,13 @@ static void enable_link_hdmi(struct pipe_ctx *pipe_ctx)
 		dal_ddc_service_write_scdc_data(
 			stream->sink->link->ddc,
 			stream->phy_pix_clk,
-			stream->public.timing.flags.LTE_340MCSC_SCRAMBLE);
+			stream->timing.flags.LTE_340MCSC_SCRAMBLE);
 
 	memset(&stream->sink->link->cur_link_settings, 0,
 			sizeof(struct dc_link_settings));
 
-	display_color_depth = stream->public.timing.display_color_depth;
-	if (stream->public.timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
+	display_color_depth = stream->timing.display_color_depth;
+	if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
 		display_color_depth = COLOR_DEPTH_888;
 
 	link->link_enc->funcs->enable_tmds_output(
@@ -1341,7 +1341,7 @@ static void disable_link(struct dc_link *link, enum signal_type signal)
 }
 
 enum dc_status dc_link_validate_mode_timing(
-		const struct core_stream *stream,
+		const struct dc_stream *stream,
 		struct dc_link *link,
 		const struct dc_crtc_timing *timing)
 {
@@ -1377,7 +1377,6 @@ bool dc_link_set_backlight_level(const struct dc_link *link, uint32_t level,
 		uint32_t frame_ramp, const struct dc_stream *stream)
 {
 	struct core_dc *core_dc = DC_TO_CORE(link->ctx->dc);
-	struct core_stream *core_stream = NULL;
 	struct abm *abm = core_dc->res_pool->abm;
 	unsigned int controller_id = 0;
 	int i;
@@ -1390,11 +1389,10 @@ bool dc_link_set_backlight_level(const struct dc_link *link, uint32_t level,
 
 	if (dc_is_embedded_signal(link->connector_signal)) {
 		if (stream != NULL) {
-			core_stream = DC_STREAM_TO_CORE(stream);
 			for (i = 0; i < MAX_PIPES; i++) {
 				if (core_dc->current_context->res_ctx.
 						pipe_ctx[i].stream
-						== core_stream)
+						== stream)
 					/* DMCU -1 for all controller id values,
 					 * therefore +1 here
 					 */
@@ -1457,7 +1455,6 @@ bool dc_link_setup_psr(struct dc_link *link,
 {
 	struct core_dc *core_dc = DC_TO_CORE(link->ctx->dc);
 	struct dmcu *dmcu = core_dc->res_pool->dmcu;
-	struct core_stream *core_stream = DC_STREAM_TO_CORE(stream);
 	int i;
 
 	psr_context->controllerId = CONTROLLER_ID_UNDEFINED;
@@ -1501,7 +1498,7 @@ bool dc_link_setup_psr(struct dc_link *link,
 
 		for (i = 0; i < MAX_PIPES; i++) {
 			if (core_dc->current_context->res_ctx.pipe_ctx[i].stream
-					== core_stream) {
+					== stream) {
 				/* dmcu -1 for all controller id values,
 				 * therefore +1 here
 				 */
@@ -1590,7 +1587,7 @@ void core_link_resume(struct dc_link *link)
 		program_hpd_filter(link);
 }
 
-static struct fixed31_32 get_pbn_per_slot(struct core_stream *stream)
+static struct fixed31_32 get_pbn_per_slot(struct dc_stream *stream)
 {
 	struct dc_link_settings *link_settings =
 			&stream->sink->link->cur_link_settings;
@@ -1699,7 +1696,7 @@ static void update_mst_stream_alloc_table(
  */
 static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx)
 {
-	struct core_stream *stream = pipe_ctx->stream;
+	struct dc_stream *stream = pipe_ctx->stream;
 	struct dc_link *link = stream->sink->link;
 	struct link_encoder *link_encoder = link->link_enc;
 	struct stream_encoder *stream_encoder = pipe_ctx->stream_enc;
@@ -1717,7 +1714,7 @@ static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx)
 	/* get calculate VC payload for stream: stream_alloc */
 	if (dm_helpers_dp_mst_write_payload_allocation_table(
 		stream->ctx,
-		&stream->public,
+		stream,
 		&proposed_table,
 		true)) {
 		update_mst_stream_alloc_table(
@@ -1759,11 +1756,11 @@ static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx)
 	/* send down message */
 	dm_helpers_dp_mst_poll_for_allocation_change_trigger(
 			stream->ctx,
-			&stream->public);
+			stream);
 
 	dm_helpers_dp_mst_send_payload_allocation(
 			stream->ctx,
-			&stream->public,
+			stream,
 			true);
 
 	/* slot X.Y for only current stream */
@@ -1781,7 +1778,7 @@ static enum dc_status allocate_mst_payload(struct pipe_ctx *pipe_ctx)
 
 static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)
 {
-	struct core_stream *stream = pipe_ctx->stream;
+	struct dc_stream *stream = pipe_ctx->stream;
 	struct dc_link *link = stream->sink->link;
 	struct link_encoder *link_encoder = link->link_enc;
 	struct stream_encoder *stream_encoder = pipe_ctx->stream_enc;
@@ -1806,7 +1803,7 @@ static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)
 	if (mst_mode) {
 		if (dm_helpers_dp_mst_write_payload_allocation_table(
 				stream->ctx,
-				&stream->public,
+				stream,
 				&proposed_table,
 				false)) {
 
@@ -1848,11 +1845,11 @@ static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)
 	if (mst_mode) {
 		dm_helpers_dp_mst_poll_for_allocation_change_trigger(
 			stream->ctx,
-			&stream->public);
+			stream);
 
 		dm_helpers_dp_mst_send_payload_allocation(
 			stream->ctx,
-			&stream->public,
+			stream,
 			false);
 	}
 

drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c

@@ -1434,7 +1434,7 @@ bool dp_validate_mode_timing(
 		return false;
 }
 
-void decide_link_settings(struct core_stream *stream,
+void decide_link_settings(struct dc_stream *stream,
 	struct dc_link_settings *link_setting)
 {
 
@@ -1446,8 +1446,7 @@ void decide_link_settings(struct core_stream *stream,
 	uint32_t req_bw;
 	uint32_t link_bw;
 
-	req_bw = bandwidth_in_kbps_from_timing(
-			&stream->public.timing);
+	req_bw = bandwidth_in_kbps_from_timing(&stream->timing);
 
 	link = stream->sink->link;
 
@@ -2327,7 +2326,7 @@ static void set_crtc_test_pattern(struct dc_link *link,
 {
 	enum controller_dp_test_pattern controller_test_pattern;
 	enum dc_color_depth color_depth = pipe_ctx->
-		stream->public.timing.display_color_depth;
+		stream->timing.display_color_depth;
 	struct bit_depth_reduction_params params;
 
 	memset(&params, 0, sizeof(params));

drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c

@@ -78,7 +78,7 @@ void dp_enable_link_phy(
 					pipes[i].clock_source->id != CLOCK_SOURCE_ID_DP_DTO) {
 				pipes[i].clock_source = dp_cs;
 				pipes[i].pix_clk_params.requested_pix_clk =
-						pipes[i].stream->public.timing.pix_clk_khz;
+						pipes[i].stream->timing.pix_clk_khz;
 				pipes[i].clock_source->funcs->program_pix_clk(
 							pipes[i].clock_source,
 							&pipes[i].pix_clk_params,

drivers/gpu/drm/amd/display/dc/dc.h

@@ -32,6 +32,7 @@
 #include "gpio_types.h"
 #include "link_service_types.h"
 #include "grph_object_ctrl_defs.h"
+#include <inc/hw/opp.h>
 
 #define MAX_SURFACES 3
 #define MAX_STREAMS 6
@@ -106,12 +107,12 @@ struct dc_cap_funcs {
 
 struct dc_stream_funcs {
 	bool (*adjust_vmin_vmax)(struct dc *dc,
-			const struct dc_stream **stream,
+			struct dc_stream **stream,
 			int num_streams,
 			int vmin,
 			int vmax);
 	bool (*get_crtc_position)(struct dc *dc,
-			const struct dc_stream **stream,
+			struct dc_stream **stream,
 			int num_streams,
 			unsigned int *v_pos,
 			unsigned int *nom_v_pos);
@@ -120,14 +121,14 @@ struct dc_stream_funcs {
 			const struct dc_stream *stream);
 
 	bool (*program_csc_matrix)(struct dc *dc,
-			const struct dc_stream *stream);
+			struct dc_stream *stream);
 
 	void (*set_static_screen_events)(struct dc *dc,
-			const struct dc_stream **stream,
+			struct dc_stream **stream,
 			int num_streams,
 			const struct dc_static_screen_events *events);
 
-	void (*set_dither_option)(const struct dc_stream *stream,
+	void (*set_dither_option)(struct dc_stream *stream,
 			enum dc_dither_option option);
 };
 
@@ -428,7 +429,7 @@ bool dc_commit_surfaces_to_stream(
 		struct dc *dc,
 		struct dc_surface **dc_surfaces,
 		uint8_t surface_count,
-		const struct dc_stream *stream);
+		struct dc_stream *stream);
 
 bool dc_post_update_surfaces_to_stream(
 		struct dc *dc);
@@ -468,6 +469,18 @@ enum surface_update_type {
 /*******************************************************************************
  * Stream Interfaces
  ******************************************************************************/
+
+struct dc_stream_status {
+	int primary_otg_inst;
+	int surface_count;
+	struct dc_surface *surfaces[MAX_SURFACE_NUM];
+
+	/*
+	 * link this stream passes through
+	 */
+	struct dc_link *link;
+};
+
 struct dc_stream {
 	struct dc_sink *sink;
 	struct dc_crtc_timing timing;
@@ -495,6 +508,21 @@ struct dc_stream {
 	/* TODO: ABM info (DMCU) */
 	/* TODO: PSR info */
 	/* TODO: CEA VIC */
+
+	/* from core_stream struct */
+	struct dc_context *ctx;
+
+	/* used by DCP and FMT */
+	struct bit_depth_reduction_params bit_depth_params;
+	struct clamping_and_pixel_encoding_params clamping;
+
+	int phy_pix_clk;
+	enum signal_type signal;
+
+	struct dc_stream_status status;
+
+	/* from stream struct */
+	int ref_count;
 };
 
 struct dc_stream_update {
@@ -521,7 +549,7 @@ struct dc_stream_update {
 
 void dc_update_surfaces_and_stream(struct dc *dc,
 		struct dc_surface_update *surface_updates, int surface_count,
-		const struct dc_stream *dc_stream,
+		struct dc_stream *dc_stream,
 		struct dc_stream_update *stream_update);
 
 /*
@@ -554,12 +582,12 @@ bool dc_stream_get_scanoutpos(const struct dc_stream *stream,
  * Structure to store surface/stream associations for validation
  */
 struct dc_validation_set {
-	const struct dc_stream *stream;
+	struct dc_stream *stream;
 	struct dc_surface *surfaces[MAX_SURFACES];
 	uint8_t surface_count;
 };
 
-bool dc_validate_stream(const struct dc *dc, const struct dc_stream *stream);
+bool dc_validate_stream(const struct dc *dc, struct dc_stream *stream);
 
 /*
  * This function takes a set of resources and checks that they are cofunctional.
@@ -587,7 +615,7 @@ bool dc_validate_resources(
 
 bool dc_validate_guaranteed(
 		const struct dc *dc,
-		const struct dc_stream *stream);
+		struct dc_stream *stream);
 
 void dc_resource_validate_ctx_copy_construct(
 		const struct validate_context *src_ctx,
@@ -616,7 +644,7 @@ bool dc_commit_context(struct dc *dc, struct validate_context *context);
  */
 bool dc_commit_streams(
 		struct dc *dc,
-		const struct dc_stream *streams[],
+		struct dc_stream *streams[],
 		uint8_t stream_count);
 /*
  * Enable stereo when commit_streams is not required,
@@ -625,7 +653,7 @@ bool dc_commit_streams(
 bool dc_enable_stereo(
 	struct dc *dc,
 	struct validate_context *context,
-	const struct dc_stream *streams[],
+	struct dc_stream *streams[],
 	uint8_t stream_count);
 
 /**
@@ -633,22 +661,11 @@ bool dc_enable_stereo(
  */
 struct dc_stream *dc_create_stream_for_sink(struct dc_sink *dc_sink);
 
-void dc_stream_retain(const struct dc_stream *dc_stream);
-void dc_stream_release(const struct dc_stream *dc_stream);
-
-struct dc_stream_status {
-	int primary_otg_inst;
-	int surface_count;
-	struct dc_surface *surfaces[MAX_SURFACE_NUM];
-
-	/*
-	 * link this stream passes through
-	 */
-	struct dc_link *link;
-};
+void dc_stream_retain(struct dc_stream *dc_stream);
+void dc_stream_release(struct dc_stream *dc_stream);
 
 struct dc_stream_status *dc_stream_get_status(
-	const struct dc_stream *dc_stream);
+	struct dc_stream *dc_stream);
 
 enum surface_update_type dc_check_update_surfaces_for_stream(
 		struct dc *dc,
@@ -915,7 +932,7 @@ bool dc_stream_set_cursor_attributes(
 	const struct dc_cursor_attributes *attributes);
 
 bool dc_stream_set_cursor_position(
-	const struct dc_stream *stream,
+	struct dc_stream *stream,
 	const struct dc_cursor_position *position);
 
 /* Newer interfaces  */

drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.c

@@ -1009,7 +1009,7 @@ bool dce110_link_encoder_construct(
 
 bool dce110_link_encoder_validate_output_with_stream(
 	struct link_encoder *enc,
-	const struct core_stream *stream)
+	const struct dc_stream *stream)
 {
 	struct dce110_link_encoder *enc110 = TO_DCE110_LINK_ENC(enc);
 	bool is_valid;
@@ -1021,22 +1021,22 @@ bool dce110_link_encoder_validate_output_with_stream(
 			enc110,
 			stream->sink->link->connector_signal,
 			stream->signal,
-			&stream->public.timing);
+			&stream->timing);
 	break;
 	case SIGNAL_TYPE_HDMI_TYPE_A:
 		is_valid = dce110_link_encoder_validate_hdmi_output(
 				enc110,
-				&stream->public.timing,
+				&stream->timing,
 				stream->phy_pix_clk);
 	break;
 	case SIGNAL_TYPE_DISPLAY_PORT:
 	case SIGNAL_TYPE_DISPLAY_PORT_MST:
 		is_valid = dce110_link_encoder_validate_dp_output(
-					enc110, &stream->public.timing);
+					enc110, &stream->timing);
 	break;
 	case SIGNAL_TYPE_EDP:
 		is_valid =
-			(stream->public.timing.
+			(stream->timing.
 				pixel_encoding == PIXEL_ENCODING_RGB) ? true : false;
 	break;
 	case SIGNAL_TYPE_VIRTUAL:

drivers/gpu/drm/amd/display/dc/dce/dce_link_encoder.h

@@ -199,7 +199,7 @@ bool dce110_link_encoder_validate_wireless_output(
 
 bool dce110_link_encoder_validate_output_with_stream(
 	struct link_encoder *enc,
-	const struct core_stream *stream);
+	const struct dc_stream *stream);
 
 /****************** HW programming ************************/
 

drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c

@@ -660,7 +660,7 @@ static enum dc_status build_mapped_resource(
 	uint8_t i, j;
 
 	for (i = 0; i < context->stream_count; i++) {
-		struct core_stream *stream = context->streams[i];
+		struct dc_stream *stream = context->streams[i];
 
 		if (old_context && resource_is_stream_unchanged(old_context, stream))
 			continue;
@@ -734,8 +734,8 @@ enum dc_status dce100_validate_with_context(
 		return DC_FAIL_SURFACE_VALIDATE;
 
 	for (i = 0; i < set_count; i++) {
-		context->streams[i] = DC_STREAM_TO_CORE(set[i].stream);
-		dc_stream_retain(&context->streams[i]->public);
+		context->streams[i] = set[i].stream;
+		dc_stream_retain(context->streams[i]);
 		context->stream_count++;
 	}
 
@@ -765,13 +765,13 @@ enum dc_status dce100_validate_with_context(
 
 enum dc_status dce100_validate_guaranteed(
 		const struct core_dc *dc,
-		const struct dc_stream *dc_stream,
+		struct dc_stream *dc_stream,
 		struct validate_context *context)
 {
 	enum dc_status result = DC_ERROR_UNEXPECTED;
 
-	context->streams[0] = DC_STREAM_TO_CORE(dc_stream);
-	dc_stream_retain(&context->streams[0]->public);
+	context->streams[0] = dc_stream;
+	dc_stream_retain(context->streams[0]);
 	context->stream_count++;
 
 	result = resource_map_pool_resources(dc, context, NULL);

drivers/gpu/drm/amd/display/dc/dce110/dce110_resource.c

@@ -718,13 +718,13 @@ static void get_pixel_clock_parameters(
 	const struct pipe_ctx *pipe_ctx,
 	struct pixel_clk_params *pixel_clk_params)
 {
-	const struct core_stream *stream = pipe_ctx->stream;
+	const struct dc_stream *stream = pipe_ctx->stream;
 
 	/*TODO: is this halved for YCbCr 420? in that case we might want to move
 	 * the pixel clock normalization for hdmi up to here instead of doing it
 	 * in pll_adjust_pix_clk
 	 */
-	pixel_clk_params->requested_pix_clk = stream->public.timing.pix_clk_khz;
+	pixel_clk_params->requested_pix_clk = stream->timing.pix_clk_khz;
 	pixel_clk_params->encoder_object_id = stream->sink->link->link_enc->id;
 	pixel_clk_params->signal_type = pipe_ctx->stream->signal;
 	pixel_clk_params->controller_id = pipe_ctx->pipe_idx + 1;
@@ -733,15 +733,15 @@ static void get_pixel_clock_parameters(
 						LINK_RATE_REF_FREQ_IN_KHZ;
 	pixel_clk_params->flags.ENABLE_SS = 0;
 	pixel_clk_params->color_depth =
-		stream->public.timing.display_color_depth;
+		stream->timing.display_color_depth;
 	pixel_clk_params->flags.DISPLAY_BLANKED = 1;
-	pixel_clk_params->flags.SUPPORT_YCBCR420 = (stream->public.timing.pixel_encoding ==
+	pixel_clk_params->flags.SUPPORT_YCBCR420 = (stream->timing.pixel_encoding ==
 			PIXEL_ENCODING_YCBCR420);
-	pixel_clk_params->pixel_encoding = stream->public.timing.pixel_encoding;
-	if (stream->public.timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) {
+	pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding;
+	if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422) {
 		pixel_clk_params->color_depth = COLOR_DEPTH_888;
 	}
-	if (stream->public.timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
+	if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
 		pixel_clk_params->requested_pix_clk  = pixel_clk_params->requested_pix_clk / 2;
 	}
 }
@@ -755,7 +755,7 @@ enum dc_status dce110_resource_build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
 		&pipe_ctx->pll_settings);
 	resource_build_bit_depth_reduction_params(pipe_ctx->stream,
 			&pipe_ctx->stream->bit_depth_params);
-	pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->public.timing.pixel_encoding;
+	pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;
 
 	return DC_OK;
 }
@@ -780,7 +780,7 @@ static enum dc_status build_mapped_resource(
 	uint8_t i, j;
 
 	for (i = 0; i < context->stream_count; i++) {
-		struct core_stream *stream = context->streams[i];
+		struct dc_stream *stream = context->streams[i];
 
 		if (old_context && resource_is_stream_unchanged(old_context, stream))
 			continue;
@@ -837,9 +837,9 @@ bool dce110_validate_bandwidth(
 		dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_VALIDATION,
 			"%s: %dx%d@%d Bandwidth validation failed!\n",
 			__func__,
-			context->streams[0]->public.timing.h_addressable,
-			context->streams[0]->public.timing.v_addressable,
-			context->streams[0]->public.timing.pix_clk_khz);
+			context->streams[0]->timing.h_addressable,
+			context->streams[0]->timing.v_addressable,
+			context->streams[0]->timing.pix_clk_khz);
 
 	if (memcmp(&dc->current_context->bw.dce,
 			&context->bw.dce, sizeof(context->bw.dce))) {
@@ -942,8 +942,8 @@ enum dc_status dce110_validate_with_context(
 		return DC_FAIL_SURFACE_VALIDATE;
 
 	for (i = 0; i < set_count; i++) {
-		context->streams[i] = DC_STREAM_TO_CORE(set[i].stream);
-		dc_stream_retain(&context->streams[i]->public);
+		context->streams[i] = set[i].stream;
+		dc_stream_retain(context->streams[i]);
 		context->stream_count++;
 	}
 
@@ -973,13 +973,13 @@ enum dc_status dce110_validate_with_context(
 
 enum dc_status dce110_validate_guaranteed(
 		const struct core_dc *dc,
-		const struct dc_stream *dc_stream,
+		struct dc_stream *dc_stream,
 		struct validate_context *context)
 {
 	enum dc_status result = DC_ERROR_UNEXPECTED;
 
-	context->streams[0] = DC_STREAM_TO_CORE(dc_stream);
-	dc_stream_retain(&context->streams[0]->public);
+	context->streams[0] = dc_stream;
+	dc_stream_retain(context->streams[0]);
 	context->stream_count++;
 
 	result = resource_map_pool_resources(dc, context, NULL);
@@ -1006,7 +1006,7 @@ enum dc_status dce110_validate_guaranteed(
 static struct pipe_ctx *dce110_acquire_underlay(
 		struct validate_context *context,
 		const struct resource_pool *pool,
-		struct core_stream *stream)
+		struct dc_stream *stream)
 {
 	struct core_dc *dc = DC_TO_CORE(stream->ctx->dc);
 	struct resource_context *res_ctx = &context->res_ctx;
@@ -1041,18 +1041,18 @@ static struct pipe_ctx *dce110_acquire_underlay(
 		 */
 
 		pipe_ctx->tg->funcs->program_timing(pipe_ctx->tg,
-				&stream->public.timing,
+				&stream->timing,
 				false);
 
 		pipe_ctx->tg->funcs->enable_advanced_request(
 				pipe_ctx->tg,
 				true,
-				&stream->public.timing);
+				&stream->timing);
 
 		pipe_ctx->mi->funcs->allocate_mem_input(pipe_ctx->mi,
-				stream->public.timing.h_total,
-				stream->public.timing.v_total,
-				stream->public.timing.pix_clk_khz,
+				stream->timing.h_total,
+				stream->timing.v_total,
+				stream->timing.pix_clk_khz,
 				context->stream_count);
 
 		color_space_to_black_color(dc,

drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.c

@@ -698,7 +698,7 @@ static void destruct(struct dce110_resource_pool *pool)
 static struct clock_source *find_matching_pll(
 		struct resource_context *res_ctx,
 		const struct resource_pool *pool,
-		const struct core_stream *const stream)
+		const struct dc_stream *const stream)
 {
 	switch (stream->sink->link->link_enc->transmitter) {
 	case TRANSMITTER_UNIPHY_A:
@@ -729,7 +729,7 @@ static enum dc_status build_mapped_resource(
 	uint8_t i, j;
 
 	for (i = 0; i < context->stream_count; i++) {
-		struct core_stream *stream = context->streams[i];
+		struct dc_stream *stream = context->streams[i];
 
 		if (old_context && resource_is_stream_unchanged(old_context, stream))
 			continue;
@@ -843,7 +843,7 @@ enum dc_status resource_map_phy_clock_resources(
 
 	/* acquire new resources */
 	for (i = 0; i < context->stream_count; i++) {
-		struct core_stream *stream = context->streams[i];
+		struct dc_stream *stream = context->streams[i];
 
 		if (old_context && resource_is_stream_unchanged(old_context, stream))
 			continue;
@@ -916,8 +916,8 @@ enum dc_status dce112_validate_with_context(
 		return DC_FAIL_SURFACE_VALIDATE;
 
 	for (i = 0; i < set_count; i++) {
-		context->streams[i] = DC_STREAM_TO_CORE(set[i].stream);
-		dc_stream_retain(&context->streams[i]->public);
+		context->streams[i] = set[i].stream;
+		dc_stream_retain(context->streams[i]);
 		context->stream_count++;
 	}
 
@@ -947,13 +947,13 @@ enum dc_status dce112_validate_with_context(
 
 enum dc_status dce112_validate_guaranteed(
 		const struct core_dc *dc,
-		const struct dc_stream *dc_stream,
+		struct dc_stream *stream,
 		struct validate_context *context)
 {
 	enum dc_status result = DC_ERROR_UNEXPECTED;
 
-	context->streams[0] = DC_STREAM_TO_CORE(dc_stream);
-	dc_stream_retain(&context->streams[0]->public);
+	context->streams[0] = stream;
+	dc_stream_retain(context->streams[0]);
 	context->stream_count++;
 
 	result = resource_map_pool_resources(dc, context, NULL);

drivers/gpu/drm/amd/display/dc/dce112/dce112_resource.h

@@ -44,7 +44,7 @@ enum dc_status dce112_validate_with_context(
 
 enum dc_status dce112_validate_guaranteed(
 		const struct core_dc *dc,
-		const struct dc_stream *dc_stream,
+		struct dc_stream *dc_stream,
 		struct validate_context *context);
 
 bool dce112_validate_bandwidth(

drivers/gpu/drm/amd/display/dc/dce80/dce80_resource.c

@@ -676,7 +676,7 @@ static enum dc_status build_mapped_resource(
 	uint8_t i, j;
 
 	for (i = 0; i < context->stream_count; i++) {
-		struct core_stream *stream = context->streams[i];
+		struct dc_stream *stream = context->streams[i];
 
 		if (old_context && resource_is_stream_unchanged(old_context, stream))
 			continue;
@@ -750,8 +750,8 @@ enum dc_status dce80_validate_with_context(
 		return DC_FAIL_SURFACE_VALIDATE;
 
 	for (i = 0; i < set_count; i++) {
-		context->streams[i] = DC_STREAM_TO_CORE(set[i].stream);
-		dc_stream_retain(&context->streams[i]->public);
+		context->streams[i] = set[i].stream;
+		dc_stream_retain(context->streams[i]);
 		context->stream_count++;
 	}
 
@@ -780,13 +780,13 @@ enum dc_status dce80_validate_with_context(
 
 enum dc_status dce80_validate_guaranteed(
 		const struct core_dc *dc,
-		const struct dc_stream *dc_stream,
+		struct dc_stream *dc_stream,
 		struct validate_context *context)
 {
 	enum dc_status result = DC_ERROR_UNEXPECTED;
 
-	context->streams[0] = DC_STREAM_TO_CORE(dc_stream);
-	dc_stream_retain(&context->streams[0]->public);
+	context->streams[0] = dc_stream;
+	dc_stream_retain(context->streams[0]);
 	context->stream_count++;
 
 	result = resource_map_pool_resources(dc, context, NULL);

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

@@ -684,12 +684,12 @@ static enum dc_status dcn10_prog_pixclk_crtc_otg(
 		struct validate_context *context,
 		struct core_dc *dc)
 {
-	struct core_stream *stream = pipe_ctx->stream;
+	struct dc_stream *stream = pipe_ctx->stream;
 	enum dc_color_space color_space;
 	struct tg_color black_color = {0};
-	bool enableStereo    = stream->public.timing.timing_3d_format == TIMING_3D_FORMAT_NONE ?
+	bool enableStereo    = stream->timing.timing_3d_format == TIMING_3D_FORMAT_NONE ?
 			false:true;
-	bool rightEyePolarity = stream->public.timing.flags.RIGHT_EYE_3D_POLARITY;
+	bool rightEyePolarity = stream->timing.flags.RIGHT_EYE_3D_POLARITY;
 
 
 	/* by upper caller loop, pipe0 is parent pipe and be called first.
@@ -722,7 +722,7 @@ static enum dc_status dcn10_prog_pixclk_crtc_otg(
 
 	pipe_ctx->tg->funcs->program_timing(
 			pipe_ctx->tg,
-			&stream->public.timing,
+			&stream->timing,
 			true);
 
 	pipe_ctx->opp->funcs->opp_set_stereo_polarity(
@@ -742,7 +742,7 @@ static enum dc_status dcn10_prog_pixclk_crtc_otg(
 				&stream->clamping);
 #endif
 	/* program otg blank color */
-	color_space = stream->public.output_color_space;
+	color_space = stream->output_color_space;
 	color_space_to_black_color(dc, color_space, &black_color);
 	pipe_ctx->tg->funcs->set_blank_color(
 			pipe_ctx->tg,
@@ -1053,16 +1053,16 @@ static bool patch_address_for_sbs_tb_stereo(
 	bool sec_split = pipe_ctx->top_pipe &&
 			pipe_ctx->top_pipe->surface == pipe_ctx->surface;
 	if (sec_split && surface->address.type == PLN_ADDR_TYPE_GRPH_STEREO &&
-		(pipe_ctx->stream->public.timing.timing_3d_format ==
+		(pipe_ctx->stream->timing.timing_3d_format ==
 		 TIMING_3D_FORMAT_SIDE_BY_SIDE ||
-		 pipe_ctx->stream->public.timing.timing_3d_format ==
+		 pipe_ctx->stream->timing.timing_3d_format ==
 		 TIMING_3D_FORMAT_TOP_AND_BOTTOM)) {
 		*addr = surface->address.grph_stereo.left_addr;
 		surface->address.grph_stereo.left_addr =
 		surface->address.grph_stereo.right_addr;
 		return true;
 	} else {
-		if (pipe_ctx->stream->public.view_format != VIEW_3D_FORMAT_NONE &&
+		if (pipe_ctx->stream->view_format != VIEW_3D_FORMAT_NONE &&
 			surface->address.type != PLN_ADDR_TYPE_GRPH_STEREO) {
 			surface->address.type = PLN_ADDR_TYPE_GRPH_STEREO;
 			surface->address.grph_stereo.right_addr =
@@ -1456,7 +1456,7 @@ static bool dcn10_translate_regamma_to_hw_format(const struct dc_transfer_func
 
 static bool dcn10_set_output_transfer_func(
 	struct pipe_ctx *pipe_ctx,
-	const struct core_stream *stream)
+	const struct dc_stream *stream)
 {
 	struct transform *xfm = pipe_ctx->xfm;
 
@@ -1465,14 +1465,14 @@ static bool dcn10_set_output_transfer_func(
 
 	xfm->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM;
 
-	if (stream->public.out_transfer_func &&
-		stream->public.out_transfer_func->type ==
+	if (stream->out_transfer_func &&
+		stream->out_transfer_func->type ==
 			TF_TYPE_PREDEFINED &&
-		stream->public.out_transfer_func->tf ==
+		stream->out_transfer_func->tf ==
 			TRANSFER_FUNCTION_SRGB) {
 		xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_SRGB);
 	} else if (dcn10_translate_regamma_to_hw_format(
-				stream->public.out_transfer_func, &xfm->regamma_params)) {
+				stream->out_transfer_func, &xfm->regamma_params)) {
 			xfm->funcs->opp_program_regamma_pwl(xfm, &xfm->regamma_params);
 			xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_USER);
 	} else {
@@ -1756,35 +1756,35 @@ static void program_gamut_remap(struct pipe_ctx *pipe_ctx)
 	adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS;
 
 
-	if (pipe_ctx->stream->public.gamut_remap_matrix.enable_remap == true) {
+	if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) {
 		adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW;
 		adjust.temperature_matrix[0] =
 				pipe_ctx->stream->
-				public.gamut_remap_matrix.matrix[0];
+				gamut_remap_matrix.matrix[0];
 		adjust.temperature_matrix[1] =
 				pipe_ctx->stream->
-				public.gamut_remap_matrix.matrix[1];
+				gamut_remap_matrix.matrix[1];
 		adjust.temperature_matrix[2] =
 				pipe_ctx->stream->
-				public.gamut_remap_matrix.matrix[2];
+				gamut_remap_matrix.matrix[2];
 		adjust.temperature_matrix[3] =
 				pipe_ctx->stream->
-				public.gamut_remap_matrix.matrix[4];
+				gamut_remap_matrix.matrix[4];
 		adjust.temperature_matrix[4] =
 				pipe_ctx->stream->
-				public.gamut_remap_matrix.matrix[5];
+				gamut_remap_matrix.matrix[5];
 		adjust.temperature_matrix[5] =
 				pipe_ctx->stream->
-				public.gamut_remap_matrix.matrix[6];
+				gamut_remap_matrix.matrix[6];
 		adjust.temperature_matrix[6] =
 				pipe_ctx->stream->
-				public.gamut_remap_matrix.matrix[8];
+				gamut_remap_matrix.matrix[8];
 		adjust.temperature_matrix[7] =
 				pipe_ctx->stream->
-				public.gamut_remap_matrix.matrix[9];
+				gamut_remap_matrix.matrix[9];
 		adjust.temperature_matrix[8] =
 				pipe_ctx->stream->
-				public.gamut_remap_matrix.matrix[10];
+				gamut_remap_matrix.matrix[10];
 	}
 
 	pipe_ctx->xfm->funcs->transform_set_gamut_remap(pipe_ctx->xfm, &adjust);
@@ -1798,14 +1798,14 @@ static void program_csc_matrix(struct pipe_ctx *pipe_ctx,
 	int i;
 	struct out_csc_color_matrix tbl_entry;
 
-	if (pipe_ctx->stream->public.csc_color_matrix.enable_adjustment
+	if (pipe_ctx->stream->csc_color_matrix.enable_adjustment
 				== true) {
 			enum dc_color_space color_space =
-				pipe_ctx->stream->public.output_color_space;
+				pipe_ctx->stream->output_color_space;
 
 			//uint16_t matrix[12];
 			for (i = 0; i < 12; i++)
-				tbl_entry.regval[i] = pipe_ctx->stream->public.csc_color_matrix.matrix[i];
+				tbl_entry.regval[i] = pipe_ctx->stream->csc_color_matrix.matrix[i];
 
 			tbl_entry.color_space = color_space;
 			//tbl_entry.regval = matrix;
@@ -1967,7 +1967,7 @@ static void update_dchubp_dpp(
 	 * pre-multiplied alpha.
 	 */
 	mpcc_cfg.pre_multiplied_alpha = is_rgb_cspace(
-			pipe_ctx->stream->public.output_color_space)
+			pipe_ctx->stream->output_color_space)
 					&& per_pixel_alpha;
 	pipe_ctx->mpcc->funcs->set(pipe_ctx->mpcc, &mpcc_cfg);
 
@@ -1975,7 +1975,7 @@ static void update_dchubp_dpp(
 		dcn10_get_surface_visual_confirm_color(pipe_ctx, &black_color);
 	} else {
 		color_space_to_black_color(
-			dc, pipe_ctx->stream->public.output_color_space,
+			dc, pipe_ctx->stream->output_color_space,
 			&black_color);
 	}
 	pipe_ctx->mpcc->funcs->set_bg_color(pipe_ctx->mpcc, &black_color);
@@ -1991,7 +1991,7 @@ static void update_dchubp_dpp(
 	program_gamut_remap(pipe_ctx);
 
 	/*TODO add adjustments parameters*/
-	ocsc.out_color_space = pipe_ctx->stream->public.output_color_space;
+	ocsc.out_color_space = pipe_ctx->stream->output_color_space;
 	pipe_ctx->xfm->funcs->opp_set_csc_default(pipe_ctx->xfm, &ocsc);
 
 	mi->funcs->mem_input_program_surface_config(
@@ -2346,11 +2346,11 @@ static void set_plane_config(
 }
 
 static void dcn10_config_stereo_parameters(
-		struct core_stream *stream, struct crtc_stereo_flags *flags)
+		struct dc_stream *stream, struct crtc_stereo_flags *flags)
 {
-	enum view_3d_format view_format = stream->public.view_format;
+	enum view_3d_format view_format = stream->view_format;
 	enum dc_timing_3d_format timing_3d_format =\
-			stream->public.timing.timing_3d_format;
+			stream->timing.timing_3d_format;
 	bool non_stereo_timing = false;
 
 	if (timing_3d_format == TIMING_3D_FORMAT_NONE ||
@@ -2374,7 +2374,7 @@ static void dcn10_config_stereo_parameters(
 				flags->DISABLE_STEREO_DP_SYNC = 1;
 		}
 		flags->RIGHT_EYE_POLARITY =\
-				stream->public.timing.flags.RIGHT_EYE_3D_POLARITY;
+				stream->timing.flags.RIGHT_EYE_3D_POLARITY;
 		if (timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
 			flags->FRAME_PACKED = 1;
 	}
@@ -2385,18 +2385,18 @@ static void dcn10_config_stereo_parameters(
 static void dcn10_setup_stereo(struct pipe_ctx *pipe_ctx, struct core_dc *dc)
 {
 	struct crtc_stereo_flags flags = { 0 };
-	struct core_stream *stream = pipe_ctx->stream;
+	struct dc_stream *stream = pipe_ctx->stream;
 
 	dcn10_config_stereo_parameters(stream, &flags);
 
 	pipe_ctx->opp->funcs->opp_set_stereo_polarity(
 		pipe_ctx->opp,
 		flags.PROGRAM_STEREO == 1 ? true:false,
-		stream->public.timing.flags.RIGHT_EYE_3D_POLARITY == 1 ? true:false);
+		stream->timing.flags.RIGHT_EYE_3D_POLARITY == 1 ? true:false);
 
 	pipe_ctx->tg->funcs->program_stereo(
 		pipe_ctx->tg,
-		&stream->public.timing,
+		&stream->timing,
 		&flags);
 
 	return;

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c

@@ -787,8 +787,8 @@ static void get_pixel_clock_parameters(
 	const struct pipe_ctx *pipe_ctx,
 	struct pixel_clk_params *pixel_clk_params)
 {
-	const struct core_stream *stream = pipe_ctx->stream;
-	pixel_clk_params->requested_pix_clk = stream->public.timing.pix_clk_khz;
+	const struct dc_stream *stream = pipe_ctx->stream;
+	pixel_clk_params->requested_pix_clk = stream->timing.pix_clk_khz;
 	pixel_clk_params->encoder_object_id = stream->sink->link->link_enc->id;
 	pixel_clk_params->signal_type = pipe_ctx->stream->signal;
 	pixel_clk_params->controller_id = pipe_ctx->pipe_idx + 1;
@@ -797,23 +797,23 @@ static void get_pixel_clock_parameters(
 		LINK_RATE_REF_FREQ_IN_KHZ;
 	pixel_clk_params->flags.ENABLE_SS = 0;
 	pixel_clk_params->color_depth =
-		stream->public.timing.display_color_depth;
+		stream->timing.display_color_depth;
 	pixel_clk_params->flags.DISPLAY_BLANKED = 1;
-	pixel_clk_params->pixel_encoding = stream->public.timing.pixel_encoding;
+	pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding;
 
-	if (stream->public.timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
+	if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
 		pixel_clk_params->color_depth = COLOR_DEPTH_888;
 
-	if (stream->public.timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
+	if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
 		pixel_clk_params->requested_pix_clk  /= 2;
 
 }
 
-static void build_clamping_params(struct core_stream *stream)
+static void build_clamping_params(struct dc_stream *stream)
 {
 	stream->clamping.clamping_level = CLAMPING_FULL_RANGE;
-	stream->clamping.c_depth = stream->public.timing.display_color_depth;
-	stream->clamping.pixel_encoding = stream->public.timing.pixel_encoding;
+	stream->clamping.c_depth = stream->timing.display_color_depth;
+	stream->clamping.pixel_encoding = stream->timing.pixel_encoding;
 }
 
 static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
@@ -826,7 +826,7 @@ static enum dc_status build_pipe_hw_param(struct pipe_ctx *pipe_ctx)
 		&pipe_ctx->pix_clk_params,
 		&pipe_ctx->pll_settings);
 
-	pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->public.timing.pixel_encoding;
+	pipe_ctx->stream->clamping.pixel_encoding = pipe_ctx->stream->timing.pixel_encoding;
 
 	resource_build_bit_depth_reduction_params(pipe_ctx->stream,
 					&pipe_ctx->stream->bit_depth_params);
@@ -844,7 +844,7 @@ static enum dc_status build_mapped_resource(
 	uint8_t i, j;
 
 	for (i = 0; i < context->stream_count; i++) {
-		struct core_stream *stream = context->streams[i];
+		struct dc_stream *stream = context->streams[i];
 
 		if (old_context && resource_is_stream_unchanged(old_context, stream)) {
 			if (stream != NULL && old_context->streams[i] != NULL) {
@@ -852,7 +852,7 @@ static enum dc_status build_mapped_resource(
 				resource_build_bit_depth_reduction_params(stream,
 						&stream->bit_depth_params);
 				stream->clamping.pixel_encoding =
-						stream->public.timing.pixel_encoding;
+						stream->timing.pixel_encoding;
 
 				resource_build_bit_depth_reduction_params(stream,
 								&stream->bit_depth_params);
@@ -896,8 +896,8 @@ enum dc_status dcn10_validate_with_context(
 		return result;
 
 	for (i = 0; i < set_count; i++) {
-		context->streams[i] = DC_STREAM_TO_CORE(set[i].stream);
-		dc_stream_retain(&context->streams[i]->public);
+		context->streams[i] = set[i].stream;
+		dc_stream_retain(context->streams[i]);
 		context->stream_count++;
 	}
 
@@ -929,13 +929,13 @@ enum dc_status dcn10_validate_with_context(
 
 enum dc_status dcn10_validate_guaranteed(
 		const struct core_dc *dc,
-		const struct dc_stream *dc_stream,
+		struct dc_stream *dc_stream,
 		struct validate_context *context)
 {
 	enum dc_status result = DC_ERROR_UNEXPECTED;
 
-	context->streams[0] = DC_STREAM_TO_CORE(dc_stream);
-	dc_stream_retain(&context->streams[0]->public);
+	context->streams[0] = dc_stream;
+	dc_stream_retain(context->streams[0]);
 	context->stream_count++;
 
 	result = resource_map_pool_resources(dc, context, NULL);
@@ -960,7 +960,7 @@ enum dc_status dcn10_validate_guaranteed(
 static struct pipe_ctx *dcn10_acquire_idle_pipe_for_layer(
 		struct validate_context *context,
 		const struct resource_pool *pool,
-		struct core_stream *stream)
+		struct dc_stream *stream)
 {
 	struct resource_context *res_ctx = &context->res_ctx;
 	struct pipe_ctx *head_pipe = resource_get_head_pipe_for_stream(res_ctx, stream);

drivers/gpu/drm/amd/display/dc/inc/core_types.h

@@ -36,41 +36,18 @@
 #include "mpc.h"
 #endif
 
-struct core_stream;
-
 #define MAX_CLOCK_SOURCES 7
 
 void enable_surface_flip_reporting(struct dc_surface *dc_surface,
 		uint32_t controller_id);
 
-/********* core_stream ************/
 #include "grph_object_id.h"
 #include "link_encoder.h"
 #include "stream_encoder.h"
 #include "clock_source.h"
 #include "audio.h"
 #include "hw_sequencer_types.h"
-#include "opp.h"
-
-#define DC_STREAM_TO_CORE(dc_stream) container_of( \
-	dc_stream, struct core_stream, public)
-
-struct core_stream {
-	struct dc_stream public;
-
-	/* field internal to DC */
-	struct dc_context *ctx;
-	struct dc_sink *sink;
 
-	/* used by DCP and FMT */
-	struct bit_depth_reduction_params bit_depth_params;
-	struct clamping_and_pixel_encoding_params clamping;
-
-	int phy_pix_clk;
-	enum signal_type signal;
-
-	struct dc_stream_status status;
-};
 
 /************ link *****************/
 struct link_init_data {
@@ -85,7 +62,7 @@ struct dc_link *link_create(const struct link_init_data *init_params);
 void link_destroy(struct dc_link **link);
 
 enum dc_status dc_link_validate_mode_timing(
-		const struct core_stream *stream,
+		const struct dc_stream *stream,
 		struct dc_link *link,
 		const struct dc_crtc_timing *timing);
 
@@ -117,7 +94,7 @@ struct resource_funcs {
 
 	enum dc_status (*validate_guaranteed)(
 					const struct core_dc *dc,
-					const struct dc_stream *stream,
+					struct dc_stream *stream,
 					struct validate_context *context);
 
 	bool (*validate_bandwidth)(
@@ -127,7 +104,7 @@ struct resource_funcs {
 	struct pipe_ctx *(*acquire_idle_pipe_for_layer)(
 			struct validate_context *context,
 			const struct resource_pool *pool,
-			struct core_stream *stream);
+			struct dc_stream *stream);
 };
 
 struct audio_support{
@@ -178,7 +155,7 @@ struct resource_pool {
 
 struct pipe_ctx {
 	struct dc_surface *surface;
-	struct core_stream *stream;
+	struct dc_stream *stream;
 
 	struct mem_input *mi;
 	struct input_pixel_processor *ipp;
@@ -264,7 +241,7 @@ union bw_context {
 };
 
 struct validate_context {
-	struct core_stream *streams[MAX_PIPES];
+	struct dc_stream *streams[MAX_PIPES];
 	struct dc_stream_status stream_status[MAX_PIPES];
 	uint8_t stream_count;
 

drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h

@@ -30,7 +30,7 @@
 #define LINK_TRAINING_RETRY_DELAY 50 /* ms */
 
 struct dc_link;
-struct core_stream;
+struct dc_stream;
 struct dc_link_settings;
 
 bool dp_hbr_verify_link_cap(
@@ -50,7 +50,7 @@ bool dp_validate_mode_timing(
 	const struct dc_crtc_timing *timing);
 
 void decide_link_settings(
-	struct core_stream *stream,
+	struct dc_stream *stream,
 	struct dc_link_settings *link_setting);
 
 bool perform_link_training_with_retries(

drivers/gpu/drm/amd/display/dc/inc/hw/link_encoder.h

@@ -17,7 +17,6 @@ struct encoder_set_dp_phy_pattern_param;
 struct link_mst_stream_allocation_table;
 struct dc_link_settings;
 struct link_training_settings;
-struct core_stream;
 struct pipe_ctx;
 
 struct encoder_init_data {
@@ -94,7 +93,7 @@ struct link_encoder {
 
 struct link_encoder_funcs {
 	bool (*validate_output_with_stream)(
-		struct link_encoder *enc, const struct core_stream *stream);
+		struct link_encoder *enc, const struct dc_stream *stream);
 	void (*hw_init)(struct link_encoder *enc);
 	void (*setup)(struct link_encoder *enc,
 		enum signal_type signal);

drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h

@@ -92,7 +92,7 @@ struct hw_sequencer_funcs {
 
 	bool (*set_output_transfer_func)(
 				struct pipe_ctx *pipe_ctx,
-				const struct core_stream *stream);
+				const struct dc_stream *stream);
 
 	void (*power_down)(struct core_dc *dc);
 

drivers/gpu/drm/amd/display/dc/inc/resource.h

@@ -103,8 +103,8 @@ void resource_reference_clock_source(
 		struct clock_source *clock_source);
 
 bool resource_are_streams_timing_synchronizable(
-		const struct core_stream *stream1,
-		const struct core_stream *stream2);
+		struct dc_stream *stream1,
+		struct dc_stream *stream2);
 
 struct clock_source *resource_find_used_clk_src_for_sharing(
 		struct resource_context *res_ctx,
@@ -116,12 +116,12 @@ struct clock_source *dc_resource_find_first_free_pll(
 
 struct pipe_ctx *resource_get_head_pipe_for_stream(
 		struct resource_context *res_ctx,
-		const struct core_stream *stream);
+		struct dc_stream *stream);
 
 bool resource_attach_surfaces_to_context(
 		struct dc_surface *const *surfaces,
 		int surface_count,
-		const struct dc_stream *dc_stream,
+		struct dc_stream *dc_stream,
 		struct validate_context *context,
 		const struct resource_pool *pool);
 
@@ -130,10 +130,10 @@ struct pipe_ctx *find_idle_secondary_pipe(
 		const struct resource_pool *pool);
 
 bool resource_is_stream_unchanged(
-	const struct validate_context *old_context, const struct core_stream *stream);
+	struct validate_context *old_context, struct dc_stream *stream);
 
 bool is_stream_unchanged(
-	const struct core_stream *old_stream, const struct core_stream *stream);
+	struct dc_stream *old_stream, struct dc_stream *stream);
 
 bool resource_validate_attach_surfaces(
 		const struct dc_validation_set set[],
@@ -164,7 +164,7 @@ bool pipe_need_reprogram(
 		struct pipe_ctx *pipe_ctx_old,
 		struct pipe_ctx *pipe_ctx);
 
-void resource_build_bit_depth_reduction_params(const struct core_stream *stream,
+void resource_build_bit_depth_reduction_params(struct dc_stream *stream,
 		struct bit_depth_reduction_params *fmt_bit_depth);
 
 #endif /* DRIVERS_GPU_DRM_AMD_DC_DEV_DC_INC_RESOURCE_H_ */

drivers/gpu/drm/amd/display/dc/virtual/virtual_link_encoder.c

@@ -30,7 +30,7 @@
 
 static bool virtual_link_encoder_validate_output_with_stream(
 	struct link_encoder *enc,
-	const struct core_stream *stream) { return true; }
+	const struct dc_stream *stream) { return true; }
 
 static void virtual_link_encoder_hw_init(struct link_encoder *enc) {}
 

drivers/gpu/drm/amd/display/modules/freesync/freesync.c

@@ -111,7 +111,7 @@ struct freesync_state {
 };
 
 struct freesync_entity {
-	const struct dc_stream *stream;
+	struct dc_stream *stream;
 	struct mod_freesync_caps *caps;
 	struct freesync_state state;
 	struct mod_freesync_user_enable user_enable;
@@ -229,7 +229,7 @@ void mod_freesync_destroy(struct mod_freesync *mod_freesync)
  * on the core_freesync->map and returns the corresponding index
  */
 static unsigned int map_index_from_stream(struct core_freesync *core_freesync,
-		const struct dc_stream *stream)
+		struct dc_stream *stream)
 {
 	unsigned int index = 0;
 
@@ -244,9 +244,8 @@ static unsigned int map_index_from_stream(struct core_freesync *core_freesync,
 }
 
 bool mod_freesync_add_stream(struct mod_freesync *mod_freesync,
-		const struct dc_stream *stream, struct mod_freesync_caps *caps)
+		struct dc_stream *stream, struct mod_freesync_caps *caps)
 {
-	struct core_stream *core_stream = NULL;
 	struct core_dc *core_dc = NULL;
 	struct core_freesync *core_freesync = NULL;
 	int persistent_freesync_enable = 0;
@@ -258,7 +257,6 @@ bool mod_freesync_add_stream(struct mod_freesync *mod_freesync,
 		return false;
 
 	core_freesync = MOD_FREESYNC_TO_CORE(mod_freesync);
-	core_stream = DC_STREAM_TO_CORE(stream);
 	core_dc = DC_TO_CORE(core_freesync->dc);
 
 	flag.save_per_edid = true;
@@ -315,7 +313,7 @@ bool mod_freesync_add_stream(struct mod_freesync *mod_freesync,
 		if (caps->supported &&
 			nom_refresh_rate_uhz >= caps->min_refresh_in_micro_hz &&
 			nom_refresh_rate_uhz <= caps->max_refresh_in_micro_hz)
-			core_stream->public.ignore_msa_timing_param = 1;
+			stream->ignore_msa_timing_param = 1;
 
 		core_freesync->num_entities++;
 		return true;
@@ -324,7 +322,7 @@ bool mod_freesync_add_stream(struct mod_freesync *mod_freesync,
 }
 
 bool mod_freesync_remove_stream(struct mod_freesync *mod_freesync,
-		const struct dc_stream *stream)
+		struct dc_stream *stream)
 {
 	int i = 0;
 	struct core_freesync *core_freesync = NULL;
@@ -346,14 +344,12 @@ bool mod_freesync_remove_stream(struct mod_freesync *mod_freesync,
 }
 
 static void update_stream_freesync_context(struct core_freesync *core_freesync,
-		const struct dc_stream *stream)
+		struct dc_stream *stream)
 {
 	unsigned int index;
 	struct freesync_context *ctx;
-	struct core_stream *core_stream;
 
-	core_stream = DC_STREAM_TO_CORE(stream);
-	ctx = &core_stream->public.freesync_ctx;
+	ctx = &stream->freesync_ctx;
 
 	index = map_index_from_stream(core_freesync, stream);
 
@@ -372,19 +368,17 @@ static void update_stream_freesync_context(struct core_freesync *core_freesync,
 }
 
 static void update_stream(struct core_freesync *core_freesync,
-		const struct dc_stream *stream)
+		struct dc_stream *stream)
 {
-	struct core_stream *core_stream = DC_STREAM_TO_CORE(stream);
-
 	unsigned int index = map_index_from_stream(core_freesync, stream);
 	if (core_freesync->map[index].caps->supported) {
-		core_stream->public.ignore_msa_timing_param = 1;
+		stream->ignore_msa_timing_param = 1;
 		update_stream_freesync_context(core_freesync, stream);
 	}
 }
 
 static void calc_freesync_range(struct core_freesync *core_freesync,
-		const struct dc_stream *stream,
+		struct dc_stream *stream,
 		struct freesync_state *state,
 		unsigned int min_refresh_in_uhz,
 		unsigned int max_refresh_in_uhz)
@@ -458,7 +452,7 @@ static void calc_freesync_range(struct core_freesync *core_freesync,
 		min_frame_duration_in_ns) / 2000;
 }
 
-static void calc_v_total_from_duration(const struct dc_stream *stream,
+static void calc_v_total_from_duration(struct dc_stream *stream,
 		unsigned int duration_in_ns, int *v_total_nominal)
 {
 	*v_total_nominal = div64_u64(div64_u64(((unsigned long long)(
@@ -467,7 +461,7 @@ static void calc_v_total_from_duration(const struct dc_stream *stream,
 }
 
 static void calc_v_total_for_static_ramp(struct core_freesync *core_freesync,
-		const struct dc_stream *stream,
+		struct dc_stream *stream,
 		unsigned int index, int *v_total)
 {
 	unsigned int frame_duration = 0;
@@ -563,7 +557,7 @@ static void reset_freesync_state_variables(struct freesync_state* state)
  * Sets freesync mode on a stream depending on current freesync state.
  */
 static bool set_freesync_on_streams(struct core_freesync *core_freesync,
-		const struct dc_stream **streams, int num_streams)
+		struct dc_stream **streams, int num_streams)
 {
 	int v_total_nominal = 0, v_total_min = 0, v_total_max = 0;
 	unsigned int stream_idx, map_index = 0;
@@ -735,7 +729,7 @@ static void set_static_ramp_variables(struct core_freesync *core_freesync,
 }
 
 void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync,
-		const struct dc_stream **streams, int num_streams)
+		struct dc_stream **streams, int num_streams)
 {
 	unsigned int index, v_total, inserted_frame_v_total = 0;
 	unsigned int min_frame_duration_in_ns, vmax, vmin = 0;
@@ -845,7 +839,7 @@ void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync,
 }
 
 void mod_freesync_update_state(struct mod_freesync *mod_freesync,
-		const struct dc_stream **streams, int num_streams,
+		struct dc_stream **streams, int num_streams,
 		struct mod_freesync_params *freesync_params)
 {
 	bool freesync_program_required = false;
@@ -935,7 +929,7 @@ void mod_freesync_update_state(struct mod_freesync *mod_freesync,
 
 
 bool mod_freesync_get_state(struct mod_freesync *mod_freesync,
-		const struct dc_stream *stream,
+		struct dc_stream *stream,
 		struct mod_freesync_params *freesync_params)
 {
 	unsigned int index = 0;
@@ -971,7 +965,7 @@ bool mod_freesync_get_state(struct mod_freesync *mod_freesync,
 }
 
 bool mod_freesync_set_user_enable(struct mod_freesync *mod_freesync,
-		const struct dc_stream **streams, int num_streams,
+		struct dc_stream **streams, int num_streams,
 		struct mod_freesync_user_enable *user_enable)
 {
 	unsigned int stream_index, map_index;
@@ -1023,7 +1017,7 @@ bool mod_freesync_set_user_enable(struct mod_freesync *mod_freesync,
 }
 
 bool mod_freesync_get_user_enable(struct mod_freesync *mod_freesync,
-		const struct dc_stream *stream,
+		struct dc_stream *stream,
 		struct mod_freesync_user_enable *user_enable)
 {
 	unsigned int index = 0;
@@ -1041,7 +1035,7 @@ bool mod_freesync_get_user_enable(struct mod_freesync *mod_freesync,
 }
 
 bool mod_freesync_get_static_ramp_active(struct mod_freesync *mod_freesync,
-		const struct dc_stream *stream,
+		struct dc_stream *stream,
 		bool *is_ramp_active)
 {
 	unsigned int index = 0;
@@ -1060,7 +1054,7 @@ bool mod_freesync_get_static_ramp_active(struct mod_freesync *mod_freesync,
 }
 
 bool mod_freesync_override_min_max(struct mod_freesync *mod_freesync,
-		const struct dc_stream *streams,
+		struct dc_stream *streams,
 		unsigned int min_refresh,
 		unsigned int max_refresh,
 		struct mod_freesync_caps *caps)
@@ -1113,7 +1107,7 @@ bool mod_freesync_override_min_max(struct mod_freesync *mod_freesync,
 }
 
 bool mod_freesync_get_min_max(struct mod_freesync *mod_freesync,
-		const struct dc_stream *stream,
+		struct dc_stream *stream,
 		unsigned int *min_refresh,
 		unsigned int *max_refresh)
 {
@@ -1135,7 +1129,7 @@ bool mod_freesync_get_min_max(struct mod_freesync *mod_freesync,
 }
 
 bool mod_freesync_get_vmin_vmax(struct mod_freesync *mod_freesync,
-		const struct dc_stream *stream,
+		struct dc_stream *stream,
 		unsigned int *vmin,
 		unsigned int *vmax)
 {
@@ -1157,7 +1151,7 @@ bool mod_freesync_get_vmin_vmax(struct mod_freesync *mod_freesync,
 }
 
 bool mod_freesync_get_v_position(struct mod_freesync *mod_freesync,
-		const struct dc_stream *stream,
+		struct dc_stream *stream,
 		unsigned int *nom_v_pos,
 		unsigned int *v_pos)
 {
@@ -1185,7 +1179,7 @@ bool mod_freesync_get_v_position(struct mod_freesync *mod_freesync,
 }
 
 void mod_freesync_notify_mode_change(struct mod_freesync *mod_freesync,
-		const struct dc_stream **streams, int num_streams)
+		struct dc_stream **streams, int num_streams)
 {
 	unsigned int stream_index, map_index;
 	struct freesync_state *state;
@@ -1310,7 +1304,7 @@ static void update_timestamps(struct core_freesync *core_freesync,
 }
 
 static void apply_below_the_range(struct core_freesync *core_freesync,
-		const struct dc_stream *stream, unsigned int map_index,
+		struct dc_stream *stream, unsigned int map_index,
 		unsigned int last_render_time_in_us)
 {
 	unsigned int inserted_frame_duration_in_us = 0;
@@ -1409,7 +1403,7 @@ static void apply_below_the_range(struct core_freesync *core_freesync,
 }
 
 static void apply_fixed_refresh(struct core_freesync *core_freesync,
-		const struct dc_stream *stream, unsigned int map_index)
+		struct dc_stream *stream, unsigned int map_index)
 {
 	unsigned int vmin = 0, vmax = 0;
 	struct freesync_state *state = &core_freesync->map[map_index].state;
@@ -1440,7 +1434,7 @@ static void apply_fixed_refresh(struct core_freesync *core_freesync,
 }
 
 void mod_freesync_pre_update_plane_addresses(struct mod_freesync *mod_freesync,
-		const struct dc_stream **streams, int num_streams,
+		struct dc_stream **streams, int num_streams,
 		unsigned int curr_time_stamp_in_us)
 {
 	unsigned int stream_index, map_index, last_render_time_in_us = 0;

drivers/gpu/drm/amd/display/modules/inc/mod_freesync.h

@@ -101,67 +101,67 @@ struct mod_freesync_params {
  * Add stream to be tracked by module
  */
 bool mod_freesync_add_stream(struct mod_freesync *mod_freesync,
-		const struct dc_stream *stream, struct mod_freesync_caps *caps);
+		struct dc_stream *stream, struct mod_freesync_caps *caps);
 
 /*
  * Remove stream to be tracked by module
  */
 bool mod_freesync_remove_stream(struct mod_freesync *mod_freesync,
-		const struct dc_stream *stream);
+		struct dc_stream *stream);
 
 /*
  * Update the freesync state flags for each display and program
  * freesync accordingly
  */
 void mod_freesync_update_state(struct mod_freesync *mod_freesync,
-		const struct dc_stream **streams, int num_streams,
+		struct dc_stream **streams, int num_streams,
 		struct mod_freesync_params *freesync_params);
 
 bool mod_freesync_get_state(struct mod_freesync *mod_freesync,
-		const struct dc_stream *stream,
+		struct dc_stream *stream,
 		struct mod_freesync_params *freesync_params);
 
 bool mod_freesync_set_user_enable(struct mod_freesync *mod_freesync,
-		const struct dc_stream **streams, int num_streams,
+		struct dc_stream **streams, int num_streams,
 		struct mod_freesync_user_enable *user_enable);
 
 bool mod_freesync_get_user_enable(struct mod_freesync *mod_freesync,
-		const struct dc_stream *stream,
+		struct dc_stream *stream,
 		struct mod_freesync_user_enable *user_enable);
 
 bool mod_freesync_get_static_ramp_active(struct mod_freesync *mod_freesync,
-		const struct dc_stream *stream,
+		struct dc_stream *stream,
 		bool *is_ramp_active);
 
 bool mod_freesync_override_min_max(struct mod_freesync *mod_freesync,
-		const struct dc_stream *streams,
+		struct dc_stream *streams,
 		unsigned int min_refresh,
 		unsigned int max_refresh,
 		struct mod_freesync_caps *caps);
 
 bool mod_freesync_get_min_max(struct mod_freesync *mod_freesync,
-		const struct dc_stream *stream,
+		struct dc_stream *stream,
 		unsigned int *min_refresh,
 		unsigned int *max_refresh);
 
 bool mod_freesync_get_vmin_vmax(struct mod_freesync *mod_freesync,
-		const struct dc_stream *stream,
+		struct dc_stream *stream,
 		unsigned int *vmin,
 		unsigned int *vmax);
 
 bool mod_freesync_get_v_position(struct mod_freesync *mod_freesync,
-		const struct dc_stream *stream,
+		struct dc_stream *stream,
 		unsigned int *nom_v_pos,
 		unsigned int *v_pos);
 
 void mod_freesync_handle_v_update(struct mod_freesync *mod_freesync,
-		const struct dc_stream **streams, int num_streams);
+		struct dc_stream **streams, int num_streams);
 
 void mod_freesync_notify_mode_change(struct mod_freesync *mod_freesync,
-		const struct dc_stream **streams, int num_streams);
+		struct dc_stream **streams, int num_streams);
 
 void mod_freesync_pre_update_plane_addresses(struct mod_freesync *mod_freesync,
-		const struct dc_stream **streams, int num_streams,
+		struct dc_stream **streams, int num_streams,
 		unsigned int curr_time_stamp);
 
 #endif