Commit 503275bf authored by Yijing Wang's avatar Yijing Wang Committed by Bjorn Helgaas

tile/PCI: use cached pci_dev->pcie_mpss to simplify code

The PCI core caches the "PCIe Max Payload Size Supported" in
pci_dev->pcie_mpss, so use that instead of pcie_capability_read_dword().
Signed-off-by: default avatarYijing Wang <wangyijing@huawei.com>
Signed-off-by: default avatarBjorn Helgaas <bhelgaas@google.com>
parent f1c66c46
...@@ -251,15 +251,12 @@ static void fixup_read_and_payload_sizes(void) ...@@ -251,15 +251,12 @@ static void fixup_read_and_payload_sizes(void)
/* Scan for the smallest maximum payload size. */ /* Scan for the smallest maximum payload size. */
for_each_pci_dev(dev) { for_each_pci_dev(dev) {
u32 devcap; u32 devcap;
int max_payload;
if (!pci_is_pcie(dev)) if (!pci_is_pcie(dev))
continue; continue;
pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &devcap); if (dev->pcie_mpss < smallest_max_payload)
max_payload = devcap & PCI_EXP_DEVCAP_PAYLOAD; smallest_max_payload = dev->pcie_mpss;
if (max_payload < smallest_max_payload)
smallest_max_payload = max_payload;
} }
/* Now, set the max_payload_size for all devices to that value. */ /* Now, set the max_payload_size for all devices to that value. */
......
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