Commit 50ca903a authored by Niklas Cassel's avatar Niklas Cassel Committed by David S. Miller

net: stmmac: simplify the common DMA init API

Use struct stmmac_dma_cfg *dma_cfg as an argument rather
than using all the struct members as individual arguments.
Signed-off-by: default avatarNiklas Cassel <niklas.cassel@axis.com>
Acked-by: default avatarAlexandre Torgue <alexandre.torgue@st.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 89ab75bf
...@@ -412,8 +412,8 @@ extern const struct stmmac_desc_ops ndesc_ops; ...@@ -412,8 +412,8 @@ extern const struct stmmac_desc_ops ndesc_ops;
struct stmmac_dma_ops { struct stmmac_dma_ops {
/* DMA core initialization */ /* DMA core initialization */
int (*reset)(void __iomem *ioaddr); int (*reset)(void __iomem *ioaddr);
void (*init)(void __iomem *ioaddr, int pbl, int fb, int mb, void (*init)(void __iomem *ioaddr, struct stmmac_dma_cfg *dma_cfg,
int aal, u32 dma_tx, u32 dma_rx, int atds); u32 dma_tx, u32 dma_rx, int atds);
/* Configure the AXI Bus Mode Register */ /* Configure the AXI Bus Mode Register */
void (*axi)(void __iomem *ioaddr, struct stmmac_axi *axi); void (*axi)(void __iomem *ioaddr, struct stmmac_axi *axi);
/* Dump DMA registers */ /* Dump DMA registers */
......
...@@ -84,8 +84,9 @@ static void dwmac1000_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi) ...@@ -84,8 +84,9 @@ static void dwmac1000_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi)
writel(value, ioaddr + DMA_AXI_BUS_MODE); writel(value, ioaddr + DMA_AXI_BUS_MODE);
} }
static void dwmac1000_dma_init(void __iomem *ioaddr, int pbl, int fb, int mb, static void dwmac1000_dma_init(void __iomem *ioaddr,
int aal, u32 dma_tx, u32 dma_rx, int atds) struct stmmac_dma_cfg *dma_cfg,
u32 dma_tx, u32 dma_rx, int atds)
{ {
u32 value = readl(ioaddr + DMA_BUS_MODE); u32 value = readl(ioaddr + DMA_BUS_MODE);
...@@ -101,20 +102,20 @@ static void dwmac1000_dma_init(void __iomem *ioaddr, int pbl, int fb, int mb, ...@@ -101,20 +102,20 @@ static void dwmac1000_dma_init(void __iomem *ioaddr, int pbl, int fb, int mb,
*/ */
value |= DMA_BUS_MODE_MAXPBL; value |= DMA_BUS_MODE_MAXPBL;
value &= ~DMA_BUS_MODE_PBL_MASK; value &= ~DMA_BUS_MODE_PBL_MASK;
value |= (pbl << DMA_BUS_MODE_PBL_SHIFT); value |= (dma_cfg->pbl << DMA_BUS_MODE_PBL_SHIFT);
/* Set the Fixed burst mode */ /* Set the Fixed burst mode */
if (fb) if (dma_cfg->fixed_burst)
value |= DMA_BUS_MODE_FB; value |= DMA_BUS_MODE_FB;
/* Mixed Burst has no effect when fb is set */ /* Mixed Burst has no effect when fb is set */
if (mb) if (dma_cfg->mixed_burst)
value |= DMA_BUS_MODE_MB; value |= DMA_BUS_MODE_MB;
if (atds) if (atds)
value |= DMA_BUS_MODE_ATDS; value |= DMA_BUS_MODE_ATDS;
if (aal) if (dma_cfg->aal)
value |= DMA_BUS_MODE_AAL; value |= DMA_BUS_MODE_AAL;
writel(value, ioaddr + DMA_BUS_MODE); writel(value, ioaddr + DMA_BUS_MODE);
......
...@@ -32,11 +32,12 @@ ...@@ -32,11 +32,12 @@
#include "dwmac100.h" #include "dwmac100.h"
#include "dwmac_dma.h" #include "dwmac_dma.h"
static void dwmac100_dma_init(void __iomem *ioaddr, int pbl, int fb, int mb, static void dwmac100_dma_init(void __iomem *ioaddr,
int aal, u32 dma_tx, u32 dma_rx, int atds) struct stmmac_dma_cfg *dma_cfg,
u32 dma_tx, u32 dma_rx, int atds)
{ {
/* Enable Application Access by writing to DMA CSR0 */ /* Enable Application Access by writing to DMA CSR0 */
writel(DMA_BUS_MODE_DEFAULT | (pbl << DMA_BUS_MODE_PBL_SHIFT), writel(DMA_BUS_MODE_DEFAULT | (dma_cfg->pbl << DMA_BUS_MODE_PBL_SHIFT),
ioaddr + DMA_BUS_MODE); ioaddr + DMA_BUS_MODE);
/* Mask interrupts by writing to CSR7 */ /* Mask interrupts by writing to CSR7 */
......
...@@ -99,27 +99,29 @@ static void dwmac4_dma_init_channel(void __iomem *ioaddr, int pbl, ...@@ -99,27 +99,29 @@ static void dwmac4_dma_init_channel(void __iomem *ioaddr, int pbl,
writel(dma_rx_phy, ioaddr + DMA_CHAN_RX_BASE_ADDR(channel)); writel(dma_rx_phy, ioaddr + DMA_CHAN_RX_BASE_ADDR(channel));
} }
static void dwmac4_dma_init(void __iomem *ioaddr, int pbl, int fb, int mb, static void dwmac4_dma_init(void __iomem *ioaddr,
int aal, u32 dma_tx, u32 dma_rx, int atds) struct stmmac_dma_cfg *dma_cfg,
u32 dma_tx, u32 dma_rx, int atds)
{ {
u32 value = readl(ioaddr + DMA_SYS_BUS_MODE); u32 value = readl(ioaddr + DMA_SYS_BUS_MODE);
int i; int i;
/* Set the Fixed burst mode */ /* Set the Fixed burst mode */
if (fb) if (dma_cfg->fixed_burst)
value |= DMA_SYS_BUS_FB; value |= DMA_SYS_BUS_FB;
/* Mixed Burst has no effect when fb is set */ /* Mixed Burst has no effect when fb is set */
if (mb) if (dma_cfg->mixed_burst)
value |= DMA_SYS_BUS_MB; value |= DMA_SYS_BUS_MB;
if (aal) if (dma_cfg->aal)
value |= DMA_SYS_BUS_AAL; value |= DMA_SYS_BUS_AAL;
writel(value, ioaddr + DMA_SYS_BUS_MODE); writel(value, ioaddr + DMA_SYS_BUS_MODE);
for (i = 0; i < DMA_CHANNEL_NB_MAX; i++) for (i = 0; i < DMA_CHANNEL_NB_MAX; i++)
dwmac4_dma_init_channel(ioaddr, pbl, dma_tx, dma_rx, i); dwmac4_dma_init_channel(ioaddr, dma_cfg->pbl,
dma_tx, dma_rx, i);
} }
static void _dwmac4_dump_dma_regs(void __iomem *ioaddr, u32 channel) static void _dwmac4_dump_dma_regs(void __iomem *ioaddr, u32 channel)
......
...@@ -1595,11 +1595,7 @@ static int stmmac_init_dma_engine(struct stmmac_priv *priv) ...@@ -1595,11 +1595,7 @@ static int stmmac_init_dma_engine(struct stmmac_priv *priv)
return ret; return ret;
} }
priv->hw->dma->init(priv->ioaddr, priv->hw->dma->init(priv->ioaddr, priv->plat->dma_cfg,
priv->plat->dma_cfg->pbl,
priv->plat->dma_cfg->fixed_burst,
priv->plat->dma_cfg->mixed_burst,
priv->plat->dma_cfg->aal,
priv->dma_tx_phy, priv->dma_rx_phy, atds); priv->dma_tx_phy, priv->dma_rx_phy, atds);
if (priv->synopsys_id >= DWMAC_CORE_4_00) { if (priv->synopsys_id >= DWMAC_CORE_4_00) {
......
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